2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
14 #include <linux/err.h>
15 #include <linux/slab.h>
19 * struct clk_div - mxs integer divider clock
20 * @divider: the parent class
21 * @ops: pointer to clk_ops of parent class
22 * @reg: register address
23 * @busy: busy bit shift
25 * The mxs divider clock is a subclass of basic clk_divider with an
29 struct clk_divider divider;
30 const struct clk_ops *ops;
35 static inline struct clk_div *to_clk_div(struct clk_hw *hw)
37 struct clk_divider *divider = container_of(hw, struct clk_divider, hw);
39 return container_of(divider, struct clk_div, divider);
42 static unsigned long clk_div_recalc_rate(struct clk_hw *hw,
43 unsigned long parent_rate)
45 struct clk_div *div = to_clk_div(hw);
47 return div->ops->recalc_rate(&div->divider.hw, parent_rate);
50 static long clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
53 struct clk_div *div = to_clk_div(hw);
55 return div->ops->round_rate(&div->divider.hw, rate, prate);
58 static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
59 unsigned long parent_rate)
61 struct clk_div *div = to_clk_div(hw);
64 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate);
66 ret = mxs_clk_wait(div->reg, div->busy);
71 static struct clk_ops clk_div_ops = {
72 .recalc_rate = clk_div_recalc_rate,
73 .round_rate = clk_div_round_rate,
74 .set_rate = clk_div_set_rate,
77 struct clk *mxs_clk_div(const char *name, const char *parent_name,
78 void __iomem *reg, u8 shift, u8 width, u8 busy)
82 struct clk_init_data init;
84 div = kzalloc(sizeof(*div), GFP_KERNEL);
86 return ERR_PTR(-ENOMEM);
89 init.ops = &clk_div_ops;
90 init.flags = CLK_SET_RATE_PARENT;
91 init.parent_names = (parent_name ? &parent_name: NULL);
92 init.num_parents = (parent_name ? 1 : 0);
97 div->divider.reg = reg;
98 div->divider.shift = shift;
99 div->divider.width = width;
100 div->divider.flags = CLK_DIVIDER_ONE_BASED;
101 div->divider.lock = &mxs_lock;
102 div->divider.hw.init = &init;
103 div->ops = &clk_divider_ops;
105 clk = clk_register(NULL, &div->divider.hw);