2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/export.h>
16 #include <linux/clk-provider.h>
17 #include <linux/regmap.h>
18 #include <linux/delay.h>
20 #include "clk-alpha-pll.h"
24 # define PLL_OUTCTRL BIT(0)
25 # define PLL_BYPASSNL BIT(1)
26 # define PLL_RESET_N BIT(2)
27 # define PLL_OFFLINE_REQ BIT(7)
28 # define PLL_LOCK_COUNT_SHIFT 8
29 # define PLL_LOCK_COUNT_MASK 0x3f
30 # define PLL_BIAS_COUNT_SHIFT 14
31 # define PLL_BIAS_COUNT_MASK 0x3f
32 # define PLL_VOTE_FSM_ENA BIT(20)
33 # define PLL_FSM_ENA BIT(20)
34 # define PLL_VOTE_FSM_RESET BIT(21)
35 # define PLL_OFFLINE_ACK BIT(28)
36 # define PLL_ACTIVE_FLAG BIT(30)
37 # define PLL_LOCK_DET BIT(31)
39 #define PLL_L_VAL 0x04
40 #define PLL_ALPHA_VAL 0x08
41 #define PLL_ALPHA_VAL_U 0x0c
43 #define PLL_USER_CTL 0x10
44 # define PLL_POST_DIV_SHIFT 8
45 # define PLL_POST_DIV_MASK 0xf
46 # define PLL_ALPHA_EN BIT(24)
47 # define PLL_VCO_SHIFT 20
48 # define PLL_VCO_MASK 0x3
50 #define PLL_USER_CTL_U 0x14
52 #define PLL_CONFIG_CTL 0x18
53 #define PLL_CONFIG_CTL_U 0x20
54 #define PLL_TEST_CTL 0x1c
55 #define PLL_TEST_CTL_U 0x20
56 #define PLL_STATUS 0x24
59 * Even though 40 bits are present, use only 32 for ease of calculation.
61 #define ALPHA_REG_BITWIDTH 40
62 #define ALPHA_BITWIDTH 32
63 #define ALPHA_16BIT_MASK 0xffff
65 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
66 struct clk_alpha_pll, clkr)
68 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
69 struct clk_alpha_pll_postdiv, clkr)
71 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
77 const char *name = clk_hw_get_name(&pll->clkr.hw);
80 ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
84 for (count = 100; count > 0; count--) {
85 ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
88 if (inverse && !(val & mask))
90 else if ((val & mask) == mask)
96 WARN(1, "%s failed to %s!\n", name, action);
100 #define wait_for_pll_enable_active(pll) \
101 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
103 #define wait_for_pll_enable_lock(pll) \
104 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
106 #define wait_for_pll_disable(pll) \
107 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
109 #define wait_for_pll_offline(pll) \
110 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
112 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
113 const struct alpha_pll_config *config)
116 u32 off = pll->offset;
118 regmap_write(regmap, off + PLL_L_VAL, config->l);
119 regmap_write(regmap, off + PLL_ALPHA_VAL, config->alpha);
120 regmap_write(regmap, off + PLL_CONFIG_CTL, config->config_ctl_val);
121 regmap_write(regmap, off + PLL_CONFIG_CTL_U, config->config_ctl_hi_val);
123 val = config->main_output_mask;
124 val |= config->aux_output_mask;
125 val |= config->aux2_output_mask;
126 val |= config->early_output_mask;
127 val |= config->pre_div_val;
128 val |= config->post_div_val;
129 val |= config->vco_val;
131 mask = config->main_output_mask;
132 mask |= config->aux_output_mask;
133 mask |= config->aux2_output_mask;
134 mask |= config->early_output_mask;
135 mask |= config->pre_div_mask;
136 mask |= config->post_div_mask;
137 mask |= config->vco_mask;
139 regmap_update_bits(regmap, off + PLL_USER_CTL, mask, val);
141 if (pll->flags & SUPPORTS_FSM_MODE)
142 qcom_pll_set_fsm_mode(regmap, off + PLL_MODE, 6, 0);
145 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
149 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
152 ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
158 if (pll->flags & SUPPORTS_OFFLINE_REQ)
159 val &= ~PLL_OFFLINE_REQ;
161 ret = regmap_write(pll->clkr.regmap, off + PLL_MODE, val);
165 /* Make sure enable request goes through before waiting for update */
168 return wait_for_pll_enable_active(pll);
171 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
175 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
178 ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
182 if (pll->flags & SUPPORTS_OFFLINE_REQ) {
183 ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
184 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
188 ret = wait_for_pll_offline(pll);
194 ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
199 wait_for_pll_disable(pll);
202 static int pll_is_enabled(struct clk_hw *hw, u32 mask)
206 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
209 ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
213 return !!(val & mask);
216 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
218 return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
221 static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
223 return pll_is_enabled(hw, PLL_LOCK_DET);
226 static int clk_alpha_pll_enable(struct clk_hw *hw)
229 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
234 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
235 ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
239 /* If in FSM mode, just vote for it */
240 if (val & PLL_VOTE_FSM_ENA) {
241 ret = clk_enable_regmap(hw);
244 return wait_for_pll_enable_active(pll);
247 /* Skip if already enabled */
248 if ((val & mask) == mask)
251 ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
252 PLL_BYPASSNL, PLL_BYPASSNL);
257 * H/W requires a 5us delay between disabling the bypass and
258 * de-asserting the reset.
263 ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
264 PLL_RESET_N, PLL_RESET_N);
268 ret = wait_for_pll_enable_lock(pll);
272 ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
273 PLL_OUTCTRL, PLL_OUTCTRL);
275 /* Ensure that the write above goes through before returning. */
280 static void clk_alpha_pll_disable(struct clk_hw *hw)
283 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
288 ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
292 /* If in FSM mode, just unvote it */
293 if (val & PLL_VOTE_FSM_ENA) {
294 clk_disable_regmap(hw);
299 regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0);
301 /* Delay of 2 output clock ticks required until output is disabled */
305 mask = PLL_RESET_N | PLL_BYPASSNL;
306 regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0);
309 static unsigned long alpha_pll_calc_rate(u64 prate, u32 l, u32 a)
311 return (prate * l) + ((prate * a) >> ALPHA_BITWIDTH);
315 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a)
321 remainder = do_div(quotient, prate);
329 /* Upper ALPHA_BITWIDTH bits of Alpha */
330 quotient = remainder << ALPHA_BITWIDTH;
331 remainder = do_div(quotient, prate);
337 return alpha_pll_calc_rate(prate, *l, *a);
340 static const struct pll_vco *
341 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
343 const struct pll_vco *v = pll->vco_table;
344 const struct pll_vco *end = v + pll->num_vco;
347 if (rate >= v->min_freq && rate <= v->max_freq)
354 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
356 u32 l, low, high, ctl;
357 u64 a = 0, prate = parent_rate;
358 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
359 u32 off = pll->offset;
361 regmap_read(pll->clkr.regmap, off + PLL_L_VAL, &l);
363 regmap_read(pll->clkr.regmap, off + PLL_USER_CTL, &ctl);
364 if (ctl & PLL_ALPHA_EN) {
365 regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL, &low);
366 if (pll->flags & SUPPORTS_16BIT_ALPHA) {
367 a = low & ALPHA_16BIT_MASK;
369 regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL_U,
371 a = (u64)high << 32 | low;
372 a >>= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
376 return alpha_pll_calc_rate(prate, l, a);
379 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
382 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
383 const struct pll_vco *vco;
384 u32 l, off = pll->offset;
387 rate = alpha_pll_round_rate(rate, prate, &l, &a);
388 vco = alpha_pll_find_vco(pll, rate);
390 pr_err("alpha pll not in a valid vco range\n");
394 regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l);
396 if (pll->flags & SUPPORTS_16BIT_ALPHA) {
397 regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL,
398 a & ALPHA_16BIT_MASK);
400 a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);
401 regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, a >> 32);
404 regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL,
405 PLL_VCO_MASK << PLL_VCO_SHIFT,
406 vco->val << PLL_VCO_SHIFT);
408 regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL, PLL_ALPHA_EN,
414 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
415 unsigned long *prate)
417 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
420 unsigned long min_freq, max_freq;
422 rate = alpha_pll_round_rate(rate, *prate, &l, &a);
423 if (alpha_pll_find_vco(pll, rate))
426 min_freq = pll->vco_table[0].min_freq;
427 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
429 return clamp(rate, min_freq, max_freq);
432 const struct clk_ops clk_alpha_pll_ops = {
433 .enable = clk_alpha_pll_enable,
434 .disable = clk_alpha_pll_disable,
435 .is_enabled = clk_alpha_pll_is_enabled,
436 .recalc_rate = clk_alpha_pll_recalc_rate,
437 .round_rate = clk_alpha_pll_round_rate,
438 .set_rate = clk_alpha_pll_set_rate,
440 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
442 const struct clk_ops clk_alpha_pll_hwfsm_ops = {
443 .enable = clk_alpha_pll_hwfsm_enable,
444 .disable = clk_alpha_pll_hwfsm_disable,
445 .is_enabled = clk_alpha_pll_hwfsm_is_enabled,
446 .recalc_rate = clk_alpha_pll_recalc_rate,
447 .round_rate = clk_alpha_pll_round_rate,
448 .set_rate = clk_alpha_pll_set_rate,
450 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
453 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
455 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
458 regmap_read(pll->clkr.regmap, pll->offset + PLL_USER_CTL, &ctl);
460 ctl >>= PLL_POST_DIV_SHIFT;
461 ctl &= PLL_POST_DIV_MASK;
463 return parent_rate >> fls(ctl);
466 static const struct clk_div_table clk_alpha_div_table[] = {
476 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
477 unsigned long *prate)
479 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
481 return divider_round_rate(hw, rate, prate, clk_alpha_div_table,
482 pll->width, CLK_DIVIDER_POWER_OF_TWO);
485 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
486 unsigned long parent_rate)
488 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
491 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
492 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
494 return regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_USER_CTL,
495 PLL_POST_DIV_MASK << PLL_POST_DIV_SHIFT,
496 div << PLL_POST_DIV_SHIFT);
499 const struct clk_ops clk_alpha_pll_postdiv_ops = {
500 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
501 .round_rate = clk_alpha_pll_postdiv_round_rate,
502 .set_rate = clk_alpha_pll_postdiv_set_rate,
504 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);