2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/bug.h>
18 #include <linux/delay.h>
19 #include <linux/export.h>
20 #include <linux/clk-provider.h>
21 #include <linux/regmap.h>
23 #include <asm/div64.h>
28 #define PLL_OUTCTRL BIT(0)
29 #define PLL_BYPASSNL BIT(1)
30 #define PLL_RESET_N BIT(2)
32 static int clk_pll_enable(struct clk_hw *hw)
34 struct clk_pll *pll = to_clk_pll(hw);
38 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
39 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
43 /* Skip if already enabled or in FSM mode */
44 if ((val & mask) == mask || val & PLL_VOTE_FSM_ENA)
47 /* Disable PLL bypass mode. */
48 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
54 * H/W requires a 5us delay between disabling the bypass and
55 * de-asserting the reset. Delay 10us just to be safe.
59 /* De-assert active-low PLL reset. */
60 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
65 /* Wait until PLL is locked. */
68 /* Enable PLL output. */
69 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
73 static void clk_pll_disable(struct clk_hw *hw)
75 struct clk_pll *pll = to_clk_pll(hw);
79 regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
80 /* Skip if in FSM mode */
81 if (val & PLL_VOTE_FSM_ENA)
83 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
84 regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0);
88 clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
90 struct clk_pll *pll = to_clk_pll(hw);
95 regmap_read(pll->clkr.regmap, pll->l_reg, &l);
96 regmap_read(pll->clkr.regmap, pll->m_reg, &m);
97 regmap_read(pll->clkr.regmap, pll->n_reg, &n);
103 rate = parent_rate * l;
110 if (pll->post_div_width) {
111 regmap_read(pll->clkr.regmap, pll->config_reg, &config);
112 config >>= pll->post_div_shift;
113 config &= BIT(pll->post_div_width) - 1;
121 struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate)
134 clk_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
136 struct clk_pll *pll = to_clk_pll(hw);
137 const struct pll_freq_tbl *f;
139 f = find_freq(pll->freq_tbl, req->rate);
141 req->rate = clk_pll_recalc_rate(hw, req->best_parent_rate);
149 clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate)
151 struct clk_pll *pll = to_clk_pll(hw);
152 const struct pll_freq_tbl *f;
155 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
157 f = find_freq(pll->freq_tbl, rate);
161 regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
162 enabled = (mode & enable_mask) == enable_mask;
167 regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
168 regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
169 regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
170 regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);
178 const struct clk_ops clk_pll_ops = {
179 .enable = clk_pll_enable,
180 .disable = clk_pll_disable,
181 .recalc_rate = clk_pll_recalc_rate,
182 .determine_rate = clk_pll_determine_rate,
183 .set_rate = clk_pll_set_rate,
185 EXPORT_SYMBOL_GPL(clk_pll_ops);
187 static int wait_for_pll(struct clk_pll *pll)
192 const char *name = clk_hw_get_name(&pll->clkr.hw);
194 /* Wait for pll to enable. */
195 for (count = 200; count > 0; count--) {
196 ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);
199 if (val & BIT(pll->status_bit))
204 WARN(1, "%s didn't enable after voting for it!\n", name);
208 static int clk_pll_vote_enable(struct clk_hw *hw)
211 struct clk_pll *p = to_clk_pll(clk_hw_get_parent(hw));
213 ret = clk_enable_regmap(hw);
217 return wait_for_pll(p);
220 const struct clk_ops clk_pll_vote_ops = {
221 .enable = clk_pll_vote_enable,
222 .disable = clk_disable_regmap,
224 EXPORT_SYMBOL_GPL(clk_pll_vote_ops);
226 static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
227 const struct pll_config *config)
232 regmap_write(regmap, pll->l_reg, config->l);
233 regmap_write(regmap, pll->m_reg, config->m);
234 regmap_write(regmap, pll->n_reg, config->n);
236 val = config->vco_val;
237 val |= config->pre_div_val;
238 val |= config->post_div_val;
239 val |= config->mn_ena_mask;
240 val |= config->main_output_mask;
241 val |= config->aux_output_mask;
243 mask = config->vco_mask;
244 mask |= config->pre_div_mask;
245 mask |= config->post_div_mask;
246 mask |= config->mn_ena_mask;
247 mask |= config->main_output_mask;
248 mask |= config->aux_output_mask;
250 regmap_update_bits(regmap, pll->config_reg, mask, val);
253 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
254 const struct pll_config *config, bool fsm_mode)
256 clk_pll_configure(pll, regmap, config);
258 qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 8);
260 EXPORT_SYMBOL_GPL(clk_pll_configure_sr);
262 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
263 const struct pll_config *config, bool fsm_mode)
265 clk_pll_configure(pll, regmap, config);
267 qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 0);
269 EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp);
271 static int clk_pll_sr2_enable(struct clk_hw *hw)
273 struct clk_pll *pll = to_clk_pll(hw);
277 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
281 /* Disable PLL bypass mode. */
282 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
288 * H/W requires a 5us delay between disabling the bypass and
289 * de-asserting the reset. Delay 10us just to be safe.
293 /* De-assert active-low PLL reset. */
294 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
299 ret = wait_for_pll(pll);
303 /* Enable PLL output. */
304 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
309 clk_pll_sr2_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
311 struct clk_pll *pll = to_clk_pll(hw);
312 const struct pll_freq_tbl *f;
315 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
317 f = find_freq(pll->freq_tbl, rate);
321 regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
322 enabled = (mode & enable_mask) == enable_mask;
327 regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
328 regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
329 regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
332 clk_pll_sr2_enable(hw);
337 const struct clk_ops clk_pll_sr2_ops = {
338 .enable = clk_pll_sr2_enable,
339 .disable = clk_pll_disable,
340 .set_rate = clk_pll_sr2_set_rate,
341 .recalc_rate = clk_pll_recalc_rate,
342 .determine_rate = clk_pll_determine_rate,
344 EXPORT_SYMBOL_GPL(clk_pll_sr2_ops);