2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/bug.h>
18 #include <linux/export.h>
19 #include <linux/clk-provider.h>
20 #include <linux/delay.h>
21 #include <linux/regmap.h>
22 #include <linux/math64.h>
24 #include <asm/div64.h>
30 #define CMD_UPDATE BIT(0)
31 #define CMD_ROOT_EN BIT(1)
32 #define CMD_DIRTY_CFG BIT(4)
33 #define CMD_DIRTY_N BIT(5)
34 #define CMD_DIRTY_M BIT(6)
35 #define CMD_DIRTY_D BIT(7)
36 #define CMD_ROOT_OFF BIT(31)
39 #define CFG_SRC_DIV_SHIFT 0
40 #define CFG_SRC_SEL_SHIFT 8
41 #define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT)
42 #define CFG_MODE_SHIFT 12
43 #define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT)
44 #define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT)
50 static int clk_rcg2_is_enabled(struct clk_hw *hw)
52 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
56 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
60 return (cmd & CMD_ROOT_OFF) == 0;
63 static u8 clk_rcg2_get_parent(struct clk_hw *hw)
65 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
66 int num_parents = clk_hw_get_num_parents(hw);
70 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
74 cfg &= CFG_SRC_SEL_MASK;
75 cfg >>= CFG_SRC_SEL_SHIFT;
77 for (i = 0; i < num_parents; i++)
78 if (cfg == rcg->parent_map[i].cfg)
82 pr_debug("%s: Clock %s has invalid parent, using default.\n",
83 __func__, clk_hw_get_name(hw));
87 static int update_config(struct clk_rcg2 *rcg)
91 struct clk_hw *hw = &rcg->clkr.hw;
92 const char *name = clk_hw_get_name(hw);
94 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
95 CMD_UPDATE, CMD_UPDATE);
99 /* Wait for update to take effect */
100 for (count = 500; count > 0; count--) {
101 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
104 if (!(cmd & CMD_UPDATE))
109 WARN(1, "%s: rcg didn't update its configuration.", name);
113 static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
115 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
117 u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
119 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
120 CFG_SRC_SEL_MASK, cfg);
124 return update_config(rcg);
128 * Calculate m/n:d rate
131 * rate = ----------- x ---
135 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
153 clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
155 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
156 u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;
158 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
160 if (rcg->mnd_width) {
161 mask = BIT(rcg->mnd_width) - 1;
162 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m);
164 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n);
168 mode = cfg & CFG_MODE_MASK;
169 mode >>= CFG_MODE_SHIFT;
172 mask = BIT(rcg->hid_width) - 1;
173 hid_div = cfg >> CFG_SRC_DIV_SHIFT;
176 return calc_rate(parent_rate, m, n, mode, hid_div);
179 static int _freq_tbl_determine_rate(struct clk_hw *hw,
180 const struct freq_tbl *f, struct clk_rate_request *req)
182 unsigned long clk_flags, rate = req->rate;
184 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
187 f = qcom_find_freq(f, rate);
191 index = qcom_find_src_index(hw, rcg->parent_map, f->src);
195 clk_flags = clk_hw_get_flags(hw);
196 p = clk_hw_get_parent_by_index(hw, index);
197 if (clk_flags & CLK_SET_RATE_PARENT) {
200 rate *= f->pre_div + 1;
210 rate = clk_hw_get_rate(p);
212 req->best_parent_hw = p;
213 req->best_parent_rate = rate;
219 static int clk_rcg2_determine_rate(struct clk_hw *hw,
220 struct clk_rate_request *req)
222 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
224 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req);
227 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
230 struct clk_hw *hw = &rcg->clkr.hw;
231 int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
236 if (rcg->mnd_width && f->n) {
237 mask = BIT(rcg->mnd_width) - 1;
238 ret = regmap_update_bits(rcg->clkr.regmap,
239 rcg->cmd_rcgr + M_REG, mask, f->m);
243 ret = regmap_update_bits(rcg->clkr.regmap,
244 rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m));
248 ret = regmap_update_bits(rcg->clkr.regmap,
249 rcg->cmd_rcgr + D_REG, mask, ~f->n);
254 mask = BIT(rcg->hid_width) - 1;
255 mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
256 cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
257 cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
258 if (rcg->mnd_width && f->n && (f->m != f->n))
259 cfg |= CFG_MODE_DUAL_EDGE;
260 ret = regmap_update_bits(rcg->clkr.regmap,
261 rcg->cmd_rcgr + CFG_REG, mask, cfg);
265 return update_config(rcg);
268 static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
270 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
271 const struct freq_tbl *f;
273 f = qcom_find_freq(rcg->freq_tbl, rate);
277 return clk_rcg2_configure(rcg, f);
280 static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
281 unsigned long parent_rate)
283 return __clk_rcg2_set_rate(hw, rate);
286 static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
287 unsigned long rate, unsigned long parent_rate, u8 index)
289 return __clk_rcg2_set_rate(hw, rate);
292 const struct clk_ops clk_rcg2_ops = {
293 .is_enabled = clk_rcg2_is_enabled,
294 .get_parent = clk_rcg2_get_parent,
295 .set_parent = clk_rcg2_set_parent,
296 .recalc_rate = clk_rcg2_recalc_rate,
297 .determine_rate = clk_rcg2_determine_rate,
298 .set_rate = clk_rcg2_set_rate,
299 .set_rate_and_parent = clk_rcg2_set_rate_and_parent,
301 EXPORT_SYMBOL_GPL(clk_rcg2_ops);
308 static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */
309 { 52, 295 }, /* 119 M */
310 { 11, 57 }, /* 130.25 M */
311 { 63, 307 }, /* 138.50 M */
312 { 11, 50 }, /* 148.50 M */
313 { 47, 206 }, /* 154 M */
314 { 31, 100 }, /* 205.25 M */
315 { 107, 269 }, /* 268.50 M */
319 static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
320 { 31, 211 }, /* 119 M */
321 { 32, 199 }, /* 130.25 M */
322 { 63, 307 }, /* 138.50 M */
323 { 11, 60 }, /* 148.50 M */
324 { 50, 263 }, /* 154 M */
325 { 31, 120 }, /* 205.25 M */
326 { 119, 359 }, /* 268.50 M */
330 static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
331 unsigned long parent_rate)
333 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
334 struct freq_tbl f = *rcg->freq_tbl;
335 const struct frac_entry *frac;
337 s64 src_rate = parent_rate;
339 u32 mask = BIT(rcg->hid_width) - 1;
342 if (src_rate == 810000000)
343 frac = frac_table_810m;
345 frac = frac_table_675m;
347 for (; frac->num; frac++) {
349 request *= frac->den;
350 request = div_s64(request, frac->num);
351 if ((src_rate < (request - delta)) ||
352 (src_rate > (request + delta)))
355 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
358 f.pre_div >>= CFG_SRC_DIV_SHIFT;
363 return clk_rcg2_configure(rcg, &f);
369 static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
370 unsigned long rate, unsigned long parent_rate, u8 index)
372 /* Parent index is set statically in frequency table */
373 return clk_edp_pixel_set_rate(hw, rate, parent_rate);
376 static int clk_edp_pixel_determine_rate(struct clk_hw *hw,
377 struct clk_rate_request *req)
379 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
380 const struct freq_tbl *f = rcg->freq_tbl;
381 const struct frac_entry *frac;
384 u32 mask = BIT(rcg->hid_width) - 1;
386 int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
388 /* Force the correct parent */
389 req->best_parent_hw = clk_hw_get_parent_by_index(hw, index);
390 req->best_parent_rate = clk_hw_get_rate(req->best_parent_hw);
392 if (req->best_parent_rate == 810000000)
393 frac = frac_table_810m;
395 frac = frac_table_675m;
397 for (; frac->num; frac++) {
399 request *= frac->den;
400 request = div_s64(request, frac->num);
401 if ((req->best_parent_rate < (request - delta)) ||
402 (req->best_parent_rate > (request + delta)))
405 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
407 hid_div >>= CFG_SRC_DIV_SHIFT;
410 req->rate = calc_rate(req->best_parent_rate,
411 frac->num, frac->den,
412 !!frac->den, hid_div);
419 const struct clk_ops clk_edp_pixel_ops = {
420 .is_enabled = clk_rcg2_is_enabled,
421 .get_parent = clk_rcg2_get_parent,
422 .set_parent = clk_rcg2_set_parent,
423 .recalc_rate = clk_rcg2_recalc_rate,
424 .set_rate = clk_edp_pixel_set_rate,
425 .set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
426 .determine_rate = clk_edp_pixel_determine_rate,
428 EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
430 static int clk_byte_determine_rate(struct clk_hw *hw,
431 struct clk_rate_request *req)
433 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
434 const struct freq_tbl *f = rcg->freq_tbl;
435 int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
436 unsigned long parent_rate, div;
437 u32 mask = BIT(rcg->hid_width) - 1;
443 req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index);
444 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, req->rate);
446 div = DIV_ROUND_UP((2 * parent_rate), req->rate) - 1;
447 div = min_t(u32, div, mask);
449 req->rate = calc_rate(parent_rate, 0, 0, 0, div);
454 static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate,
455 unsigned long parent_rate)
457 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
458 struct freq_tbl f = *rcg->freq_tbl;
460 u32 mask = BIT(rcg->hid_width) - 1;
462 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
463 div = min_t(u32, div, mask);
467 return clk_rcg2_configure(rcg, &f);
470 static int clk_byte_set_rate_and_parent(struct clk_hw *hw,
471 unsigned long rate, unsigned long parent_rate, u8 index)
473 /* Parent index is set statically in frequency table */
474 return clk_byte_set_rate(hw, rate, parent_rate);
477 const struct clk_ops clk_byte_ops = {
478 .is_enabled = clk_rcg2_is_enabled,
479 .get_parent = clk_rcg2_get_parent,
480 .set_parent = clk_rcg2_set_parent,
481 .recalc_rate = clk_rcg2_recalc_rate,
482 .set_rate = clk_byte_set_rate,
483 .set_rate_and_parent = clk_byte_set_rate_and_parent,
484 .determine_rate = clk_byte_determine_rate,
486 EXPORT_SYMBOL_GPL(clk_byte_ops);
488 static const struct frac_entry frac_table_pixel[] = {
496 static int clk_pixel_determine_rate(struct clk_hw *hw,
497 struct clk_rate_request *req)
499 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
500 unsigned long request, src_rate;
502 const struct freq_tbl *f = rcg->freq_tbl;
503 const struct frac_entry *frac = frac_table_pixel;
504 int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
506 req->best_parent_hw = clk_hw_get_parent_by_index(hw, index);
508 for (; frac->num; frac++) {
509 request = (req->rate * frac->den) / frac->num;
511 src_rate = clk_hw_round_rate(req->best_parent_hw, request);
512 if ((src_rate < (request - delta)) ||
513 (src_rate > (request + delta)))
516 req->best_parent_rate = src_rate;
517 req->rate = (src_rate * frac->num) / frac->den;
524 static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
525 unsigned long parent_rate)
527 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
528 struct freq_tbl f = *rcg->freq_tbl;
529 const struct frac_entry *frac = frac_table_pixel;
530 unsigned long request;
532 u32 mask = BIT(rcg->hid_width) - 1;
535 for (; frac->num; frac++) {
536 request = (rate * frac->den) / frac->num;
538 if ((parent_rate < (request - delta)) ||
539 (parent_rate > (request + delta)))
542 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
545 f.pre_div >>= CFG_SRC_DIV_SHIFT;
550 return clk_rcg2_configure(rcg, &f);
555 static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
556 unsigned long parent_rate, u8 index)
558 /* Parent index is set statically in frequency table */
559 return clk_pixel_set_rate(hw, rate, parent_rate);
562 const struct clk_ops clk_pixel_ops = {
563 .is_enabled = clk_rcg2_is_enabled,
564 .get_parent = clk_rcg2_get_parent,
565 .set_parent = clk_rcg2_set_parent,
566 .recalc_rate = clk_rcg2_recalc_rate,
567 .set_rate = clk_pixel_set_rate,
568 .set_rate_and_parent = clk_pixel_set_rate_and_parent,
569 .determine_rate = clk_pixel_determine_rate,
571 EXPORT_SYMBOL_GPL(clk_pixel_ops);