2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/bug.h>
18 #include <linux/export.h>
19 #include <linux/clk-provider.h>
20 #include <linux/delay.h>
21 #include <linux/regmap.h>
22 #include <linux/math64.h>
24 #include <asm/div64.h>
30 #define CMD_UPDATE BIT(0)
31 #define CMD_ROOT_EN BIT(1)
32 #define CMD_DIRTY_CFG BIT(4)
33 #define CMD_DIRTY_N BIT(5)
34 #define CMD_DIRTY_M BIT(6)
35 #define CMD_DIRTY_D BIT(7)
36 #define CMD_ROOT_OFF BIT(31)
39 #define CFG_SRC_DIV_SHIFT 0
40 #define CFG_SRC_SEL_SHIFT 8
41 #define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT)
42 #define CFG_MODE_SHIFT 12
43 #define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT)
44 #define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT)
50 static int clk_rcg2_is_enabled(struct clk_hw *hw)
52 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
56 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
60 return (cmd & CMD_ROOT_OFF) == 0;
63 static u8 clk_rcg2_get_parent(struct clk_hw *hw)
65 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
66 int num_parents = __clk_get_num_parents(hw->clk);
70 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
74 cfg &= CFG_SRC_SEL_MASK;
75 cfg >>= CFG_SRC_SEL_SHIFT;
77 for (i = 0; i < num_parents; i++)
78 if (cfg == rcg->parent_map[i])
84 static int update_config(struct clk_rcg2 *rcg)
88 struct clk_hw *hw = &rcg->clkr.hw;
89 const char *name = __clk_get_name(hw->clk);
91 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
92 CMD_UPDATE, CMD_UPDATE);
96 /* Wait for update to take effect */
97 for (count = 500; count > 0; count--) {
98 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
101 if (!(cmd & CMD_UPDATE))
106 WARN(1, "%s: rcg didn't update its configuration.", name);
110 static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
112 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
115 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
117 rcg->parent_map[index] << CFG_SRC_SEL_SHIFT);
121 return update_config(rcg);
125 * Calculate m/n:d rate
128 * rate = ----------- x ---
132 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
150 clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
152 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
153 u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;
155 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
157 if (rcg->mnd_width) {
158 mask = BIT(rcg->mnd_width) - 1;
159 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m);
161 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n);
165 mode = cfg & CFG_MODE_MASK;
166 mode >>= CFG_MODE_SHIFT;
169 mask = BIT(rcg->hid_width) - 1;
170 hid_div = cfg >> CFG_SRC_DIV_SHIFT;
173 return calc_rate(parent_rate, m, n, mode, hid_div);
176 static long _freq_tbl_determine_rate(struct clk_hw *hw,
177 const struct freq_tbl *f, unsigned long rate,
178 unsigned long *p_rate, struct clk_hw **p_hw)
180 unsigned long clk_flags;
183 f = qcom_find_freq(f, rate);
187 clk_flags = __clk_get_flags(hw->clk);
188 p = clk_get_parent_by_index(hw->clk, f->src);
189 if (clk_flags & CLK_SET_RATE_PARENT) {
192 rate *= f->pre_div + 1;
202 rate = __clk_get_rate(p);
204 *p_hw = __clk_get_hw(p);
210 static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
211 unsigned long min_rate, unsigned long max_rate,
212 unsigned long *p_rate, struct clk_hw **p)
214 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
216 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
219 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
224 if (rcg->mnd_width && f->n) {
225 mask = BIT(rcg->mnd_width) - 1;
226 ret = regmap_update_bits(rcg->clkr.regmap,
227 rcg->cmd_rcgr + M_REG, mask, f->m);
231 ret = regmap_update_bits(rcg->clkr.regmap,
232 rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m));
236 ret = regmap_update_bits(rcg->clkr.regmap,
237 rcg->cmd_rcgr + D_REG, mask, ~f->n);
242 mask = BIT(rcg->hid_width) - 1;
243 mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
244 cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
245 cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
246 if (rcg->mnd_width && f->n)
247 cfg |= CFG_MODE_DUAL_EDGE;
248 ret = regmap_update_bits(rcg->clkr.regmap,
249 rcg->cmd_rcgr + CFG_REG, mask, cfg);
253 return update_config(rcg);
256 static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
258 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
259 const struct freq_tbl *f;
261 f = qcom_find_freq(rcg->freq_tbl, rate);
265 return clk_rcg2_configure(rcg, f);
268 static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
269 unsigned long parent_rate)
271 return __clk_rcg2_set_rate(hw, rate);
274 static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
275 unsigned long rate, unsigned long parent_rate, u8 index)
277 return __clk_rcg2_set_rate(hw, rate);
280 const struct clk_ops clk_rcg2_ops = {
281 .is_enabled = clk_rcg2_is_enabled,
282 .get_parent = clk_rcg2_get_parent,
283 .set_parent = clk_rcg2_set_parent,
284 .recalc_rate = clk_rcg2_recalc_rate,
285 .determine_rate = clk_rcg2_determine_rate,
286 .set_rate = clk_rcg2_set_rate,
287 .set_rate_and_parent = clk_rcg2_set_rate_and_parent,
289 EXPORT_SYMBOL_GPL(clk_rcg2_ops);
296 static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */
297 { 52, 295 }, /* 119 M */
298 { 11, 57 }, /* 130.25 M */
299 { 63, 307 }, /* 138.50 M */
300 { 11, 50 }, /* 148.50 M */
301 { 47, 206 }, /* 154 M */
302 { 31, 100 }, /* 205.25 M */
303 { 107, 269 }, /* 268.50 M */
307 static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
308 { 31, 211 }, /* 119 M */
309 { 32, 199 }, /* 130.25 M */
310 { 63, 307 }, /* 138.50 M */
311 { 11, 60 }, /* 148.50 M */
312 { 50, 263 }, /* 154 M */
313 { 31, 120 }, /* 205.25 M */
314 { 119, 359 }, /* 268.50 M */
318 static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
319 unsigned long parent_rate)
321 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
322 struct freq_tbl f = *rcg->freq_tbl;
323 const struct frac_entry *frac;
325 s64 src_rate = parent_rate;
327 u32 mask = BIT(rcg->hid_width) - 1;
330 if (src_rate == 810000000)
331 frac = frac_table_810m;
333 frac = frac_table_675m;
335 for (; frac->num; frac++) {
337 request *= frac->den;
338 request = div_s64(request, frac->num);
339 if ((src_rate < (request - delta)) ||
340 (src_rate > (request + delta)))
343 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
346 f.pre_div >>= CFG_SRC_DIV_SHIFT;
351 return clk_rcg2_configure(rcg, &f);
357 static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
358 unsigned long rate, unsigned long parent_rate, u8 index)
360 /* Parent index is set statically in frequency table */
361 return clk_edp_pixel_set_rate(hw, rate, parent_rate);
364 static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
365 unsigned long min_rate,
366 unsigned long max_rate,
367 unsigned long *p_rate, struct clk_hw **p)
369 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
370 const struct freq_tbl *f = rcg->freq_tbl;
371 const struct frac_entry *frac;
373 s64 src_rate = *p_rate;
375 u32 mask = BIT(rcg->hid_width) - 1;
378 /* Force the correct parent */
379 *p = __clk_get_hw(clk_get_parent_by_index(hw->clk, f->src));
381 if (src_rate == 810000000)
382 frac = frac_table_810m;
384 frac = frac_table_675m;
386 for (; frac->num; frac++) {
388 request *= frac->den;
389 request = div_s64(request, frac->num);
390 if ((src_rate < (request - delta)) ||
391 (src_rate > (request + delta)))
394 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
396 hid_div >>= CFG_SRC_DIV_SHIFT;
399 return calc_rate(src_rate, frac->num, frac->den, !!frac->den,
406 const struct clk_ops clk_edp_pixel_ops = {
407 .is_enabled = clk_rcg2_is_enabled,
408 .get_parent = clk_rcg2_get_parent,
409 .set_parent = clk_rcg2_set_parent,
410 .recalc_rate = clk_rcg2_recalc_rate,
411 .set_rate = clk_edp_pixel_set_rate,
412 .set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
413 .determine_rate = clk_edp_pixel_determine_rate,
415 EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
417 static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate,
418 unsigned long min_rate, unsigned long max_rate,
419 unsigned long *p_rate, struct clk_hw **p_hw)
421 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
422 const struct freq_tbl *f = rcg->freq_tbl;
423 unsigned long parent_rate, div;
424 u32 mask = BIT(rcg->hid_width) - 1;
430 p = clk_get_parent_by_index(hw->clk, f->src);
431 *p_hw = __clk_get_hw(p);
432 *p_rate = parent_rate = __clk_round_rate(p, rate);
434 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
435 div = min_t(u32, div, mask);
437 return calc_rate(parent_rate, 0, 0, 0, div);
440 static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate,
441 unsigned long parent_rate)
443 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
444 struct freq_tbl f = *rcg->freq_tbl;
446 u32 mask = BIT(rcg->hid_width) - 1;
448 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
449 div = min_t(u32, div, mask);
453 return clk_rcg2_configure(rcg, &f);
456 static int clk_byte_set_rate_and_parent(struct clk_hw *hw,
457 unsigned long rate, unsigned long parent_rate, u8 index)
459 /* Parent index is set statically in frequency table */
460 return clk_byte_set_rate(hw, rate, parent_rate);
463 const struct clk_ops clk_byte_ops = {
464 .is_enabled = clk_rcg2_is_enabled,
465 .get_parent = clk_rcg2_get_parent,
466 .set_parent = clk_rcg2_set_parent,
467 .recalc_rate = clk_rcg2_recalc_rate,
468 .set_rate = clk_byte_set_rate,
469 .set_rate_and_parent = clk_byte_set_rate_and_parent,
470 .determine_rate = clk_byte_determine_rate,
472 EXPORT_SYMBOL_GPL(clk_byte_ops);
474 static const struct frac_entry frac_table_pixel[] = {
482 static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
483 unsigned long min_rate,
484 unsigned long max_rate,
485 unsigned long *p_rate, struct clk_hw **p)
487 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
488 unsigned long request, src_rate;
490 const struct freq_tbl *f = rcg->freq_tbl;
491 const struct frac_entry *frac = frac_table_pixel;
492 struct clk *parent = clk_get_parent_by_index(hw->clk, f->src);
494 *p = __clk_get_hw(parent);
496 for (; frac->num; frac++) {
497 request = (rate * frac->den) / frac->num;
499 src_rate = __clk_round_rate(parent, request);
500 if ((src_rate < (request - delta)) ||
501 (src_rate > (request + delta)))
505 return (src_rate * frac->num) / frac->den;
511 static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
512 unsigned long parent_rate)
514 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
515 struct freq_tbl f = *rcg->freq_tbl;
516 const struct frac_entry *frac = frac_table_pixel;
517 unsigned long request, src_rate;
519 u32 mask = BIT(rcg->hid_width) - 1;
521 struct clk *parent = clk_get_parent_by_index(hw->clk, f.src);
523 for (; frac->num; frac++) {
524 request = (rate * frac->den) / frac->num;
526 src_rate = __clk_round_rate(parent, request);
527 if ((src_rate < (request - delta)) ||
528 (src_rate > (request + delta)))
531 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
534 f.pre_div >>= CFG_SRC_DIV_SHIFT;
539 return clk_rcg2_configure(rcg, &f);
544 static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
545 unsigned long parent_rate, u8 index)
547 /* Parent index is set statically in frequency table */
548 return clk_pixel_set_rate(hw, rate, parent_rate);
551 const struct clk_ops clk_pixel_ops = {
552 .is_enabled = clk_rcg2_is_enabled,
553 .get_parent = clk_rcg2_get_parent,
554 .set_parent = clk_rcg2_set_parent,
555 .recalc_rate = clk_rcg2_recalc_rate,
556 .set_rate = clk_pixel_set_rate,
557 .set_rate_and_parent = clk_pixel_set_rate_and_parent,
558 .determine_rate = clk_pixel_determine_rate,
560 EXPORT_SYMBOL_GPL(clk_pixel_ops);