2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/bug.h>
18 #include <linux/export.h>
19 #include <linux/clk-provider.h>
20 #include <linux/delay.h>
21 #include <linux/regmap.h>
22 #include <linux/math64.h>
24 #include <asm/div64.h>
30 #define CMD_UPDATE BIT(0)
31 #define CMD_ROOT_EN BIT(1)
32 #define CMD_DIRTY_CFG BIT(4)
33 #define CMD_DIRTY_N BIT(5)
34 #define CMD_DIRTY_M BIT(6)
35 #define CMD_DIRTY_D BIT(7)
36 #define CMD_ROOT_OFF BIT(31)
39 #define CFG_SRC_DIV_SHIFT 0
40 #define CFG_SRC_SEL_SHIFT 8
41 #define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT)
42 #define CFG_MODE_SHIFT 12
43 #define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT)
44 #define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT)
55 static int clk_rcg2_is_enabled(struct clk_hw *hw)
57 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
61 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
65 return (cmd & CMD_ROOT_OFF) == 0;
68 static u8 clk_rcg2_get_parent(struct clk_hw *hw)
70 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
71 int num_parents = clk_hw_get_num_parents(hw);
75 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
79 cfg &= CFG_SRC_SEL_MASK;
80 cfg >>= CFG_SRC_SEL_SHIFT;
82 for (i = 0; i < num_parents; i++)
83 if (cfg == rcg->parent_map[i].cfg)
87 pr_debug("%s: Clock %s has invalid parent, using default.\n",
88 __func__, clk_hw_get_name(hw));
92 static int update_config(struct clk_rcg2 *rcg)
96 struct clk_hw *hw = &rcg->clkr.hw;
97 const char *name = clk_hw_get_name(hw);
99 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
100 CMD_UPDATE, CMD_UPDATE);
104 /* Wait for update to take effect */
105 for (count = 500; count > 0; count--) {
106 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
109 if (!(cmd & CMD_UPDATE))
114 WARN(1, "%s: rcg didn't update its configuration.", name);
118 static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
120 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
122 u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
124 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
125 CFG_SRC_SEL_MASK, cfg);
129 return update_config(rcg);
133 * Calculate m/n:d rate
136 * rate = ----------- x ---
140 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
158 clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
160 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
161 u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;
163 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
165 if (rcg->mnd_width) {
166 mask = BIT(rcg->mnd_width) - 1;
167 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m);
169 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n);
173 mode = cfg & CFG_MODE_MASK;
174 mode >>= CFG_MODE_SHIFT;
177 mask = BIT(rcg->hid_width) - 1;
178 hid_div = cfg >> CFG_SRC_DIV_SHIFT;
181 return calc_rate(parent_rate, m, n, mode, hid_div);
184 static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
185 struct clk_rate_request *req,
186 enum freq_policy policy)
188 unsigned long clk_flags, rate = req->rate;
190 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
195 f = qcom_find_freq_floor(f, rate);
198 f = qcom_find_freq(f, rate);
207 index = qcom_find_src_index(hw, rcg->parent_map, f->src);
211 clk_flags = clk_hw_get_flags(hw);
212 p = clk_hw_get_parent_by_index(hw, index);
213 if (clk_flags & CLK_SET_RATE_PARENT) {
216 rate *= f->pre_div + 1;
226 rate = clk_hw_get_rate(p);
228 req->best_parent_hw = p;
229 req->best_parent_rate = rate;
235 static int clk_rcg2_determine_rate(struct clk_hw *hw,
236 struct clk_rate_request *req)
238 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
240 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, CEIL);
243 static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
244 struct clk_rate_request *req)
246 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
248 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);
251 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
254 struct clk_hw *hw = &rcg->clkr.hw;
255 int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
260 if (rcg->mnd_width && f->n) {
261 mask = BIT(rcg->mnd_width) - 1;
262 ret = regmap_update_bits(rcg->clkr.regmap,
263 rcg->cmd_rcgr + M_REG, mask, f->m);
267 ret = regmap_update_bits(rcg->clkr.regmap,
268 rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m));
272 ret = regmap_update_bits(rcg->clkr.regmap,
273 rcg->cmd_rcgr + D_REG, mask, ~f->n);
278 mask = BIT(rcg->hid_width) - 1;
279 mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
280 cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
281 cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
282 if (rcg->mnd_width && f->n && (f->m != f->n))
283 cfg |= CFG_MODE_DUAL_EDGE;
284 ret = regmap_update_bits(rcg->clkr.regmap,
285 rcg->cmd_rcgr + CFG_REG, mask, cfg);
289 return update_config(rcg);
292 static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
293 enum freq_policy policy)
295 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
296 const struct freq_tbl *f;
300 f = qcom_find_freq_floor(rcg->freq_tbl, rate);
303 f = qcom_find_freq(rcg->freq_tbl, rate);
312 return clk_rcg2_configure(rcg, f);
315 static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
316 unsigned long parent_rate)
318 return __clk_rcg2_set_rate(hw, rate, CEIL);
321 static int clk_rcg2_set_floor_rate(struct clk_hw *hw, unsigned long rate,
322 unsigned long parent_rate)
324 return __clk_rcg2_set_rate(hw, rate, FLOOR);
327 static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
328 unsigned long rate, unsigned long parent_rate, u8 index)
330 return __clk_rcg2_set_rate(hw, rate, CEIL);
333 static int clk_rcg2_set_floor_rate_and_parent(struct clk_hw *hw,
334 unsigned long rate, unsigned long parent_rate, u8 index)
336 return __clk_rcg2_set_rate(hw, rate, FLOOR);
339 const struct clk_ops clk_rcg2_ops = {
340 .is_enabled = clk_rcg2_is_enabled,
341 .get_parent = clk_rcg2_get_parent,
342 .set_parent = clk_rcg2_set_parent,
343 .recalc_rate = clk_rcg2_recalc_rate,
344 .determine_rate = clk_rcg2_determine_rate,
345 .set_rate = clk_rcg2_set_rate,
346 .set_rate_and_parent = clk_rcg2_set_rate_and_parent,
348 EXPORT_SYMBOL_GPL(clk_rcg2_ops);
350 const struct clk_ops clk_rcg2_floor_ops = {
351 .is_enabled = clk_rcg2_is_enabled,
352 .get_parent = clk_rcg2_get_parent,
353 .set_parent = clk_rcg2_set_parent,
354 .recalc_rate = clk_rcg2_recalc_rate,
355 .determine_rate = clk_rcg2_determine_floor_rate,
356 .set_rate = clk_rcg2_set_floor_rate,
357 .set_rate_and_parent = clk_rcg2_set_floor_rate_and_parent,
359 EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
361 static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate)
363 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
364 const char *name = clk_hw_get_name(hw);
367 /* force enable RCG */
368 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
369 CMD_ROOT_EN, CMD_ROOT_EN);
373 /* wait for RCG to turn ON */
374 for (count = 500; count > 0; count--) {
375 ret = clk_rcg2_is_enabled(hw);
381 pr_err("%s: RCG did not turn on\n", name);
384 ret = __clk_rcg2_set_rate(hw, rate, CEIL);
388 /* clear force enable RCG */
389 return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
393 static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,
394 unsigned long parent_rate)
396 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
399 rcg->current_freq = rate;
401 if (!__clk_is_enabled(hw->clk))
404 return clk_rcg2_shared_force_enable(hw, rcg->current_freq);
408 clk_rcg2_shared_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
410 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
412 return rcg->current_freq = clk_rcg2_recalc_rate(hw, parent_rate);
415 static int clk_rcg2_shared_enable(struct clk_hw *hw)
417 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
419 return clk_rcg2_shared_force_enable(hw, rcg->current_freq);
422 static void clk_rcg2_shared_disable(struct clk_hw *hw)
424 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
426 /* switch to XO, which is the lowest entry in the freq table */
427 clk_rcg2_shared_set_rate(hw, rcg->freq_tbl[0].freq, 0);
430 const struct clk_ops clk_rcg2_shared_ops = {
431 .enable = clk_rcg2_shared_enable,
432 .disable = clk_rcg2_shared_disable,
433 .get_parent = clk_rcg2_get_parent,
434 .recalc_rate = clk_rcg2_shared_recalc_rate,
435 .determine_rate = clk_rcg2_determine_rate,
436 .set_rate = clk_rcg2_shared_set_rate,
438 EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
445 static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */
446 { 52, 295 }, /* 119 M */
447 { 11, 57 }, /* 130.25 M */
448 { 63, 307 }, /* 138.50 M */
449 { 11, 50 }, /* 148.50 M */
450 { 47, 206 }, /* 154 M */
451 { 31, 100 }, /* 205.25 M */
452 { 107, 269 }, /* 268.50 M */
456 static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
457 { 31, 211 }, /* 119 M */
458 { 32, 199 }, /* 130.25 M */
459 { 63, 307 }, /* 138.50 M */
460 { 11, 60 }, /* 148.50 M */
461 { 50, 263 }, /* 154 M */
462 { 31, 120 }, /* 205.25 M */
463 { 119, 359 }, /* 268.50 M */
467 static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
468 unsigned long parent_rate)
470 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
471 struct freq_tbl f = *rcg->freq_tbl;
472 const struct frac_entry *frac;
474 s64 src_rate = parent_rate;
476 u32 mask = BIT(rcg->hid_width) - 1;
479 if (src_rate == 810000000)
480 frac = frac_table_810m;
482 frac = frac_table_675m;
484 for (; frac->num; frac++) {
486 request *= frac->den;
487 request = div_s64(request, frac->num);
488 if ((src_rate < (request - delta)) ||
489 (src_rate > (request + delta)))
492 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
495 f.pre_div >>= CFG_SRC_DIV_SHIFT;
500 return clk_rcg2_configure(rcg, &f);
506 static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
507 unsigned long rate, unsigned long parent_rate, u8 index)
509 /* Parent index is set statically in frequency table */
510 return clk_edp_pixel_set_rate(hw, rate, parent_rate);
513 static int clk_edp_pixel_determine_rate(struct clk_hw *hw,
514 struct clk_rate_request *req)
516 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
517 const struct freq_tbl *f = rcg->freq_tbl;
518 const struct frac_entry *frac;
521 u32 mask = BIT(rcg->hid_width) - 1;
523 int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
525 /* Force the correct parent */
526 req->best_parent_hw = clk_hw_get_parent_by_index(hw, index);
527 req->best_parent_rate = clk_hw_get_rate(req->best_parent_hw);
529 if (req->best_parent_rate == 810000000)
530 frac = frac_table_810m;
532 frac = frac_table_675m;
534 for (; frac->num; frac++) {
536 request *= frac->den;
537 request = div_s64(request, frac->num);
538 if ((req->best_parent_rate < (request - delta)) ||
539 (req->best_parent_rate > (request + delta)))
542 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
544 hid_div >>= CFG_SRC_DIV_SHIFT;
547 req->rate = calc_rate(req->best_parent_rate,
548 frac->num, frac->den,
549 !!frac->den, hid_div);
556 const struct clk_ops clk_edp_pixel_ops = {
557 .is_enabled = clk_rcg2_is_enabled,
558 .get_parent = clk_rcg2_get_parent,
559 .set_parent = clk_rcg2_set_parent,
560 .recalc_rate = clk_rcg2_recalc_rate,
561 .set_rate = clk_edp_pixel_set_rate,
562 .set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
563 .determine_rate = clk_edp_pixel_determine_rate,
565 EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
567 static int clk_byte_determine_rate(struct clk_hw *hw,
568 struct clk_rate_request *req)
570 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
571 const struct freq_tbl *f = rcg->freq_tbl;
572 int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
573 unsigned long parent_rate, div;
574 u32 mask = BIT(rcg->hid_width) - 1;
580 req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index);
581 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, req->rate);
583 div = DIV_ROUND_UP((2 * parent_rate), req->rate) - 1;
584 div = min_t(u32, div, mask);
586 req->rate = calc_rate(parent_rate, 0, 0, 0, div);
591 static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate,
592 unsigned long parent_rate)
594 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
595 struct freq_tbl f = *rcg->freq_tbl;
597 u32 mask = BIT(rcg->hid_width) - 1;
599 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
600 div = min_t(u32, div, mask);
604 return clk_rcg2_configure(rcg, &f);
607 static int clk_byte_set_rate_and_parent(struct clk_hw *hw,
608 unsigned long rate, unsigned long parent_rate, u8 index)
610 /* Parent index is set statically in frequency table */
611 return clk_byte_set_rate(hw, rate, parent_rate);
614 const struct clk_ops clk_byte_ops = {
615 .is_enabled = clk_rcg2_is_enabled,
616 .get_parent = clk_rcg2_get_parent,
617 .set_parent = clk_rcg2_set_parent,
618 .recalc_rate = clk_rcg2_recalc_rate,
619 .set_rate = clk_byte_set_rate,
620 .set_rate_and_parent = clk_byte_set_rate_and_parent,
621 .determine_rate = clk_byte_determine_rate,
623 EXPORT_SYMBOL_GPL(clk_byte_ops);
625 static int clk_byte2_determine_rate(struct clk_hw *hw,
626 struct clk_rate_request *req)
628 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
629 unsigned long parent_rate, div;
630 u32 mask = BIT(rcg->hid_width) - 1;
632 unsigned long rate = req->rate;
637 p = req->best_parent_hw;
638 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, rate);
640 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
641 div = min_t(u32, div, mask);
643 req->rate = calc_rate(parent_rate, 0, 0, 0, div);
648 static int clk_byte2_set_rate(struct clk_hw *hw, unsigned long rate,
649 unsigned long parent_rate)
651 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
652 struct freq_tbl f = { 0 };
654 int i, num_parents = clk_hw_get_num_parents(hw);
655 u32 mask = BIT(rcg->hid_width) - 1;
658 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
659 div = min_t(u32, div, mask);
663 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
664 cfg &= CFG_SRC_SEL_MASK;
665 cfg >>= CFG_SRC_SEL_SHIFT;
667 for (i = 0; i < num_parents; i++) {
668 if (cfg == rcg->parent_map[i].cfg) {
669 f.src = rcg->parent_map[i].src;
670 return clk_rcg2_configure(rcg, &f);
677 static int clk_byte2_set_rate_and_parent(struct clk_hw *hw,
678 unsigned long rate, unsigned long parent_rate, u8 index)
680 /* Read the hardware to determine parent during set_rate */
681 return clk_byte2_set_rate(hw, rate, parent_rate);
684 const struct clk_ops clk_byte2_ops = {
685 .is_enabled = clk_rcg2_is_enabled,
686 .get_parent = clk_rcg2_get_parent,
687 .set_parent = clk_rcg2_set_parent,
688 .recalc_rate = clk_rcg2_recalc_rate,
689 .set_rate = clk_byte2_set_rate,
690 .set_rate_and_parent = clk_byte2_set_rate_and_parent,
691 .determine_rate = clk_byte2_determine_rate,
693 EXPORT_SYMBOL_GPL(clk_byte2_ops);
695 static const struct frac_entry frac_table_pixel[] = {
703 static int clk_pixel_determine_rate(struct clk_hw *hw,
704 struct clk_rate_request *req)
706 unsigned long request, src_rate;
708 const struct frac_entry *frac = frac_table_pixel;
710 for (; frac->num; frac++) {
711 request = (req->rate * frac->den) / frac->num;
713 src_rate = clk_hw_round_rate(req->best_parent_hw, request);
714 if ((src_rate < (request - delta)) ||
715 (src_rate > (request + delta)))
718 req->best_parent_rate = src_rate;
719 req->rate = (src_rate * frac->num) / frac->den;
726 static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
727 unsigned long parent_rate)
729 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
730 struct freq_tbl f = { 0 };
731 const struct frac_entry *frac = frac_table_pixel;
732 unsigned long request;
734 u32 mask = BIT(rcg->hid_width) - 1;
736 int i, num_parents = clk_hw_get_num_parents(hw);
738 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
739 cfg &= CFG_SRC_SEL_MASK;
740 cfg >>= CFG_SRC_SEL_SHIFT;
742 for (i = 0; i < num_parents; i++)
743 if (cfg == rcg->parent_map[i].cfg) {
744 f.src = rcg->parent_map[i].src;
748 for (; frac->num; frac++) {
749 request = (rate * frac->den) / frac->num;
751 if ((parent_rate < (request - delta)) ||
752 (parent_rate > (request + delta)))
755 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
758 f.pre_div >>= CFG_SRC_DIV_SHIFT;
763 return clk_rcg2_configure(rcg, &f);
768 static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
769 unsigned long parent_rate, u8 index)
771 return clk_pixel_set_rate(hw, rate, parent_rate);
774 const struct clk_ops clk_pixel_ops = {
775 .is_enabled = clk_rcg2_is_enabled,
776 .get_parent = clk_rcg2_get_parent,
777 .set_parent = clk_rcg2_set_parent,
778 .recalc_rate = clk_rcg2_recalc_rate,
779 .set_rate = clk_pixel_set_rate,
780 .set_rate_and_parent = clk_pixel_set_rate_and_parent,
781 .determine_rate = clk_pixel_determine_rate,
783 EXPORT_SYMBOL_GPL(clk_pixel_ops);
785 static int clk_gfx3d_determine_rate(struct clk_hw *hw,
786 struct clk_rate_request *req)
788 struct clk_rate_request parent_req = { };
789 struct clk_hw *p2, *p8, *p9, *xo;
790 unsigned long p9_rate;
793 xo = clk_hw_get_parent_by_index(hw, 0);
794 if (req->rate == clk_hw_get_rate(xo)) {
795 req->best_parent_hw = xo;
799 p9 = clk_hw_get_parent_by_index(hw, 2);
800 p2 = clk_hw_get_parent_by_index(hw, 3);
801 p8 = clk_hw_get_parent_by_index(hw, 4);
803 /* PLL9 is a fixed rate PLL */
804 p9_rate = clk_hw_get_rate(p9);
806 parent_req.rate = req->rate = min(req->rate, p9_rate);
807 if (req->rate == p9_rate) {
808 req->rate = req->best_parent_rate = p9_rate;
809 req->best_parent_hw = p9;
813 if (req->best_parent_hw == p9) {
814 /* Are we going back to a previously used rate? */
815 if (clk_hw_get_rate(p8) == req->rate)
816 req->best_parent_hw = p8;
818 req->best_parent_hw = p2;
819 } else if (req->best_parent_hw == p8) {
820 req->best_parent_hw = p2;
822 req->best_parent_hw = p8;
825 ret = __clk_determine_rate(req->best_parent_hw, &parent_req);
829 req->rate = req->best_parent_rate = parent_req.rate;
834 static int clk_gfx3d_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
835 unsigned long parent_rate, u8 index)
837 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
841 /* Just mux it, we don't use the division or m/n hardware */
842 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
843 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
847 return update_config(rcg);
850 static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate,
851 unsigned long parent_rate)
854 * We should never get here; clk_gfx3d_determine_rate() should always
855 * make us use a different parent than what we're currently using, so
856 * clk_gfx3d_set_rate_and_parent() should always be called.
861 const struct clk_ops clk_gfx3d_ops = {
862 .is_enabled = clk_rcg2_is_enabled,
863 .get_parent = clk_rcg2_get_parent,
864 .set_parent = clk_rcg2_set_parent,
865 .recalc_rate = clk_rcg2_recalc_rate,
866 .set_rate = clk_gfx3d_set_rate,
867 .set_rate_and_parent = clk_gfx3d_set_rate_and_parent,
868 .determine_rate = clk_gfx3d_determine_rate,
870 EXPORT_SYMBOL_GPL(clk_gfx3d_ops);