drivers/clk/qcom/clk-smd-rpm.c

   1 /*
   2  * Copyright (c) 2015, Linaro Limited
   3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk-provider.h>
  16 #include <linux/err.h>
  17 #include <linux/export.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/mutex.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/soc/qcom/smd-rpm.h>
  26
  27 #include "clk-smd-rpm.h"
  28 #include <dt-bindings/clock/qcom,rpmcc.h>
  29
  30 #define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
  31
  32 static DEFINE_MUTEX(rpm_smd_clk_lock);
  33
  34 static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
  35                                        unsigned long rate)
  36 {
  37         struct clk_smd_rpm_req req = {
  38                 .key = cpu_to_le32(r->rpm_key),
  39                 .nbytes = cpu_to_le32(sizeof(u32)),
  40                 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
  41         };
  42
  43         return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
  44                                   r->rpm_res_type, r->rpm_clk_id, &req,
  45                                   sizeof(req));
  46 }
  47
  48 static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
  49                                       unsigned long rate)
  50 {
  51         struct clk_smd_rpm_req req = {
  52                 .key = cpu_to_le32(r->rpm_key),
  53                 .nbytes = cpu_to_le32(sizeof(u32)),
  54                 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
  55         };
  56
  57         return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
  58                                   r->rpm_res_type, r->rpm_clk_id, &req,
  59                                   sizeof(req));
  60 }
  61
  62 static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate,
  63                             unsigned long *active, unsigned long *sleep)
  64 {
  65         *active = rate;
  66
  67         /*
  68          * Active-only clocks don't care what the rate is during sleep. So,
  69          * they vote for zero.
  70          */
  71         if (r->active_only)
  72                 *sleep = 0;
  73         else
  74                 *sleep = *active;
  75 }
  76
  77 static int clk_smd_rpm_prepare(struct clk_hw *hw)
  78 {
  79         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
  80         struct clk_smd_rpm *peer = r->peer;
  81         unsigned long this_rate = 0, this_sleep_rate = 0;
  82         unsigned long peer_rate = 0, peer_sleep_rate = 0;
  83         unsigned long active_rate, sleep_rate;
  84         int ret = 0;
  85
  86         mutex_lock(&rpm_smd_clk_lock);
  87
  88         /* Don't send requests to the RPM if the rate has not been set. */
  89         if (!r->rate)
  90                 goto out;
  91
  92         to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
  93
  94         /* Take peer clock's rate into account only if it's enabled. */
  95         if (peer->enabled)
  96                 to_active_sleep(peer, peer->rate,
  97                                 &peer_rate, &peer_sleep_rate);
  98
  99         active_rate = max(this_rate, peer_rate);
 100
 101         if (r->branch)
 102                 active_rate = !!active_rate;
 103
 104         ret = clk_smd_rpm_set_rate_active(r, active_rate);
 105         if (ret)
 106                 goto out;
 107
 108         sleep_rate = max(this_sleep_rate, peer_sleep_rate);
 109         if (r->branch)
 110                 sleep_rate = !!sleep_rate;
 111
 112         ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
 113         if (ret)
 114                 /* Undo the active set vote and restore it */
 115                 ret = clk_smd_rpm_set_rate_active(r, peer_rate);
 116
 117 out:
 118         if (!ret)
 119                 r->enabled = true;
 120
 121         mutex_unlock(&rpm_smd_clk_lock);
 122
 123         return ret;
 124 }
 125
 126 static void clk_smd_rpm_unprepare(struct clk_hw *hw)
 127 {
 128         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 129         struct clk_smd_rpm *peer = r->peer;
 130         unsigned long peer_rate = 0, peer_sleep_rate = 0;
 131         unsigned long active_rate, sleep_rate;
 132         int ret;
 133
 134         mutex_lock(&rpm_smd_clk_lock);
 135
 136         if (!r->rate)
 137                 goto out;
 138
 139         /* Take peer clock's rate into account only if it's enabled. */
 140         if (peer->enabled)
 141                 to_active_sleep(peer, peer->rate, &peer_rate,
 142                                 &peer_sleep_rate);
 143
 144         active_rate = r->branch ? !!peer_rate : peer_rate;
 145         ret = clk_smd_rpm_set_rate_active(r, active_rate);
 146         if (ret)
 147                 goto out;
 148
 149         sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
 150         ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
 151         if (ret)
 152                 goto out;
 153
 154         r->enabled = false;
 155
 156 out:
 157         mutex_unlock(&rpm_smd_clk_lock);
 158 }
 159
 160 static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,
 161                                 unsigned long parent_rate)
 162 {
 163         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 164         struct clk_smd_rpm *peer = r->peer;
 165         unsigned long active_rate, sleep_rate;
 166         unsigned long this_rate = 0, this_sleep_rate = 0;
 167         unsigned long peer_rate = 0, peer_sleep_rate = 0;
 168         int ret = 0;
 169
 170         mutex_lock(&rpm_smd_clk_lock);
 171
 172         if (!r->enabled)
 173                 goto out;
 174
 175         to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
 176
 177         /* Take peer clock's rate into account only if it's enabled. */
 178         if (peer->enabled)
 179                 to_active_sleep(peer, peer->rate,
 180                                 &peer_rate, &peer_sleep_rate);
 181
 182         active_rate = max(this_rate, peer_rate);
 183         ret = clk_smd_rpm_set_rate_active(r, active_rate);
 184         if (ret)
 185                 goto out;
 186
 187         sleep_rate = max(this_sleep_rate, peer_sleep_rate);
 188         ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
 189         if (ret)
 190                 goto out;
 191
 192         r->rate = rate;
 193
 194 out:
 195         mutex_unlock(&rpm_smd_clk_lock);
 196
 197         return ret;
 198 }
 199
 200 static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
 201                                    unsigned long *parent_rate)
 202 {
 203         /*
 204          * RPM handles rate rounding and we don't have a way to
 205          * know what the rate will be, so just return whatever
 206          * rate is requested.
 207          */
 208         return rate;
 209 }
 210
 211 static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,
 212                                              unsigned long parent_rate)
 213 {
 214         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 215
 216         /*
 217          * RPM handles rate rounding and we don't have a way to
 218          * know what the rate will be, so just return whatever
 219          * rate was set.
 220          */
 221         return r->rate;
 222 }
 223
 224 static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
 225 {
 226         int ret;
 227         struct clk_smd_rpm_req req = {
 228                 .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE),
 229                 .nbytes = cpu_to_le32(sizeof(u32)),
 230                 .value = cpu_to_le32(1),
 231         };
 232
 233         ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE,
 234                                  QCOM_SMD_RPM_MISC_CLK,
 235                                  QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
 236         if (ret) {
 237                 pr_err("RPM clock scaling (sleep set) not enabled!\n");
 238                 return ret;
 239         }
 240
 241         ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE,
 242                                  QCOM_SMD_RPM_MISC_CLK,
 243                                  QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
 244         if (ret) {
 245                 pr_err("RPM clock scaling (active set) not enabled!\n");
 246                 return ret;
 247         }
 248
 249         pr_debug("%s: RPM clock scaling is enabled\n", __func__);
 250         return 0;
 251 }
 252
 253 const struct clk_ops clk_smd_rpm_ops = {
 254         .prepare        = clk_smd_rpm_prepare,
 255         .unprepare      = clk_smd_rpm_unprepare,
 256         .set_rate       = clk_smd_rpm_set_rate,
 257         .round_rate     = clk_smd_rpm_round_rate,
 258         .recalc_rate    = clk_smd_rpm_recalc_rate,
 259 };
 260 EXPORT_SYMBOL_GPL(clk_smd_rpm_ops);
 261
 262 const struct clk_ops clk_smd_rpm_branch_ops = {
 263         .prepare        = clk_smd_rpm_prepare,
 264         .unprepare      = clk_smd_rpm_unprepare,
 265         .round_rate     = clk_smd_rpm_round_rate,
 266         .recalc_rate    = clk_smd_rpm_recalc_rate,
 267 };
 268 EXPORT_SYMBOL_GPL(clk_smd_rpm_branch_ops);
 269
 270 struct rpm_cc {
 271         struct qcom_rpm *rpm;
 272         struct clk_onecell_data data;
 273         struct clk *clks[];
 274 };
 275
 276 struct rpm_smd_clk_desc {
 277         struct clk_smd_rpm **clks;
 278         size_t num_clks;
 279 };
 280
 281 /* msm8916 */
 282 DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
 283 DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
 284 DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
 285 DEFINE_CLK_SMD_RPM_BRANCH(msm8916, xo, xo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000);
 286 DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
 287 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1);
 288 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2);
 289 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk1, rf_clk1_a, 4);
 290 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk2, rf_clk2_a, 5);
 291 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1_pin, bb_clk1_a_pin, 1);
 292 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2);
 293 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4);
 294 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5);
 295
 296 static struct clk_smd_rpm *msm8916_clks[] = {
 297         [RPM_XO_CLK_SRC]        = &msm8916_xo,
 298         [RPM_XO_A_CLK_SRC]      = &msm8916_xo_a,
 299         [RPM_PCNOC_CLK]         = &msm8916_pcnoc_clk,
 300         [RPM_PCNOC_A_CLK]       = &msm8916_pcnoc_a_clk,
 301         [RPM_SNOC_CLK]          = &msm8916_snoc_clk,
 302         [RPM_SNOC_A_CLK]        = &msm8916_snoc_a_clk,
 303         [RPM_BIMC_CLK]          = &msm8916_bimc_clk,
 304         [RPM_BIMC_A_CLK]        = &msm8916_bimc_a_clk,
 305         [RPM_QDSS_CLK]          = &msm8916_qdss_clk,
 306         [RPM_QDSS_A_CLK]        = &msm8916_qdss_a_clk,
 307         [RPM_BB_CLK1]           = &msm8916_bb_clk1,
 308         [RPM_BB_CLK1_A]         = &msm8916_bb_clk1_a,
 309         [RPM_BB_CLK2]           = &msm8916_bb_clk2,
 310         [RPM_BB_CLK2_A]         = &msm8916_bb_clk2_a,
 311         [RPM_RF_CLK1]           = &msm8916_rf_clk1,
 312         [RPM_RF_CLK1_A]         = &msm8916_rf_clk1_a,
 313         [RPM_RF_CLK2]           = &msm8916_rf_clk2,
 314         [RPM_RF_CLK2_A]         = &msm8916_rf_clk2_a,
 315         [RPM_BB_CLK1_PIN]       = &msm8916_bb_clk1_pin,
 316         [RPM_BB_CLK1_A_PIN]     = &msm8916_bb_clk1_a_pin,
 317         [RPM_BB_CLK2_PIN]       = &msm8916_bb_clk2_pin,
 318         [RPM_BB_CLK2_A_PIN]     = &msm8916_bb_clk2_a_pin,
 319         [RPM_RF_CLK1_PIN]       = &msm8916_rf_clk1_pin,
 320         [RPM_RF_CLK1_A_PIN]     = &msm8916_rf_clk1_a_pin,
 321         [RPM_RF_CLK2_PIN]       = &msm8916_rf_clk2_pin,
 322         [RPM_RF_CLK2_A_PIN]     = &msm8916_rf_clk2_a_pin,
 323 };
 324
 325 static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
 326         .clks = msm8916_clks,
 327         .num_clks = ARRAY_SIZE(msm8916_clks),
 328 };
 329
 330 /* msm8974 */
 331 DEFINE_CLK_SMD_RPM(msm8974, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
 332 DEFINE_CLK_SMD_RPM(msm8974, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
 333 DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
 334 DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3);
 335 DEFINE_CLK_SMD_RPM(msm8974, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
 336 DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
 337 DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
 338 DEFINE_CLK_SMD_RPM_BRANCH(msm8974, cxo_clk_src, cxo_a_clk_src, QCOM_SMD_RPM_MISC_CLK, 0, 19200000);
 339 DEFINE_CLK_SMD_RPM_QDSS(msm8974, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
 340 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d0, cxo_d0_a, 1);
 341 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d1, cxo_d1_a, 2);
 342 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a0, cxo_a0_a, 4);
 343 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a1, cxo_a1_a, 5);
 344 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a2, cxo_a2_a, 6);
 345 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_a_clk1, 11);
 346 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_a_clk2, 12);
 347 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_a_clk, 7);
 348 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0_pin, cxo_d0_a_pin, 1);
 349 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1_pin, cxo_d1_a_pin, 2);
 350 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0_pin, cxo_a0_a_pin, 4);
 351 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1_pin, cxo_a1_a_pin, 5);
 352 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2_pin, cxo_a2_a_pin, 6);
 353
 354 static struct clk_smd_rpm *msm8974_clks[] = {
 355         [RPM_CXO_CLK_SRC]       = &msm8974_cxo_clk_src,
 356         [RPM_CXO_A_CLK_SRC]     = &msm8974_cxo_a_clk_src,
 357         [RPM_PNOC_CLK]          = &msm8974_pnoc_clk,
 358         [RPM_PNOC_A_CLK]        = &msm8974_pnoc_a_clk,
 359         [RPM_SNOC_CLK]          = &msm8974_snoc_clk,
 360         [RPM_SNOC_A_CLK]        = &msm8974_snoc_a_clk,
 361         [RPM_BIMC_CLK]          = &msm8974_bimc_clk,
 362         [RPM_BIMC_A_CLK]        = &msm8974_bimc_a_clk,
 363         [RPM_QDSS_CLK]          = &msm8974_qdss_clk,
 364         [RPM_QDSS_A_CLK]        = &msm8974_qdss_a_clk,
 365         [RPM_CNOC_CLK]          = &msm8974_cnoc_clk,
 366         [RPM_CNOC_A_CLK]        = &msm8974_cnoc_a_clk,
 367         [RPM_MMSSNOC_AHB_CLK]   = &msm8974_mmssnoc_ahb_clk,
 368         [RPM_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
 369         [RPM_OCMEMGX_CLK]       = &msm8974_ocmemgx_clk,
 370         [RPM_OCMEMGX_A_CLK]     = &msm8974_ocmemgx_a_clk,
 371         [RPM_GFX3D_CLK_SRC]     = &msm8974_gfx3d_clk_src,
 372         [RPM_GFX3D_A_CLK_SRC]   = &msm8974_gfx3d_a_clk_src,
 373         [RPM_CXO_D0]            = &msm8974_cxo_d0,
 374         [RPM_CXO_D0_A]          = &msm8974_cxo_d0_a,
 375         [RPM_CXO_D1]            = &msm8974_cxo_d1,
 376         [RPM_CXO_D1_A]          = &msm8974_cxo_d1_a,
 377         [RPM_CXO_A0]            = &msm8974_cxo_a0,
 378         [RPM_CXO_A0_A]          = &msm8974_cxo_a0_a,
 379         [RPM_CXO_A1]            = &msm8974_cxo_a1,
 380         [RPM_CXO_A1_A]          = &msm8974_cxo_a1_a,
 381         [RPM_CXO_A2]            = &msm8974_cxo_a2,
 382         [RPM_CXO_A2_A]          = &msm8974_cxo_a2_a,
 383         [RPM_DIV_CLK1]          = &msm8974_div_clk1,
 384         [RPM_DIV_A_CLK1]        = &msm8974_div_a_clk1,
 385         [RPM_DIV_CLK2]          = &msm8974_div_clk2,
 386         [RPM_DIV_A_CLK2]        = &msm8974_div_a_clk2,
 387         [RPM_DIFF_CLK]          = &msm8974_diff_clk,
 388         [RPM_DIFF_A_CLK]        = &msm8974_diff_a_clk,
 389         [RPM_CXO_D0_PIN]        = &msm8974_cxo_d0_pin,
 390         [RPM_CXO_D0_A_PIN]      = &msm8974_cxo_d0_a_pin,
 391         [RPM_CXO_D1_PIN]        = &msm8974_cxo_d1_pin,
 392         [RPM_CXO_D1_A_PIN]      = &msm8974_cxo_d1_a_pin,
 393         [RPM_CXO_A0_PIN]        = &msm8974_cxo_a0_pin,
 394         [RPM_CXO_A0_A_PIN]      = &msm8974_cxo_a0_a_pin,
 395         [RPM_CXO_A1_PIN]        = &msm8974_cxo_a1_pin,
 396         [RPM_CXO_A1_A_PIN]      = &msm8974_cxo_a1_a_pin,
 397         [RPM_CXO_A2_PIN]        = &msm8974_cxo_a2_pin,
 398         [RPM_CXO_A2_A_PIN]      = &msm8974_cxo_a2_a_pin,
 399 };
 400
 401 static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
 402         .clks = msm8974_clks,
 403         .num_clks = ARRAY_SIZE(msm8974_clks),
 404 };
 405
 406 /* apq8084 */
 407 DEFINE_CLK_SMD_RPM(apq8084, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
 408 DEFINE_CLK_SMD_RPM(apq8084, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
 409 DEFINE_CLK_SMD_RPM(apq8084, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
 410 DEFINE_CLK_SMD_RPM(apq8084, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3);
 411 DEFINE_CLK_SMD_RPM(apq8084, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
 412 DEFINE_CLK_SMD_RPM(apq8084, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
 413 DEFINE_CLK_SMD_RPM(apq8084, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
 414 DEFINE_CLK_SMD_RPM_BRANCH(apq8084, xo_clk_src, xo_a_clk_src, QCOM_SMD_RPM_MISC_CLK, 0, 19200000);
 415 DEFINE_CLK_SMD_RPM_QDSS(apq8084, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
 416
 417 DEFINE_CLK_SMD_RPM_XO_BUFFER(apq8084, bb_clk1, bb_clk1_a, 1);
 418 DEFINE_CLK_SMD_RPM_XO_BUFFER(apq8084, bb_clk2, bb_clk2_a, 2);
 419 DEFINE_CLK_SMD_RPM_XO_BUFFER(apq8084, rf_clk1, rf_clk1_a, 4);
 420 DEFINE_CLK_SMD_RPM_XO_BUFFER(apq8084, rf_clk2, rf_clk2_a, 5);
 421 DEFINE_CLK_SMD_RPM_XO_BUFFER(apq8084, rf_clk3, rf_clk3_a, 6);
 422 DEFINE_CLK_SMD_RPM_XO_BUFFER(apq8084, diff_clk1, diff_clk1_a, 7);
 423 DEFINE_CLK_SMD_RPM_XO_BUFFER(apq8084, div_clk1, div_clk1_a, 11);
 424 DEFINE_CLK_SMD_RPM_XO_BUFFER(apq8084, div_clk2, div_clk2_a, 12);
 425 DEFINE_CLK_SMD_RPM_XO_BUFFER(apq8084, div_clk3, div_clk3_a, 13);
 426
 427 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(apq8084, bb_clk1_pin, bb_clk1_a_pin, 1);
 428 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(apq8084, bb_clk2_pin, bb_clk2_a_pin, 2);
 429 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(apq8084, rf_clk1_pin, rf_clk1_a_pin, 4);
 430 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(apq8084, rf_clk2_pin, rf_clk2_a_pin, 5);
 431 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(apq8084, rf_clk3_pin, rf_clk3_a_pin, 6);
 432
 433 static struct clk_smd_rpm *apq8084_clks[] = {
 434         [RPM_XO_CLK_SRC]        = &apq8084_xo_clk_src,
 435         [RPM_XO_A_CLK_SRC]      = &apq8084_xo_a_clk_src,
 436         [RPM_PNOC_CLK]          = &apq8084_pnoc_clk,
 437         [RPM_PNOC_A_CLK]        = &apq8084_pnoc_a_clk,
 438         [RPM_SNOC_CLK]          = &apq8084_snoc_clk,
 439         [RPM_SNOC_A_CLK]        = &apq8084_snoc_a_clk,
 440         [RPM_BIMC_CLK]          = &apq8084_bimc_clk,
 441         [RPM_BIMC_A_CLK]        = &apq8084_bimc_a_clk,
 442         [RPM_QDSS_CLK]          = &apq8084_qdss_clk,
 443         [RPM_QDSS_A_CLK]        = &apq8084_qdss_a_clk,
 444         [RPM_CNOC_CLK]          = &apq8084_cnoc_clk,
 445         [RPM_CNOC_A_CLK]        = &apq8084_cnoc_a_clk,
 446         [RPM_MMSSNOC_AHB_CLK]   = &apq8084_mmssnoc_ahb_clk,
 447         [RPM_MMSSNOC_AHB_A_CLK] = &apq8084_mmssnoc_ahb_a_clk,
 448         [RPM_OCMEMGX_CLK]       = &apq8084_ocmemgx_clk,
 449         [RPM_OCMEMGX_A_CLK]     = &apq8084_ocmemgx_a_clk,
 450         [RPM_GFX3D_CLK_SRC]     = &apq8084_gfx3d_clk_src,
 451         [RPM_GFX3D_A_CLK_SRC]   = &apq8084_gfx3d_a_clk_src,
 452         [RPM_BB_CLK1]           = &apq8084_bb_clk1,
 453         [RPM_BB_CLK1_A]         = &apq8084_bb_clk1_a,
 454         [RPM_BB_CLK2]           = &apq8084_bb_clk2,
 455         [RPM_BB_CLK2_A]         = &apq8084_bb_clk2_a,
 456         [RPM_RF_CLK1]           = &apq8084_rf_clk1,
 457         [RPM_RF_CLK1_A]         = &apq8084_rf_clk1_a,
 458         [RPM_RF_CLK2]           = &apq8084_rf_clk2,
 459         [RPM_RF_CLK2_A]         = &apq8084_rf_clk2_a,
 460         [RPM_RF_CLK3]           = &apq8084_rf_clk3,
 461         [RPM_RF_CLK3_A]         = &apq8084_rf_clk3_a,
 462         [RPM_DIFF_CLK1]         = &apq8084_diff_clk1,
 463         [RPM_DIFF_CLK1_A]       = &apq8084_diff_clk1_a,
 464         [RPM_DIV_CLK1]          = &apq8084_div_clk1,
 465         [RPM_DIV_CLK1_A]        = &apq8084_div_clk1_a,
 466         [RPM_DIV_CLK2]          = &apq8084_div_clk2,
 467         [RPM_DIV_CLK2_A]        = &apq8084_div_clk2_a,
 468         [RPM_DIV_CLK3]          = &apq8084_div_clk3,
 469         [RPM_DIV_CLK3_A]        = &apq8084_div_clk3_a,
 470         [RPM_BB_CLK1_PIN]       = &apq8084_bb_clk1_pin,
 471         [RPM_BB_CLK1_A_PIN]     = &apq8084_bb_clk1_a_pin,
 472         [RPM_BB_CLK2_PIN]       = &apq8084_bb_clk2_pin,
 473         [RPM_BB_CLK2_A_PIN]     = &apq8084_bb_clk2_a_pin,
 474         [RPM_RF_CLK1_PIN]       = &apq8084_rf_clk1_pin,
 475         [RPM_RF_CLK1_A_PIN]     = &apq8084_rf_clk1_a_pin,
 476         [RPM_RF_CLK2_PIN]       = &apq8084_rf_clk2_pin,
 477         [RPM_RF_CLK2_A_PIN]     = &apq8084_rf_clk2_a_pin,
 478         [RPM_RF_CLK3_PIN]       = &apq8084_rf_clk3_pin,
 479         [RPM_RF_CLK3_A_PIN]     = &apq8084_rf_clk3_a_pin,
 480 };
 481
 482 static const struct rpm_smd_clk_desc rpm_clk_apq8084 = {
 483         .clks = apq8084_clks,
 484         .num_clks = ARRAY_SIZE(apq8084_clks),
 485 };
 486
 487 static const struct of_device_id rpm_smd_clk_match_table[] = {
 488         { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916},
 489         { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974},
 490         { .compatible = "qcom,rpmcc-apq8084", .data = &rpm_clk_apq8084},
 491         { }
 492 };
 493 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
 494
 495 static int rpm_smd_clk_probe(struct platform_device *pdev)
 496 {
 497         struct clk **clks;
 498         struct clk *clk;
 499         struct rpm_cc *rcc;
 500         struct clk_onecell_data *data;
 501         int ret, i;
 502         size_t num_clks;
 503         struct qcom_smd_rpm *rpm;
 504         struct clk_smd_rpm **rpm_smd_clks;
 505         const struct rpm_smd_clk_desc *desc;
 506
 507         rpm = dev_get_drvdata(pdev->dev.parent);
 508         if (!rpm) {
 509                 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
 510                 return -ENODEV;
 511         }
 512
 513         desc = of_device_get_match_data(&pdev->dev);
 514         if (!desc)
 515                 return -EINVAL;
 516
 517         rpm_smd_clks = desc->clks;
 518         num_clks = desc->num_clks;
 519
 520         rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc) + sizeof(*clks) * num_clks,
 521                            GFP_KERNEL);
 522         if (!rcc)
 523                 return -ENOMEM;
 524
 525         clks = rcc->clks;
 526         data = &rcc->data;
 527         data->clks = clks;
 528         data->clk_num = num_clks;
 529
 530         for (i = 0; i < num_clks; i++) {
 531                 if (!rpm_smd_clks[i]) {
 532                         clks[i] = ERR_PTR(-ENOENT);
 533                         continue;
 534                 }
 535
 536                 rpm_smd_clks[i]->rpm = rpm;
 537                 clk = devm_clk_register(&pdev->dev, &rpm_smd_clks[i]->hw);
 538                 if (IS_ERR(clk)) {
 539                         ret = PTR_ERR(clk);
 540                         goto err;
 541                 }
 542
 543                 clks[i] = clk;
 544         }
 545
 546         ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
 547                                   data);
 548         if (ret)
 549                 goto err;
 550
 551         ret = clk_smd_rpm_enable_scaling(rpm);
 552         if (ret) {
 553                 of_clk_del_provider(pdev->dev.of_node);
 554                 goto err;
 555         }
 556
 557         return 0;
 558 err:
 559         dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);
 560         return ret;
 561 }
 562
 563 static int rpm_smd_clk_remove(struct platform_device *pdev)
 564 {
 565         of_clk_del_provider(pdev->dev.of_node);
 566         return 0;
 567 }
 568
 569 static struct platform_driver rpm_smd_clk_driver = {
 570         .driver = {
 571                 .name = "qcom-clk-smd-rpm",
 572                 .of_match_table = rpm_smd_clk_match_table,
 573         },
 574         .probe = rpm_smd_clk_probe,
 575         .remove = rpm_smd_clk_remove,
 576 };
 577
 578 static int __init rpm_smd_clk_init(void)
 579 {
 580         return platform_driver_register(&rpm_smd_clk_driver);
 581 }
 582 core_initcall(rpm_smd_clk_init);
 583
 584 static void __exit rpm_smd_clk_exit(void)
 585 {
 586         platform_driver_unregister(&rpm_smd_clk_driver);
 587 }
 588 module_exit(rpm_smd_clk_exit);
 589
 590 MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver");
 591 MODULE_LICENSE("GPL v2");
 592 MODULE_ALIAS("platform:qcom-clk-smd-rpm");