2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
26 #include <dt-bindings/reset/qcom,gcc-apq8084.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
47 static const struct parent_map gcc_xo_gpll0_map[] = {
52 static const char * const gcc_xo_gpll0[] = {
57 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
63 static const char * const gcc_xo_gpll0_gpll4[] = {
69 static const struct parent_map gcc_xo_sata_asic0_map[] = {
71 { P_SATA_ASIC0_CLK, 2 }
74 static const char * const gcc_xo_sata_asic0[] = {
79 static const struct parent_map gcc_xo_sata_rx_map[] = {
84 static const char * const gcc_xo_sata_rx[] = {
89 static const struct parent_map gcc_xo_pcie_map[] = {
91 { P_PCIE_0_1_PIPE_CLK, 2 }
94 static const char * const gcc_xo_pcie[] = {
99 static const struct parent_map gcc_xo_pcie_sleep_map[] = {
104 static const char * const gcc_xo_pcie_sleep[] = {
109 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
111 static struct clk_pll gpll0 = {
115 .config_reg = 0x0014,
117 .status_reg = 0x001c,
119 .clkr.hw.init = &(struct clk_init_data){
121 .parent_names = (const char *[]){ "xo" },
127 static struct clk_regmap gpll0_vote = {
128 .enable_reg = 0x1480,
129 .enable_mask = BIT(0),
130 .hw.init = &(struct clk_init_data){
131 .name = "gpll0_vote",
132 .parent_names = (const char *[]){ "gpll0" },
134 .ops = &clk_pll_vote_ops,
138 static struct clk_rcg2 config_noc_clk_src = {
141 .parent_map = gcc_xo_gpll0_map,
142 .clkr.hw.init = &(struct clk_init_data){
143 .name = "config_noc_clk_src",
144 .parent_names = gcc_xo_gpll0,
146 .ops = &clk_rcg2_ops,
150 static struct clk_rcg2 periph_noc_clk_src = {
153 .parent_map = gcc_xo_gpll0_map,
154 .clkr.hw.init = &(struct clk_init_data){
155 .name = "periph_noc_clk_src",
156 .parent_names = gcc_xo_gpll0,
158 .ops = &clk_rcg2_ops,
162 static struct clk_rcg2 system_noc_clk_src = {
165 .parent_map = gcc_xo_gpll0_map,
166 .clkr.hw.init = &(struct clk_init_data){
167 .name = "system_noc_clk_src",
168 .parent_names = gcc_xo_gpll0,
170 .ops = &clk_rcg2_ops,
174 static struct clk_pll gpll1 = {
178 .config_reg = 0x0054,
180 .status_reg = 0x005c,
182 .clkr.hw.init = &(struct clk_init_data){
184 .parent_names = (const char *[]){ "xo" },
190 static struct clk_regmap gpll1_vote = {
191 .enable_reg = 0x1480,
192 .enable_mask = BIT(1),
193 .hw.init = &(struct clk_init_data){
194 .name = "gpll1_vote",
195 .parent_names = (const char *[]){ "gpll1" },
197 .ops = &clk_pll_vote_ops,
201 static struct clk_pll gpll4 = {
205 .config_reg = 0x1dd4,
207 .status_reg = 0x1ddc,
209 .clkr.hw.init = &(struct clk_init_data){
211 .parent_names = (const char *[]){ "xo" },
217 static struct clk_regmap gpll4_vote = {
218 .enable_reg = 0x1480,
219 .enable_mask = BIT(4),
220 .hw.init = &(struct clk_init_data){
221 .name = "gpll4_vote",
222 .parent_names = (const char *[]){ "gpll4" },
224 .ops = &clk_pll_vote_ops,
228 static const struct freq_tbl ftbl_gcc_ufs_axi_clk[] = {
229 F(100000000, P_GPLL0, 6, 0, 0),
230 F(200000000, P_GPLL0, 3, 0, 0),
231 F(240000000, P_GPLL0, 2.5, 0, 0),
235 static struct clk_rcg2 ufs_axi_clk_src = {
239 .parent_map = gcc_xo_gpll0_map,
240 .freq_tbl = ftbl_gcc_ufs_axi_clk,
241 .clkr.hw.init = &(struct clk_init_data){
242 .name = "ufs_axi_clk_src",
243 .parent_names = gcc_xo_gpll0,
245 .ops = &clk_rcg2_ops,
249 static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
250 F(125000000, P_GPLL0, 1, 5, 24),
254 static struct clk_rcg2 usb30_master_clk_src = {
258 .parent_map = gcc_xo_gpll0_map,
259 .freq_tbl = ftbl_gcc_usb30_master_clk,
260 .clkr.hw.init = &(struct clk_init_data){
261 .name = "usb30_master_clk_src",
262 .parent_names = gcc_xo_gpll0,
264 .ops = &clk_rcg2_ops,
268 static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk[] = {
269 F(125000000, P_GPLL0, 1, 5, 24),
273 static struct clk_rcg2 usb30_sec_master_clk_src = {
277 .parent_map = gcc_xo_gpll0_map,
278 .freq_tbl = ftbl_gcc_usb30_sec_master_clk,
279 .clkr.hw.init = &(struct clk_init_data){
280 .name = "usb30_sec_master_clk_src",
281 .parent_names = gcc_xo_gpll0,
283 .ops = &clk_rcg2_ops,
287 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
290 .enable_reg = 0x1bd0,
291 .enable_mask = BIT(0),
292 .hw.init = &(struct clk_init_data){
293 .name = "gcc_usb30_sec_mock_utmi_clk",
294 .parent_names = (const char *[]){
295 "usb30_sec_mock_utmi_clk_src",
298 .flags = CLK_SET_RATE_PARENT,
299 .ops = &clk_branch2_ops,
304 static struct clk_branch gcc_usb30_sec_sleep_clk = {
307 .enable_reg = 0x1bcc,
308 .enable_mask = BIT(0),
309 .hw.init = &(struct clk_init_data){
310 .name = "gcc_usb30_sec_sleep_clk",
311 .parent_names = (const char *[]){
315 .flags = CLK_SET_RATE_PARENT,
316 .ops = &clk_branch2_ops,
321 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
322 F(19200000, P_XO, 1, 0, 0),
323 F(50000000, P_GPLL0, 12, 0, 0),
327 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
330 .parent_map = gcc_xo_gpll0_map,
331 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
332 .clkr.hw.init = &(struct clk_init_data){
333 .name = "blsp1_qup1_i2c_apps_clk_src",
334 .parent_names = gcc_xo_gpll0,
336 .ops = &clk_rcg2_ops,
340 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = {
341 F(960000, P_XO, 10, 1, 2),
342 F(4800000, P_XO, 4, 0, 0),
343 F(9600000, P_XO, 2, 0, 0),
344 F(15000000, P_GPLL0, 10, 1, 4),
345 F(19200000, P_XO, 1, 0, 0),
346 F(25000000, P_GPLL0, 12, 1, 2),
347 F(50000000, P_GPLL0, 12, 0, 0),
351 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
355 .parent_map = gcc_xo_gpll0_map,
356 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
357 .clkr.hw.init = &(struct clk_init_data){
358 .name = "blsp1_qup1_spi_apps_clk_src",
359 .parent_names = gcc_xo_gpll0,
361 .ops = &clk_rcg2_ops,
365 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
368 .parent_map = gcc_xo_gpll0_map,
369 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
370 .clkr.hw.init = &(struct clk_init_data){
371 .name = "blsp1_qup2_i2c_apps_clk_src",
372 .parent_names = gcc_xo_gpll0,
374 .ops = &clk_rcg2_ops,
378 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
382 .parent_map = gcc_xo_gpll0_map,
383 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
384 .clkr.hw.init = &(struct clk_init_data){
385 .name = "blsp1_qup2_spi_apps_clk_src",
386 .parent_names = gcc_xo_gpll0,
388 .ops = &clk_rcg2_ops,
392 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
395 .parent_map = gcc_xo_gpll0_map,
396 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
397 .clkr.hw.init = &(struct clk_init_data){
398 .name = "blsp1_qup3_i2c_apps_clk_src",
399 .parent_names = gcc_xo_gpll0,
401 .ops = &clk_rcg2_ops,
405 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
409 .parent_map = gcc_xo_gpll0_map,
410 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
411 .clkr.hw.init = &(struct clk_init_data){
412 .name = "blsp1_qup3_spi_apps_clk_src",
413 .parent_names = gcc_xo_gpll0,
415 .ops = &clk_rcg2_ops,
419 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
422 .parent_map = gcc_xo_gpll0_map,
423 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
424 .clkr.hw.init = &(struct clk_init_data){
425 .name = "blsp1_qup4_i2c_apps_clk_src",
426 .parent_names = gcc_xo_gpll0,
428 .ops = &clk_rcg2_ops,
432 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
436 .parent_map = gcc_xo_gpll0_map,
437 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
438 .clkr.hw.init = &(struct clk_init_data){
439 .name = "blsp1_qup4_spi_apps_clk_src",
440 .parent_names = gcc_xo_gpll0,
442 .ops = &clk_rcg2_ops,
446 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
449 .parent_map = gcc_xo_gpll0_map,
450 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
451 .clkr.hw.init = &(struct clk_init_data){
452 .name = "blsp1_qup5_i2c_apps_clk_src",
453 .parent_names = gcc_xo_gpll0,
455 .ops = &clk_rcg2_ops,
459 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
463 .parent_map = gcc_xo_gpll0_map,
464 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
465 .clkr.hw.init = &(struct clk_init_data){
466 .name = "blsp1_qup5_spi_apps_clk_src",
467 .parent_names = gcc_xo_gpll0,
469 .ops = &clk_rcg2_ops,
473 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
476 .parent_map = gcc_xo_gpll0_map,
477 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
478 .clkr.hw.init = &(struct clk_init_data){
479 .name = "blsp1_qup6_i2c_apps_clk_src",
480 .parent_names = gcc_xo_gpll0,
482 .ops = &clk_rcg2_ops,
486 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
490 .parent_map = gcc_xo_gpll0_map,
491 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
492 .clkr.hw.init = &(struct clk_init_data){
493 .name = "blsp1_qup6_spi_apps_clk_src",
494 .parent_names = gcc_xo_gpll0,
496 .ops = &clk_rcg2_ops,
500 static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = {
501 F(3686400, P_GPLL0, 1, 96, 15625),
502 F(7372800, P_GPLL0, 1, 192, 15625),
503 F(14745600, P_GPLL0, 1, 384, 15625),
504 F(16000000, P_GPLL0, 5, 2, 15),
505 F(19200000, P_XO, 1, 0, 0),
506 F(24000000, P_GPLL0, 5, 1, 5),
507 F(32000000, P_GPLL0, 1, 4, 75),
508 F(40000000, P_GPLL0, 15, 0, 0),
509 F(46400000, P_GPLL0, 1, 29, 375),
510 F(48000000, P_GPLL0, 12.5, 0, 0),
511 F(51200000, P_GPLL0, 1, 32, 375),
512 F(56000000, P_GPLL0, 1, 7, 75),
513 F(58982400, P_GPLL0, 1, 1536, 15625),
514 F(60000000, P_GPLL0, 10, 0, 0),
515 F(63160000, P_GPLL0, 9.5, 0, 0),
519 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
523 .parent_map = gcc_xo_gpll0_map,
524 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
525 .clkr.hw.init = &(struct clk_init_data){
526 .name = "blsp1_uart1_apps_clk_src",
527 .parent_names = gcc_xo_gpll0,
529 .ops = &clk_rcg2_ops,
533 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
537 .parent_map = gcc_xo_gpll0_map,
538 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
539 .clkr.hw.init = &(struct clk_init_data){
540 .name = "blsp1_uart2_apps_clk_src",
541 .parent_names = gcc_xo_gpll0,
543 .ops = &clk_rcg2_ops,
547 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
551 .parent_map = gcc_xo_gpll0_map,
552 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
553 .clkr.hw.init = &(struct clk_init_data){
554 .name = "blsp1_uart3_apps_clk_src",
555 .parent_names = gcc_xo_gpll0,
557 .ops = &clk_rcg2_ops,
561 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
565 .parent_map = gcc_xo_gpll0_map,
566 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
567 .clkr.hw.init = &(struct clk_init_data){
568 .name = "blsp1_uart4_apps_clk_src",
569 .parent_names = gcc_xo_gpll0,
571 .ops = &clk_rcg2_ops,
575 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
579 .parent_map = gcc_xo_gpll0_map,
580 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
581 .clkr.hw.init = &(struct clk_init_data){
582 .name = "blsp1_uart5_apps_clk_src",
583 .parent_names = gcc_xo_gpll0,
585 .ops = &clk_rcg2_ops,
589 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
593 .parent_map = gcc_xo_gpll0_map,
594 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
595 .clkr.hw.init = &(struct clk_init_data){
596 .name = "blsp1_uart6_apps_clk_src",
597 .parent_names = gcc_xo_gpll0,
599 .ops = &clk_rcg2_ops,
603 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
606 .parent_map = gcc_xo_gpll0_map,
607 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
608 .clkr.hw.init = &(struct clk_init_data){
609 .name = "blsp2_qup1_i2c_apps_clk_src",
610 .parent_names = gcc_xo_gpll0,
612 .ops = &clk_rcg2_ops,
616 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
620 .parent_map = gcc_xo_gpll0_map,
621 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
622 .clkr.hw.init = &(struct clk_init_data){
623 .name = "blsp2_qup1_spi_apps_clk_src",
624 .parent_names = gcc_xo_gpll0,
626 .ops = &clk_rcg2_ops,
630 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
633 .parent_map = gcc_xo_gpll0_map,
634 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
635 .clkr.hw.init = &(struct clk_init_data){
636 .name = "blsp2_qup2_i2c_apps_clk_src",
637 .parent_names = gcc_xo_gpll0,
639 .ops = &clk_rcg2_ops,
643 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
647 .parent_map = gcc_xo_gpll0_map,
648 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
649 .clkr.hw.init = &(struct clk_init_data){
650 .name = "blsp2_qup2_spi_apps_clk_src",
651 .parent_names = gcc_xo_gpll0,
653 .ops = &clk_rcg2_ops,
657 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
660 .parent_map = gcc_xo_gpll0_map,
661 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
662 .clkr.hw.init = &(struct clk_init_data){
663 .name = "blsp2_qup3_i2c_apps_clk_src",
664 .parent_names = gcc_xo_gpll0,
666 .ops = &clk_rcg2_ops,
670 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
674 .parent_map = gcc_xo_gpll0_map,
675 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
676 .clkr.hw.init = &(struct clk_init_data){
677 .name = "blsp2_qup3_spi_apps_clk_src",
678 .parent_names = gcc_xo_gpll0,
680 .ops = &clk_rcg2_ops,
684 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
687 .parent_map = gcc_xo_gpll0_map,
688 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
689 .clkr.hw.init = &(struct clk_init_data){
690 .name = "blsp2_qup4_i2c_apps_clk_src",
691 .parent_names = gcc_xo_gpll0,
693 .ops = &clk_rcg2_ops,
697 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
701 .parent_map = gcc_xo_gpll0_map,
702 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
703 .clkr.hw.init = &(struct clk_init_data){
704 .name = "blsp2_qup4_spi_apps_clk_src",
705 .parent_names = gcc_xo_gpll0,
707 .ops = &clk_rcg2_ops,
711 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
714 .parent_map = gcc_xo_gpll0_map,
715 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
716 .clkr.hw.init = &(struct clk_init_data){
717 .name = "blsp2_qup5_i2c_apps_clk_src",
718 .parent_names = gcc_xo_gpll0,
720 .ops = &clk_rcg2_ops,
724 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
728 .parent_map = gcc_xo_gpll0_map,
729 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
730 .clkr.hw.init = &(struct clk_init_data){
731 .name = "blsp2_qup5_spi_apps_clk_src",
732 .parent_names = gcc_xo_gpll0,
734 .ops = &clk_rcg2_ops,
738 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
741 .parent_map = gcc_xo_gpll0_map,
742 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
743 .clkr.hw.init = &(struct clk_init_data){
744 .name = "blsp2_qup6_i2c_apps_clk_src",
745 .parent_names = gcc_xo_gpll0,
747 .ops = &clk_rcg2_ops,
751 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
755 .parent_map = gcc_xo_gpll0_map,
756 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
757 .clkr.hw.init = &(struct clk_init_data){
758 .name = "blsp2_qup6_spi_apps_clk_src",
759 .parent_names = gcc_xo_gpll0,
761 .ops = &clk_rcg2_ops,
765 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
769 .parent_map = gcc_xo_gpll0_map,
770 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
771 .clkr.hw.init = &(struct clk_init_data){
772 .name = "blsp2_uart1_apps_clk_src",
773 .parent_names = gcc_xo_gpll0,
775 .ops = &clk_rcg2_ops,
779 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
783 .parent_map = gcc_xo_gpll0_map,
784 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
785 .clkr.hw.init = &(struct clk_init_data){
786 .name = "blsp2_uart2_apps_clk_src",
787 .parent_names = gcc_xo_gpll0,
789 .ops = &clk_rcg2_ops,
793 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
797 .parent_map = gcc_xo_gpll0_map,
798 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
799 .clkr.hw.init = &(struct clk_init_data){
800 .name = "blsp2_uart3_apps_clk_src",
801 .parent_names = gcc_xo_gpll0,
803 .ops = &clk_rcg2_ops,
807 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
811 .parent_map = gcc_xo_gpll0_map,
812 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
813 .clkr.hw.init = &(struct clk_init_data){
814 .name = "blsp2_uart4_apps_clk_src",
815 .parent_names = gcc_xo_gpll0,
817 .ops = &clk_rcg2_ops,
821 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
825 .parent_map = gcc_xo_gpll0_map,
826 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
827 .clkr.hw.init = &(struct clk_init_data){
828 .name = "blsp2_uart5_apps_clk_src",
829 .parent_names = gcc_xo_gpll0,
831 .ops = &clk_rcg2_ops,
835 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
839 .parent_map = gcc_xo_gpll0_map,
840 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
841 .clkr.hw.init = &(struct clk_init_data){
842 .name = "blsp2_uart6_apps_clk_src",
843 .parent_names = gcc_xo_gpll0,
845 .ops = &clk_rcg2_ops,
849 static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
850 F(50000000, P_GPLL0, 12, 0, 0),
851 F(85710000, P_GPLL0, 7, 0, 0),
852 F(100000000, P_GPLL0, 6, 0, 0),
853 F(171430000, P_GPLL0, 3.5, 0, 0),
857 static struct clk_rcg2 ce1_clk_src = {
860 .parent_map = gcc_xo_gpll0_map,
861 .freq_tbl = ftbl_gcc_ce1_clk,
862 .clkr.hw.init = &(struct clk_init_data){
863 .name = "ce1_clk_src",
864 .parent_names = gcc_xo_gpll0,
866 .ops = &clk_rcg2_ops,
870 static const struct freq_tbl ftbl_gcc_ce2_clk[] = {
871 F(50000000, P_GPLL0, 12, 0, 0),
872 F(85710000, P_GPLL0, 7, 0, 0),
873 F(100000000, P_GPLL0, 6, 0, 0),
874 F(171430000, P_GPLL0, 3.5, 0, 0),
878 static struct clk_rcg2 ce2_clk_src = {
881 .parent_map = gcc_xo_gpll0_map,
882 .freq_tbl = ftbl_gcc_ce2_clk,
883 .clkr.hw.init = &(struct clk_init_data){
884 .name = "ce2_clk_src",
885 .parent_names = gcc_xo_gpll0,
887 .ops = &clk_rcg2_ops,
891 static const struct freq_tbl ftbl_gcc_ce3_clk[] = {
892 F(50000000, P_GPLL0, 12, 0, 0),
893 F(85710000, P_GPLL0, 7, 0, 0),
894 F(100000000, P_GPLL0, 6, 0, 0),
895 F(171430000, P_GPLL0, 3.5, 0, 0),
899 static struct clk_rcg2 ce3_clk_src = {
902 .parent_map = gcc_xo_gpll0_map,
903 .freq_tbl = ftbl_gcc_ce3_clk,
904 .clkr.hw.init = &(struct clk_init_data){
905 .name = "ce3_clk_src",
906 .parent_names = gcc_xo_gpll0,
908 .ops = &clk_rcg2_ops,
912 static const struct freq_tbl ftbl_gcc_gp_clk[] = {
913 F(19200000, P_XO, 1, 0, 0),
914 F(100000000, P_GPLL0, 6, 0, 0),
915 F(200000000, P_GPLL0, 3, 0, 0),
919 static struct clk_rcg2 gp1_clk_src = {
923 .parent_map = gcc_xo_gpll0_map,
924 .freq_tbl = ftbl_gcc_gp_clk,
925 .clkr.hw.init = &(struct clk_init_data){
926 .name = "gp1_clk_src",
927 .parent_names = gcc_xo_gpll0,
929 .ops = &clk_rcg2_ops,
933 static struct clk_rcg2 gp2_clk_src = {
937 .parent_map = gcc_xo_gpll0_map,
938 .freq_tbl = ftbl_gcc_gp_clk,
939 .clkr.hw.init = &(struct clk_init_data){
940 .name = "gp2_clk_src",
941 .parent_names = gcc_xo_gpll0,
943 .ops = &clk_rcg2_ops,
947 static struct clk_rcg2 gp3_clk_src = {
951 .parent_map = gcc_xo_gpll0_map,
952 .freq_tbl = ftbl_gcc_gp_clk,
953 .clkr.hw.init = &(struct clk_init_data){
954 .name = "gp3_clk_src",
955 .parent_names = gcc_xo_gpll0,
957 .ops = &clk_rcg2_ops,
961 static const struct freq_tbl ftbl_gcc_pcie_0_1_aux_clk[] = {
962 F(1010000, P_XO, 1, 1, 19),
966 static struct clk_rcg2 pcie_0_aux_clk_src = {
970 .parent_map = gcc_xo_pcie_sleep_map,
971 .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
972 .clkr.hw.init = &(struct clk_init_data){
973 .name = "pcie_0_aux_clk_src",
974 .parent_names = gcc_xo_pcie_sleep,
976 .ops = &clk_rcg2_ops,
980 static struct clk_rcg2 pcie_1_aux_clk_src = {
984 .parent_map = gcc_xo_pcie_sleep_map,
985 .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
986 .clkr.hw.init = &(struct clk_init_data){
987 .name = "pcie_1_aux_clk_src",
988 .parent_names = gcc_xo_pcie_sleep,
990 .ops = &clk_rcg2_ops,
994 static const struct freq_tbl ftbl_gcc_pcie_0_1_pipe_clk[] = {
995 F(125000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
996 F(250000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
1000 static struct clk_rcg2 pcie_0_pipe_clk_src = {
1003 .parent_map = gcc_xo_pcie_map,
1004 .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
1005 .clkr.hw.init = &(struct clk_init_data){
1006 .name = "pcie_0_pipe_clk_src",
1007 .parent_names = gcc_xo_pcie,
1009 .ops = &clk_rcg2_ops,
1013 static struct clk_rcg2 pcie_1_pipe_clk_src = {
1016 .parent_map = gcc_xo_pcie_map,
1017 .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
1018 .clkr.hw.init = &(struct clk_init_data){
1019 .name = "pcie_1_pipe_clk_src",
1020 .parent_names = gcc_xo_pcie,
1022 .ops = &clk_rcg2_ops,
1026 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1027 F(60000000, P_GPLL0, 10, 0, 0),
1031 static struct clk_rcg2 pdm2_clk_src = {
1034 .parent_map = gcc_xo_gpll0_map,
1035 .freq_tbl = ftbl_gcc_pdm2_clk,
1036 .clkr.hw.init = &(struct clk_init_data){
1037 .name = "pdm2_clk_src",
1038 .parent_names = gcc_xo_gpll0,
1040 .ops = &clk_rcg2_ops,
1044 static const struct freq_tbl ftbl_gcc_sata_asic0_clk[] = {
1045 F(75000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1046 F(150000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1047 F(300000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1051 static struct clk_rcg2 sata_asic0_clk_src = {
1054 .parent_map = gcc_xo_sata_asic0_map,
1055 .freq_tbl = ftbl_gcc_sata_asic0_clk,
1056 .clkr.hw.init = &(struct clk_init_data){
1057 .name = "sata_asic0_clk_src",
1058 .parent_names = gcc_xo_sata_asic0,
1060 .ops = &clk_rcg2_ops,
1064 static const struct freq_tbl ftbl_gcc_sata_pmalive_clk[] = {
1065 F(19200000, P_XO, 1, 0, 0),
1066 F(50000000, P_GPLL0, 12, 0, 0),
1067 F(100000000, P_GPLL0, 6, 0, 0),
1071 static struct clk_rcg2 sata_pmalive_clk_src = {
1074 .parent_map = gcc_xo_gpll0_map,
1075 .freq_tbl = ftbl_gcc_sata_pmalive_clk,
1076 .clkr.hw.init = &(struct clk_init_data){
1077 .name = "sata_pmalive_clk_src",
1078 .parent_names = gcc_xo_gpll0,
1080 .ops = &clk_rcg2_ops,
1084 static const struct freq_tbl ftbl_gcc_sata_rx_clk[] = {
1085 F(75000000, P_SATA_RX_CLK, 1, 0, 0),
1086 F(150000000, P_SATA_RX_CLK, 1, 0, 0),
1087 F(300000000, P_SATA_RX_CLK, 1, 0, 0),
1091 static struct clk_rcg2 sata_rx_clk_src = {
1094 .parent_map = gcc_xo_sata_rx_map,
1095 .freq_tbl = ftbl_gcc_sata_rx_clk,
1096 .clkr.hw.init = &(struct clk_init_data){
1097 .name = "sata_rx_clk_src",
1098 .parent_names = gcc_xo_sata_rx,
1100 .ops = &clk_rcg2_ops,
1104 static const struct freq_tbl ftbl_gcc_sata_rx_oob_clk[] = {
1105 F(100000000, P_GPLL0, 6, 0, 0),
1109 static struct clk_rcg2 sata_rx_oob_clk_src = {
1112 .parent_map = gcc_xo_gpll0_map,
1113 .freq_tbl = ftbl_gcc_sata_rx_oob_clk,
1114 .clkr.hw.init = &(struct clk_init_data){
1115 .name = "sata_rx_oob_clk_src",
1116 .parent_names = gcc_xo_gpll0,
1118 .ops = &clk_rcg2_ops,
1122 static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
1123 F(144000, P_XO, 16, 3, 25),
1124 F(400000, P_XO, 12, 1, 4),
1125 F(20000000, P_GPLL0, 15, 1, 2),
1126 F(25000000, P_GPLL0, 12, 1, 2),
1127 F(50000000, P_GPLL0, 12, 0, 0),
1128 F(100000000, P_GPLL0, 6, 0, 0),
1129 F(192000000, P_GPLL4, 4, 0, 0),
1130 F(200000000, P_GPLL0, 3, 0, 0),
1131 F(384000000, P_GPLL4, 2, 0, 0),
1135 static struct clk_rcg2 sdcc1_apps_clk_src = {
1139 .parent_map = gcc_xo_gpll0_gpll4_map,
1140 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1141 .clkr.hw.init = &(struct clk_init_data){
1142 .name = "sdcc1_apps_clk_src",
1143 .parent_names = gcc_xo_gpll0_gpll4,
1145 .ops = &clk_rcg2_ops,
1149 static struct clk_rcg2 sdcc2_apps_clk_src = {
1153 .parent_map = gcc_xo_gpll0_map,
1154 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1155 .clkr.hw.init = &(struct clk_init_data){
1156 .name = "sdcc2_apps_clk_src",
1157 .parent_names = gcc_xo_gpll0,
1159 .ops = &clk_rcg2_ops,
1163 static struct clk_rcg2 sdcc3_apps_clk_src = {
1167 .parent_map = gcc_xo_gpll0_map,
1168 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1169 .clkr.hw.init = &(struct clk_init_data){
1170 .name = "sdcc3_apps_clk_src",
1171 .parent_names = gcc_xo_gpll0,
1173 .ops = &clk_rcg2_ops,
1177 static struct clk_rcg2 sdcc4_apps_clk_src = {
1181 .parent_map = gcc_xo_gpll0_map,
1182 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1183 .clkr.hw.init = &(struct clk_init_data){
1184 .name = "sdcc4_apps_clk_src",
1185 .parent_names = gcc_xo_gpll0,
1187 .ops = &clk_rcg2_ops,
1191 static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = {
1192 F(105000, P_XO, 2, 1, 91),
1196 static struct clk_rcg2 tsif_ref_clk_src = {
1200 .parent_map = gcc_xo_gpll0_map,
1201 .freq_tbl = ftbl_gcc_tsif_ref_clk,
1202 .clkr.hw.init = &(struct clk_init_data){
1203 .name = "tsif_ref_clk_src",
1204 .parent_names = gcc_xo_gpll0,
1206 .ops = &clk_rcg2_ops,
1210 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
1211 F(60000000, P_GPLL0, 10, 0, 0),
1215 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1218 .parent_map = gcc_xo_gpll0_map,
1219 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
1220 .clkr.hw.init = &(struct clk_init_data){
1221 .name = "usb30_mock_utmi_clk_src",
1222 .parent_names = gcc_xo_gpll0,
1224 .ops = &clk_rcg2_ops,
1228 static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk[] = {
1229 F(125000000, P_GPLL0, 1, 5, 24),
1233 static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = {
1236 .parent_map = gcc_xo_gpll0_map,
1237 .freq_tbl = ftbl_gcc_usb30_sec_mock_utmi_clk,
1238 .clkr.hw.init = &(struct clk_init_data){
1239 .name = "usb30_sec_mock_utmi_clk_src",
1240 .parent_names = gcc_xo_gpll0,
1242 .ops = &clk_rcg2_ops,
1246 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1247 F(75000000, P_GPLL0, 8, 0, 0),
1251 static struct clk_rcg2 usb_hs_system_clk_src = {
1254 .parent_map = gcc_xo_gpll0_map,
1255 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1256 .clkr.hw.init = &(struct clk_init_data){
1257 .name = "usb_hs_system_clk_src",
1258 .parent_names = gcc_xo_gpll0,
1260 .ops = &clk_rcg2_ops,
1264 static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
1265 F(480000000, P_GPLL1, 1, 0, 0),
1269 static const struct parent_map usb_hsic_clk_src_map[] = {
1274 static struct clk_rcg2 usb_hsic_clk_src = {
1277 .parent_map = usb_hsic_clk_src_map,
1278 .freq_tbl = ftbl_gcc_usb_hsic_clk,
1279 .clkr.hw.init = &(struct clk_init_data){
1280 .name = "usb_hsic_clk_src",
1281 .parent_names = (const char *[]){
1286 .ops = &clk_rcg2_ops,
1290 static const struct freq_tbl ftbl_gcc_usb_hsic_ahb_clk_src[] = {
1291 F(60000000, P_GPLL1, 8, 0, 0),
1295 static struct clk_rcg2 usb_hsic_ahb_clk_src = {
1299 .parent_map = usb_hsic_clk_src_map,
1300 .freq_tbl = ftbl_gcc_usb_hsic_ahb_clk_src,
1301 .clkr.hw.init = &(struct clk_init_data){
1302 .name = "usb_hsic_ahb_clk_src",
1303 .parent_names = (const char *[]){
1308 .ops = &clk_rcg2_ops,
1312 static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
1313 F(9600000, P_XO, 2, 0, 0),
1317 static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
1320 .parent_map = gcc_xo_gpll0_map,
1321 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
1322 .clkr.hw.init = &(struct clk_init_data){
1323 .name = "usb_hsic_io_cal_clk_src",
1324 .parent_names = gcc_xo_gpll0,
1326 .ops = &clk_rcg2_ops,
1330 static struct clk_branch gcc_usb_hsic_mock_utmi_clk = {
1333 .enable_reg = 0x1f14,
1334 .enable_mask = BIT(0),
1335 .hw.init = &(struct clk_init_data){
1336 .name = "gcc_usb_hsic_mock_utmi_clk",
1337 .parent_names = (const char *[]){
1338 "usb_hsic_mock_utmi_clk_src",
1341 .flags = CLK_SET_RATE_PARENT,
1342 .ops = &clk_branch2_ops,
1347 static const struct freq_tbl ftbl_gcc_usb_hsic_mock_utmi_clk[] = {
1348 F(60000000, P_GPLL0, 10, 0, 0),
1352 static struct clk_rcg2 usb_hsic_mock_utmi_clk_src = {
1355 .parent_map = gcc_xo_gpll0_map,
1356 .freq_tbl = ftbl_gcc_usb_hsic_mock_utmi_clk,
1357 .clkr.hw.init = &(struct clk_init_data){
1358 .name = "usb_hsic_mock_utmi_clk_src",
1359 .parent_names = gcc_xo_gpll0,
1361 .ops = &clk_rcg2_ops,
1365 static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
1366 F(75000000, P_GPLL0, 8, 0, 0),
1370 static struct clk_rcg2 usb_hsic_system_clk_src = {
1373 .parent_map = gcc_xo_gpll0_map,
1374 .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
1375 .clkr.hw.init = &(struct clk_init_data){
1376 .name = "usb_hsic_system_clk_src",
1377 .parent_names = gcc_xo_gpll0,
1379 .ops = &clk_rcg2_ops,
1383 static struct clk_branch gcc_bam_dma_ahb_clk = {
1385 .halt_check = BRANCH_HALT_VOTED,
1387 .enable_reg = 0x1484,
1388 .enable_mask = BIT(12),
1389 .hw.init = &(struct clk_init_data){
1390 .name = "gcc_bam_dma_ahb_clk",
1391 .parent_names = (const char *[]){
1392 "periph_noc_clk_src",
1395 .ops = &clk_branch2_ops,
1400 static struct clk_branch gcc_blsp1_ahb_clk = {
1402 .halt_check = BRANCH_HALT_VOTED,
1404 .enable_reg = 0x1484,
1405 .enable_mask = BIT(17),
1406 .hw.init = &(struct clk_init_data){
1407 .name = "gcc_blsp1_ahb_clk",
1408 .parent_names = (const char *[]){
1409 "periph_noc_clk_src",
1412 .ops = &clk_branch2_ops,
1417 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1420 .enable_reg = 0x0648,
1421 .enable_mask = BIT(0),
1422 .hw.init = &(struct clk_init_data){
1423 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1424 .parent_names = (const char *[]){
1425 "blsp1_qup1_i2c_apps_clk_src",
1428 .flags = CLK_SET_RATE_PARENT,
1429 .ops = &clk_branch2_ops,
1434 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1437 .enable_reg = 0x0644,
1438 .enable_mask = BIT(0),
1439 .hw.init = &(struct clk_init_data){
1440 .name = "gcc_blsp1_qup1_spi_apps_clk",
1441 .parent_names = (const char *[]){
1442 "blsp1_qup1_spi_apps_clk_src",
1445 .flags = CLK_SET_RATE_PARENT,
1446 .ops = &clk_branch2_ops,
1451 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1454 .enable_reg = 0x06c8,
1455 .enable_mask = BIT(0),
1456 .hw.init = &(struct clk_init_data){
1457 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1458 .parent_names = (const char *[]){
1459 "blsp1_qup2_i2c_apps_clk_src",
1462 .flags = CLK_SET_RATE_PARENT,
1463 .ops = &clk_branch2_ops,
1468 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1471 .enable_reg = 0x06c4,
1472 .enable_mask = BIT(0),
1473 .hw.init = &(struct clk_init_data){
1474 .name = "gcc_blsp1_qup2_spi_apps_clk",
1475 .parent_names = (const char *[]){
1476 "blsp1_qup2_spi_apps_clk_src",
1479 .flags = CLK_SET_RATE_PARENT,
1480 .ops = &clk_branch2_ops,
1485 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1488 .enable_reg = 0x0748,
1489 .enable_mask = BIT(0),
1490 .hw.init = &(struct clk_init_data){
1491 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1492 .parent_names = (const char *[]){
1493 "blsp1_qup3_i2c_apps_clk_src",
1496 .flags = CLK_SET_RATE_PARENT,
1497 .ops = &clk_branch2_ops,
1502 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1505 .enable_reg = 0x0744,
1506 .enable_mask = BIT(0),
1507 .hw.init = &(struct clk_init_data){
1508 .name = "gcc_blsp1_qup3_spi_apps_clk",
1509 .parent_names = (const char *[]){
1510 "blsp1_qup3_spi_apps_clk_src",
1513 .flags = CLK_SET_RATE_PARENT,
1514 .ops = &clk_branch2_ops,
1519 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1522 .enable_reg = 0x07c8,
1523 .enable_mask = BIT(0),
1524 .hw.init = &(struct clk_init_data){
1525 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1526 .parent_names = (const char *[]){
1527 "blsp1_qup4_i2c_apps_clk_src",
1530 .flags = CLK_SET_RATE_PARENT,
1531 .ops = &clk_branch2_ops,
1536 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1539 .enable_reg = 0x07c4,
1540 .enable_mask = BIT(0),
1541 .hw.init = &(struct clk_init_data){
1542 .name = "gcc_blsp1_qup4_spi_apps_clk",
1543 .parent_names = (const char *[]){
1544 "blsp1_qup4_spi_apps_clk_src",
1547 .flags = CLK_SET_RATE_PARENT,
1548 .ops = &clk_branch2_ops,
1553 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1556 .enable_reg = 0x0848,
1557 .enable_mask = BIT(0),
1558 .hw.init = &(struct clk_init_data){
1559 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1560 .parent_names = (const char *[]){
1561 "blsp1_qup5_i2c_apps_clk_src",
1564 .flags = CLK_SET_RATE_PARENT,
1565 .ops = &clk_branch2_ops,
1570 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1573 .enable_reg = 0x0844,
1574 .enable_mask = BIT(0),
1575 .hw.init = &(struct clk_init_data){
1576 .name = "gcc_blsp1_qup5_spi_apps_clk",
1577 .parent_names = (const char *[]){
1578 "blsp1_qup5_spi_apps_clk_src",
1581 .flags = CLK_SET_RATE_PARENT,
1582 .ops = &clk_branch2_ops,
1587 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1590 .enable_reg = 0x08c8,
1591 .enable_mask = BIT(0),
1592 .hw.init = &(struct clk_init_data){
1593 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1594 .parent_names = (const char *[]){
1595 "blsp1_qup6_i2c_apps_clk_src",
1598 .flags = CLK_SET_RATE_PARENT,
1599 .ops = &clk_branch2_ops,
1604 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1607 .enable_reg = 0x08c4,
1608 .enable_mask = BIT(0),
1609 .hw.init = &(struct clk_init_data){
1610 .name = "gcc_blsp1_qup6_spi_apps_clk",
1611 .parent_names = (const char *[]){
1612 "blsp1_qup6_spi_apps_clk_src",
1615 .flags = CLK_SET_RATE_PARENT,
1616 .ops = &clk_branch2_ops,
1621 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1624 .enable_reg = 0x0684,
1625 .enable_mask = BIT(0),
1626 .hw.init = &(struct clk_init_data){
1627 .name = "gcc_blsp1_uart1_apps_clk",
1628 .parent_names = (const char *[]){
1629 "blsp1_uart1_apps_clk_src",
1632 .flags = CLK_SET_RATE_PARENT,
1633 .ops = &clk_branch2_ops,
1638 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1641 .enable_reg = 0x0704,
1642 .enable_mask = BIT(0),
1643 .hw.init = &(struct clk_init_data){
1644 .name = "gcc_blsp1_uart2_apps_clk",
1645 .parent_names = (const char *[]){
1646 "blsp1_uart2_apps_clk_src",
1649 .flags = CLK_SET_RATE_PARENT,
1650 .ops = &clk_branch2_ops,
1655 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1658 .enable_reg = 0x0784,
1659 .enable_mask = BIT(0),
1660 .hw.init = &(struct clk_init_data){
1661 .name = "gcc_blsp1_uart3_apps_clk",
1662 .parent_names = (const char *[]){
1663 "blsp1_uart3_apps_clk_src",
1666 .flags = CLK_SET_RATE_PARENT,
1667 .ops = &clk_branch2_ops,
1672 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1675 .enable_reg = 0x0804,
1676 .enable_mask = BIT(0),
1677 .hw.init = &(struct clk_init_data){
1678 .name = "gcc_blsp1_uart4_apps_clk",
1679 .parent_names = (const char *[]){
1680 "blsp1_uart4_apps_clk_src",
1683 .flags = CLK_SET_RATE_PARENT,
1684 .ops = &clk_branch2_ops,
1689 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1692 .enable_reg = 0x0884,
1693 .enable_mask = BIT(0),
1694 .hw.init = &(struct clk_init_data){
1695 .name = "gcc_blsp1_uart5_apps_clk",
1696 .parent_names = (const char *[]){
1697 "blsp1_uart5_apps_clk_src",
1700 .flags = CLK_SET_RATE_PARENT,
1701 .ops = &clk_branch2_ops,
1706 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1709 .enable_reg = 0x0904,
1710 .enable_mask = BIT(0),
1711 .hw.init = &(struct clk_init_data){
1712 .name = "gcc_blsp1_uart6_apps_clk",
1713 .parent_names = (const char *[]){
1714 "blsp1_uart6_apps_clk_src",
1717 .flags = CLK_SET_RATE_PARENT,
1718 .ops = &clk_branch2_ops,
1723 static struct clk_branch gcc_blsp2_ahb_clk = {
1725 .halt_check = BRANCH_HALT_VOTED,
1727 .enable_reg = 0x1484,
1728 .enable_mask = BIT(15),
1729 .hw.init = &(struct clk_init_data){
1730 .name = "gcc_blsp2_ahb_clk",
1731 .parent_names = (const char *[]){
1732 "periph_noc_clk_src",
1735 .ops = &clk_branch2_ops,
1740 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1743 .enable_reg = 0x0988,
1744 .enable_mask = BIT(0),
1745 .hw.init = &(struct clk_init_data){
1746 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1747 .parent_names = (const char *[]){
1748 "blsp2_qup1_i2c_apps_clk_src",
1751 .flags = CLK_SET_RATE_PARENT,
1752 .ops = &clk_branch2_ops,
1757 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1760 .enable_reg = 0x0984,
1761 .enable_mask = BIT(0),
1762 .hw.init = &(struct clk_init_data){
1763 .name = "gcc_blsp2_qup1_spi_apps_clk",
1764 .parent_names = (const char *[]){
1765 "blsp2_qup1_spi_apps_clk_src",
1768 .flags = CLK_SET_RATE_PARENT,
1769 .ops = &clk_branch2_ops,
1774 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1777 .enable_reg = 0x0a08,
1778 .enable_mask = BIT(0),
1779 .hw.init = &(struct clk_init_data){
1780 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1781 .parent_names = (const char *[]){
1782 "blsp2_qup2_i2c_apps_clk_src",
1785 .flags = CLK_SET_RATE_PARENT,
1786 .ops = &clk_branch2_ops,
1791 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1794 .enable_reg = 0x0a04,
1795 .enable_mask = BIT(0),
1796 .hw.init = &(struct clk_init_data){
1797 .name = "gcc_blsp2_qup2_spi_apps_clk",
1798 .parent_names = (const char *[]){
1799 "blsp2_qup2_spi_apps_clk_src",
1802 .flags = CLK_SET_RATE_PARENT,
1803 .ops = &clk_branch2_ops,
1808 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1811 .enable_reg = 0x0a88,
1812 .enable_mask = BIT(0),
1813 .hw.init = &(struct clk_init_data){
1814 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1815 .parent_names = (const char *[]){
1816 "blsp2_qup3_i2c_apps_clk_src",
1819 .flags = CLK_SET_RATE_PARENT,
1820 .ops = &clk_branch2_ops,
1825 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1828 .enable_reg = 0x0a84,
1829 .enable_mask = BIT(0),
1830 .hw.init = &(struct clk_init_data){
1831 .name = "gcc_blsp2_qup3_spi_apps_clk",
1832 .parent_names = (const char *[]){
1833 "blsp2_qup3_spi_apps_clk_src",
1836 .flags = CLK_SET_RATE_PARENT,
1837 .ops = &clk_branch2_ops,
1842 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1845 .enable_reg = 0x0b08,
1846 .enable_mask = BIT(0),
1847 .hw.init = &(struct clk_init_data){
1848 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1849 .parent_names = (const char *[]){
1850 "blsp2_qup4_i2c_apps_clk_src",
1853 .flags = CLK_SET_RATE_PARENT,
1854 .ops = &clk_branch2_ops,
1859 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1862 .enable_reg = 0x0b04,
1863 .enable_mask = BIT(0),
1864 .hw.init = &(struct clk_init_data){
1865 .name = "gcc_blsp2_qup4_spi_apps_clk",
1866 .parent_names = (const char *[]){
1867 "blsp2_qup4_spi_apps_clk_src",
1870 .flags = CLK_SET_RATE_PARENT,
1871 .ops = &clk_branch2_ops,
1876 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1879 .enable_reg = 0x0b88,
1880 .enable_mask = BIT(0),
1881 .hw.init = &(struct clk_init_data){
1882 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1883 .parent_names = (const char *[]){
1884 "blsp2_qup5_i2c_apps_clk_src",
1887 .flags = CLK_SET_RATE_PARENT,
1888 .ops = &clk_branch2_ops,
1893 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1896 .enable_reg = 0x0b84,
1897 .enable_mask = BIT(0),
1898 .hw.init = &(struct clk_init_data){
1899 .name = "gcc_blsp2_qup5_spi_apps_clk",
1900 .parent_names = (const char *[]){
1901 "blsp2_qup5_spi_apps_clk_src",
1904 .flags = CLK_SET_RATE_PARENT,
1905 .ops = &clk_branch2_ops,
1910 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1913 .enable_reg = 0x0c08,
1914 .enable_mask = BIT(0),
1915 .hw.init = &(struct clk_init_data){
1916 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1917 .parent_names = (const char *[]){
1918 "blsp2_qup6_i2c_apps_clk_src",
1921 .flags = CLK_SET_RATE_PARENT,
1922 .ops = &clk_branch2_ops,
1927 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1930 .enable_reg = 0x0c04,
1931 .enable_mask = BIT(0),
1932 .hw.init = &(struct clk_init_data){
1933 .name = "gcc_blsp2_qup6_spi_apps_clk",
1934 .parent_names = (const char *[]){
1935 "blsp2_qup6_spi_apps_clk_src",
1938 .flags = CLK_SET_RATE_PARENT,
1939 .ops = &clk_branch2_ops,
1944 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1947 .enable_reg = 0x09c4,
1948 .enable_mask = BIT(0),
1949 .hw.init = &(struct clk_init_data){
1950 .name = "gcc_blsp2_uart1_apps_clk",
1951 .parent_names = (const char *[]){
1952 "blsp2_uart1_apps_clk_src",
1955 .flags = CLK_SET_RATE_PARENT,
1956 .ops = &clk_branch2_ops,
1961 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1964 .enable_reg = 0x0a44,
1965 .enable_mask = BIT(0),
1966 .hw.init = &(struct clk_init_data){
1967 .name = "gcc_blsp2_uart2_apps_clk",
1968 .parent_names = (const char *[]){
1969 "blsp2_uart2_apps_clk_src",
1972 .flags = CLK_SET_RATE_PARENT,
1973 .ops = &clk_branch2_ops,
1978 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1981 .enable_reg = 0x0ac4,
1982 .enable_mask = BIT(0),
1983 .hw.init = &(struct clk_init_data){
1984 .name = "gcc_blsp2_uart3_apps_clk",
1985 .parent_names = (const char *[]){
1986 "blsp2_uart3_apps_clk_src",
1989 .flags = CLK_SET_RATE_PARENT,
1990 .ops = &clk_branch2_ops,
1995 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1998 .enable_reg = 0x0b44,
1999 .enable_mask = BIT(0),
2000 .hw.init = &(struct clk_init_data){
2001 .name = "gcc_blsp2_uart4_apps_clk",
2002 .parent_names = (const char *[]){
2003 "blsp2_uart4_apps_clk_src",
2006 .flags = CLK_SET_RATE_PARENT,
2007 .ops = &clk_branch2_ops,
2012 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
2015 .enable_reg = 0x0bc4,
2016 .enable_mask = BIT(0),
2017 .hw.init = &(struct clk_init_data){
2018 .name = "gcc_blsp2_uart5_apps_clk",
2019 .parent_names = (const char *[]){
2020 "blsp2_uart5_apps_clk_src",
2023 .flags = CLK_SET_RATE_PARENT,
2024 .ops = &clk_branch2_ops,
2029 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
2032 .enable_reg = 0x0c44,
2033 .enable_mask = BIT(0),
2034 .hw.init = &(struct clk_init_data){
2035 .name = "gcc_blsp2_uart6_apps_clk",
2036 .parent_names = (const char *[]){
2037 "blsp2_uart6_apps_clk_src",
2040 .flags = CLK_SET_RATE_PARENT,
2041 .ops = &clk_branch2_ops,
2046 static struct clk_branch gcc_boot_rom_ahb_clk = {
2048 .halt_check = BRANCH_HALT_VOTED,
2050 .enable_reg = 0x1484,
2051 .enable_mask = BIT(10),
2052 .hw.init = &(struct clk_init_data){
2053 .name = "gcc_boot_rom_ahb_clk",
2054 .parent_names = (const char *[]){
2055 "config_noc_clk_src",
2058 .ops = &clk_branch2_ops,
2063 static struct clk_branch gcc_ce1_ahb_clk = {
2065 .halt_check = BRANCH_HALT_VOTED,
2067 .enable_reg = 0x1484,
2068 .enable_mask = BIT(3),
2069 .hw.init = &(struct clk_init_data){
2070 .name = "gcc_ce1_ahb_clk",
2071 .parent_names = (const char *[]){
2072 "config_noc_clk_src",
2075 .ops = &clk_branch2_ops,
2080 static struct clk_branch gcc_ce1_axi_clk = {
2082 .halt_check = BRANCH_HALT_VOTED,
2084 .enable_reg = 0x1484,
2085 .enable_mask = BIT(4),
2086 .hw.init = &(struct clk_init_data){
2087 .name = "gcc_ce1_axi_clk",
2088 .parent_names = (const char *[]){
2089 "system_noc_clk_src",
2092 .ops = &clk_branch2_ops,
2097 static struct clk_branch gcc_ce1_clk = {
2099 .halt_check = BRANCH_HALT_VOTED,
2101 .enable_reg = 0x1484,
2102 .enable_mask = BIT(5),
2103 .hw.init = &(struct clk_init_data){
2104 .name = "gcc_ce1_clk",
2105 .parent_names = (const char *[]){
2109 .flags = CLK_SET_RATE_PARENT,
2110 .ops = &clk_branch2_ops,
2115 static struct clk_branch gcc_ce2_ahb_clk = {
2117 .halt_check = BRANCH_HALT_VOTED,
2119 .enable_reg = 0x1484,
2120 .enable_mask = BIT(0),
2121 .hw.init = &(struct clk_init_data){
2122 .name = "gcc_ce2_ahb_clk",
2123 .parent_names = (const char *[]){
2124 "config_noc_clk_src",
2127 .ops = &clk_branch2_ops,
2132 static struct clk_branch gcc_ce2_axi_clk = {
2134 .halt_check = BRANCH_HALT_VOTED,
2136 .enable_reg = 0x1484,
2137 .enable_mask = BIT(1),
2138 .hw.init = &(struct clk_init_data){
2139 .name = "gcc_ce2_axi_clk",
2140 .parent_names = (const char *[]){
2141 "system_noc_clk_src",
2144 .ops = &clk_branch2_ops,
2149 static struct clk_branch gcc_ce2_clk = {
2151 .halt_check = BRANCH_HALT_VOTED,
2153 .enable_reg = 0x1484,
2154 .enable_mask = BIT(2),
2155 .hw.init = &(struct clk_init_data){
2156 .name = "gcc_ce2_clk",
2157 .parent_names = (const char *[]){
2161 .flags = CLK_SET_RATE_PARENT,
2162 .ops = &clk_branch2_ops,
2167 static struct clk_branch gcc_ce3_ahb_clk = {
2169 .halt_check = BRANCH_HALT_VOTED,
2171 .enable_reg = 0x1d0c,
2172 .enable_mask = BIT(0),
2173 .hw.init = &(struct clk_init_data){
2174 .name = "gcc_ce3_ahb_clk",
2175 .parent_names = (const char *[]){
2176 "config_noc_clk_src",
2179 .ops = &clk_branch2_ops,
2184 static struct clk_branch gcc_ce3_axi_clk = {
2186 .halt_check = BRANCH_HALT_VOTED,
2188 .enable_reg = 0x1d08,
2189 .enable_mask = BIT(0),
2190 .hw.init = &(struct clk_init_data){
2191 .name = "gcc_ce3_axi_clk",
2192 .parent_names = (const char *[]){
2193 "system_noc_clk_src",
2196 .ops = &clk_branch2_ops,
2201 static struct clk_branch gcc_ce3_clk = {
2203 .halt_check = BRANCH_HALT_VOTED,
2205 .enable_reg = 0x1d04,
2206 .enable_mask = BIT(0),
2207 .hw.init = &(struct clk_init_data){
2208 .name = "gcc_ce3_clk",
2209 .parent_names = (const char *[]){
2213 .flags = CLK_SET_RATE_PARENT,
2214 .ops = &clk_branch2_ops,
2219 static struct clk_branch gcc_gp1_clk = {
2222 .enable_reg = 0x1900,
2223 .enable_mask = BIT(0),
2224 .hw.init = &(struct clk_init_data){
2225 .name = "gcc_gp1_clk",
2226 .parent_names = (const char *[]){
2230 .flags = CLK_SET_RATE_PARENT,
2231 .ops = &clk_branch2_ops,
2236 static struct clk_branch gcc_gp2_clk = {
2239 .enable_reg = 0x1940,
2240 .enable_mask = BIT(0),
2241 .hw.init = &(struct clk_init_data){
2242 .name = "gcc_gp2_clk",
2243 .parent_names = (const char *[]){
2247 .flags = CLK_SET_RATE_PARENT,
2248 .ops = &clk_branch2_ops,
2253 static struct clk_branch gcc_gp3_clk = {
2256 .enable_reg = 0x1980,
2257 .enable_mask = BIT(0),
2258 .hw.init = &(struct clk_init_data){
2259 .name = "gcc_gp3_clk",
2260 .parent_names = (const char *[]){
2264 .flags = CLK_SET_RATE_PARENT,
2265 .ops = &clk_branch2_ops,
2270 static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
2273 .enable_reg = 0x0248,
2274 .enable_mask = BIT(0),
2275 .hw.init = &(struct clk_init_data){
2276 .name = "gcc_ocmem_noc_cfg_ahb_clk",
2277 .parent_names = (const char *[]){
2278 "config_noc_clk_src",
2281 .ops = &clk_branch2_ops,
2286 static struct clk_branch gcc_pcie_0_aux_clk = {
2289 .enable_reg = 0x1b10,
2290 .enable_mask = BIT(0),
2291 .hw.init = &(struct clk_init_data){
2292 .name = "gcc_pcie_0_aux_clk",
2293 .parent_names = (const char *[]){
2294 "pcie_0_aux_clk_src",
2297 .flags = CLK_SET_RATE_PARENT,
2298 .ops = &clk_branch2_ops,
2303 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2306 .enable_reg = 0x1b0c,
2307 .enable_mask = BIT(0),
2308 .hw.init = &(struct clk_init_data){
2309 .name = "gcc_pcie_0_cfg_ahb_clk",
2310 .parent_names = (const char *[]){
2311 "config_noc_clk_src",
2314 .flags = CLK_SET_RATE_PARENT,
2315 .ops = &clk_branch2_ops,
2320 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2323 .enable_reg = 0x1b08,
2324 .enable_mask = BIT(0),
2325 .hw.init = &(struct clk_init_data){
2326 .name = "gcc_pcie_0_mstr_axi_clk",
2327 .parent_names = (const char *[]){
2328 "config_noc_clk_src",
2331 .flags = CLK_SET_RATE_PARENT,
2332 .ops = &clk_branch2_ops,
2337 static struct clk_branch gcc_pcie_0_pipe_clk = {
2340 .enable_reg = 0x1b14,
2341 .enable_mask = BIT(0),
2342 .hw.init = &(struct clk_init_data){
2343 .name = "gcc_pcie_0_pipe_clk",
2344 .parent_names = (const char *[]){
2345 "pcie_0_pipe_clk_src",
2348 .flags = CLK_SET_RATE_PARENT,
2349 .ops = &clk_branch2_ops,
2354 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2357 .enable_reg = 0x1b04,
2358 .enable_mask = BIT(0),
2359 .hw.init = &(struct clk_init_data){
2360 .name = "gcc_pcie_0_slv_axi_clk",
2361 .parent_names = (const char *[]){
2362 "config_noc_clk_src",
2365 .flags = CLK_SET_RATE_PARENT,
2366 .ops = &clk_branch2_ops,
2371 static struct clk_branch gcc_pcie_1_aux_clk = {
2374 .enable_reg = 0x1b90,
2375 .enable_mask = BIT(0),
2376 .hw.init = &(struct clk_init_data){
2377 .name = "gcc_pcie_1_aux_clk",
2378 .parent_names = (const char *[]){
2379 "pcie_1_aux_clk_src",
2382 .flags = CLK_SET_RATE_PARENT,
2383 .ops = &clk_branch2_ops,
2388 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2391 .enable_reg = 0x1b8c,
2392 .enable_mask = BIT(0),
2393 .hw.init = &(struct clk_init_data){
2394 .name = "gcc_pcie_1_cfg_ahb_clk",
2395 .parent_names = (const char *[]){
2396 "config_noc_clk_src",
2399 .flags = CLK_SET_RATE_PARENT,
2400 .ops = &clk_branch2_ops,
2405 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2408 .enable_reg = 0x1b88,
2409 .enable_mask = BIT(0),
2410 .hw.init = &(struct clk_init_data){
2411 .name = "gcc_pcie_1_mstr_axi_clk",
2412 .parent_names = (const char *[]){
2413 "config_noc_clk_src",
2416 .flags = CLK_SET_RATE_PARENT,
2417 .ops = &clk_branch2_ops,
2422 static struct clk_branch gcc_pcie_1_pipe_clk = {
2425 .enable_reg = 0x1b94,
2426 .enable_mask = BIT(0),
2427 .hw.init = &(struct clk_init_data){
2428 .name = "gcc_pcie_1_pipe_clk",
2429 .parent_names = (const char *[]){
2430 "pcie_1_pipe_clk_src",
2433 .flags = CLK_SET_RATE_PARENT,
2434 .ops = &clk_branch2_ops,
2439 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2442 .enable_reg = 0x1b84,
2443 .enable_mask = BIT(0),
2444 .hw.init = &(struct clk_init_data){
2445 .name = "gcc_pcie_1_slv_axi_clk",
2446 .parent_names = (const char *[]){
2447 "config_noc_clk_src",
2450 .flags = CLK_SET_RATE_PARENT,
2451 .ops = &clk_branch2_ops,
2456 static struct clk_branch gcc_pdm2_clk = {
2459 .enable_reg = 0x0ccc,
2460 .enable_mask = BIT(0),
2461 .hw.init = &(struct clk_init_data){
2462 .name = "gcc_pdm2_clk",
2463 .parent_names = (const char *[]){
2467 .flags = CLK_SET_RATE_PARENT,
2468 .ops = &clk_branch2_ops,
2473 static struct clk_branch gcc_pdm_ahb_clk = {
2476 .enable_reg = 0x0cc4,
2477 .enable_mask = BIT(0),
2478 .hw.init = &(struct clk_init_data){
2479 .name = "gcc_pdm_ahb_clk",
2480 .parent_names = (const char *[]){
2481 "periph_noc_clk_src",
2484 .ops = &clk_branch2_ops,
2489 static struct clk_branch gcc_periph_noc_usb_hsic_ahb_clk = {
2492 .enable_reg = 0x01a4,
2493 .enable_mask = BIT(0),
2494 .hw.init = &(struct clk_init_data){
2495 .name = "gcc_periph_noc_usb_hsic_ahb_clk",
2496 .parent_names = (const char *[]){
2497 "usb_hsic_ahb_clk_src",
2500 .flags = CLK_SET_RATE_PARENT,
2501 .ops = &clk_branch2_ops,
2506 static struct clk_branch gcc_prng_ahb_clk = {
2508 .halt_check = BRANCH_HALT_VOTED,
2510 .enable_reg = 0x1484,
2511 .enable_mask = BIT(13),
2512 .hw.init = &(struct clk_init_data){
2513 .name = "gcc_prng_ahb_clk",
2514 .parent_names = (const char *[]){
2515 "periph_noc_clk_src",
2518 .ops = &clk_branch2_ops,
2523 static struct clk_branch gcc_sata_asic0_clk = {
2526 .enable_reg = 0x1c54,
2527 .enable_mask = BIT(0),
2528 .hw.init = &(struct clk_init_data){
2529 .name = "gcc_sata_asic0_clk",
2530 .parent_names = (const char *[]){
2531 "sata_asic0_clk_src",
2534 .flags = CLK_SET_RATE_PARENT,
2535 .ops = &clk_branch2_ops,
2540 static struct clk_branch gcc_sata_axi_clk = {
2543 .enable_reg = 0x1c44,
2544 .enable_mask = BIT(0),
2545 .hw.init = &(struct clk_init_data){
2546 .name = "gcc_sata_axi_clk",
2547 .parent_names = (const char *[]){
2548 "config_noc_clk_src",
2551 .flags = CLK_SET_RATE_PARENT,
2552 .ops = &clk_branch2_ops,
2557 static struct clk_branch gcc_sata_cfg_ahb_clk = {
2560 .enable_reg = 0x1c48,
2561 .enable_mask = BIT(0),
2562 .hw.init = &(struct clk_init_data){
2563 .name = "gcc_sata_cfg_ahb_clk",
2564 .parent_names = (const char *[]){
2565 "config_noc_clk_src",
2568 .flags = CLK_SET_RATE_PARENT,
2569 .ops = &clk_branch2_ops,
2574 static struct clk_branch gcc_sata_pmalive_clk = {
2577 .enable_reg = 0x1c50,
2578 .enable_mask = BIT(0),
2579 .hw.init = &(struct clk_init_data){
2580 .name = "gcc_sata_pmalive_clk",
2581 .parent_names = (const char *[]){
2582 "sata_pmalive_clk_src",
2585 .flags = CLK_SET_RATE_PARENT,
2586 .ops = &clk_branch2_ops,
2591 static struct clk_branch gcc_sata_rx_clk = {
2594 .enable_reg = 0x1c58,
2595 .enable_mask = BIT(0),
2596 .hw.init = &(struct clk_init_data){
2597 .name = "gcc_sata_rx_clk",
2598 .parent_names = (const char *[]){
2602 .flags = CLK_SET_RATE_PARENT,
2603 .ops = &clk_branch2_ops,
2608 static struct clk_branch gcc_sata_rx_oob_clk = {
2611 .enable_reg = 0x1c4c,
2612 .enable_mask = BIT(0),
2613 .hw.init = &(struct clk_init_data){
2614 .name = "gcc_sata_rx_oob_clk",
2615 .parent_names = (const char *[]){
2616 "sata_rx_oob_clk_src",
2619 .flags = CLK_SET_RATE_PARENT,
2620 .ops = &clk_branch2_ops,
2625 static struct clk_branch gcc_sdcc1_ahb_clk = {
2628 .enable_reg = 0x04c8,
2629 .enable_mask = BIT(0),
2630 .hw.init = &(struct clk_init_data){
2631 .name = "gcc_sdcc1_ahb_clk",
2632 .parent_names = (const char *[]){
2633 "periph_noc_clk_src",
2636 .ops = &clk_branch2_ops,
2641 static struct clk_branch gcc_sdcc1_apps_clk = {
2644 .enable_reg = 0x04c4,
2645 .enable_mask = BIT(0),
2646 .hw.init = &(struct clk_init_data){
2647 .name = "gcc_sdcc1_apps_clk",
2648 .parent_names = (const char *[]){
2649 "sdcc1_apps_clk_src",
2652 .flags = CLK_SET_RATE_PARENT,
2653 .ops = &clk_branch2_ops,
2658 static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
2661 .enable_reg = 0x04e8,
2662 .enable_mask = BIT(0),
2663 .hw.init = &(struct clk_init_data){
2664 .name = "gcc_sdcc1_cdccal_ff_clk",
2665 .parent_names = (const char *[]){
2669 .ops = &clk_branch2_ops,
2674 static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
2677 .enable_reg = 0x04e4,
2678 .enable_mask = BIT(0),
2679 .hw.init = &(struct clk_init_data){
2680 .name = "gcc_sdcc1_cdccal_sleep_clk",
2681 .parent_names = (const char *[]){
2685 .ops = &clk_branch2_ops,
2690 static struct clk_branch gcc_sdcc2_ahb_clk = {
2693 .enable_reg = 0x0508,
2694 .enable_mask = BIT(0),
2695 .hw.init = &(struct clk_init_data){
2696 .name = "gcc_sdcc2_ahb_clk",
2697 .parent_names = (const char *[]){
2698 "periph_noc_clk_src",
2701 .ops = &clk_branch2_ops,
2706 static struct clk_branch gcc_sdcc2_apps_clk = {
2709 .enable_reg = 0x0504,
2710 .enable_mask = BIT(0),
2711 .hw.init = &(struct clk_init_data){
2712 .name = "gcc_sdcc2_apps_clk",
2713 .parent_names = (const char *[]){
2714 "sdcc2_apps_clk_src",
2717 .flags = CLK_SET_RATE_PARENT,
2718 .ops = &clk_branch2_ops,
2723 static struct clk_branch gcc_sdcc3_ahb_clk = {
2726 .enable_reg = 0x0548,
2727 .enable_mask = BIT(0),
2728 .hw.init = &(struct clk_init_data){
2729 .name = "gcc_sdcc3_ahb_clk",
2730 .parent_names = (const char *[]){
2731 "periph_noc_clk_src",
2734 .ops = &clk_branch2_ops,
2739 static struct clk_branch gcc_sdcc3_apps_clk = {
2742 .enable_reg = 0x0544,
2743 .enable_mask = BIT(0),
2744 .hw.init = &(struct clk_init_data){
2745 .name = "gcc_sdcc3_apps_clk",
2746 .parent_names = (const char *[]){
2747 "sdcc3_apps_clk_src",
2750 .flags = CLK_SET_RATE_PARENT,
2751 .ops = &clk_branch2_ops,
2756 static struct clk_branch gcc_sdcc4_ahb_clk = {
2759 .enable_reg = 0x0588,
2760 .enable_mask = BIT(0),
2761 .hw.init = &(struct clk_init_data){
2762 .name = "gcc_sdcc4_ahb_clk",
2763 .parent_names = (const char *[]){
2764 "periph_noc_clk_src",
2767 .ops = &clk_branch2_ops,
2772 static struct clk_branch gcc_sdcc4_apps_clk = {
2775 .enable_reg = 0x0584,
2776 .enable_mask = BIT(0),
2777 .hw.init = &(struct clk_init_data){
2778 .name = "gcc_sdcc4_apps_clk",
2779 .parent_names = (const char *[]){
2780 "sdcc4_apps_clk_src",
2783 .flags = CLK_SET_RATE_PARENT,
2784 .ops = &clk_branch2_ops,
2789 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
2792 .enable_reg = 0x013c,
2793 .enable_mask = BIT(0),
2794 .hw.init = &(struct clk_init_data){
2795 .name = "gcc_sys_noc_ufs_axi_clk",
2796 .parent_names = (const char *[]){
2800 .flags = CLK_SET_RATE_PARENT,
2801 .ops = &clk_branch2_ops,
2806 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2809 .enable_reg = 0x0108,
2810 .enable_mask = BIT(0),
2811 .hw.init = &(struct clk_init_data){
2812 .name = "gcc_sys_noc_usb3_axi_clk",
2813 .parent_names = (const char *[]){
2814 "usb30_master_clk_src",
2817 .flags = CLK_SET_RATE_PARENT,
2818 .ops = &clk_branch2_ops,
2823 static struct clk_branch gcc_sys_noc_usb3_sec_axi_clk = {
2826 .enable_reg = 0x0138,
2827 .enable_mask = BIT(0),
2828 .hw.init = &(struct clk_init_data){
2829 .name = "gcc_sys_noc_usb3_sec_axi_clk",
2830 .parent_names = (const char *[]){
2831 "usb30_sec_master_clk_src",
2834 .flags = CLK_SET_RATE_PARENT,
2835 .ops = &clk_branch2_ops,
2840 static struct clk_branch gcc_tsif_ahb_clk = {
2843 .enable_reg = 0x0d84,
2844 .enable_mask = BIT(0),
2845 .hw.init = &(struct clk_init_data){
2846 .name = "gcc_tsif_ahb_clk",
2847 .parent_names = (const char *[]){
2848 "periph_noc_clk_src",
2851 .ops = &clk_branch2_ops,
2856 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2859 .enable_reg = 0x0d8c,
2860 .enable_mask = BIT(0),
2861 .hw.init = &(struct clk_init_data){
2862 .name = "gcc_tsif_inactivity_timers_clk",
2863 .parent_names = (const char *[]){
2867 .flags = CLK_SET_RATE_PARENT,
2868 .ops = &clk_branch2_ops,
2873 static struct clk_branch gcc_tsif_ref_clk = {
2876 .enable_reg = 0x0d88,
2877 .enable_mask = BIT(0),
2878 .hw.init = &(struct clk_init_data){
2879 .name = "gcc_tsif_ref_clk",
2880 .parent_names = (const char *[]){
2884 .flags = CLK_SET_RATE_PARENT,
2885 .ops = &clk_branch2_ops,
2890 static struct clk_branch gcc_ufs_ahb_clk = {
2893 .enable_reg = 0x1d48,
2894 .enable_mask = BIT(0),
2895 .hw.init = &(struct clk_init_data){
2896 .name = "gcc_ufs_ahb_clk",
2897 .parent_names = (const char *[]){
2898 "config_noc_clk_src",
2901 .flags = CLK_SET_RATE_PARENT,
2902 .ops = &clk_branch2_ops,
2907 static struct clk_branch gcc_ufs_axi_clk = {
2910 .enable_reg = 0x1d44,
2911 .enable_mask = BIT(0),
2912 .hw.init = &(struct clk_init_data){
2913 .name = "gcc_ufs_axi_clk",
2914 .parent_names = (const char *[]){
2918 .flags = CLK_SET_RATE_PARENT,
2919 .ops = &clk_branch2_ops,
2924 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2927 .enable_reg = 0x1d50,
2928 .enable_mask = BIT(0),
2929 .hw.init = &(struct clk_init_data){
2930 .name = "gcc_ufs_rx_cfg_clk",
2931 .parent_names = (const char *[]){
2935 .flags = CLK_SET_RATE_PARENT,
2936 .ops = &clk_branch2_ops,
2941 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2944 .enable_reg = 0x1d5c,
2945 .enable_mask = BIT(0),
2946 .hw.init = &(struct clk_init_data){
2947 .name = "gcc_ufs_rx_symbol_0_clk",
2948 .parent_names = (const char *[]){
2949 "ufs_rx_symbol_0_clk_src",
2952 .flags = CLK_SET_RATE_PARENT,
2953 .ops = &clk_branch2_ops,
2958 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2961 .enable_reg = 0x1d60,
2962 .enable_mask = BIT(0),
2963 .hw.init = &(struct clk_init_data){
2964 .name = "gcc_ufs_rx_symbol_1_clk",
2965 .parent_names = (const char *[]){
2966 "ufs_rx_symbol_1_clk_src",
2969 .flags = CLK_SET_RATE_PARENT,
2970 .ops = &clk_branch2_ops,
2975 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2978 .enable_reg = 0x1d4c,
2979 .enable_mask = BIT(0),
2980 .hw.init = &(struct clk_init_data){
2981 .name = "gcc_ufs_tx_cfg_clk",
2982 .parent_names = (const char *[]){
2986 .flags = CLK_SET_RATE_PARENT,
2987 .ops = &clk_branch2_ops,
2992 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2995 .enable_reg = 0x1d54,
2996 .enable_mask = BIT(0),
2997 .hw.init = &(struct clk_init_data){
2998 .name = "gcc_ufs_tx_symbol_0_clk",
2999 .parent_names = (const char *[]){
3000 "ufs_tx_symbol_0_clk_src",
3003 .flags = CLK_SET_RATE_PARENT,
3004 .ops = &clk_branch2_ops,
3009 static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
3012 .enable_reg = 0x1d58,
3013 .enable_mask = BIT(0),
3014 .hw.init = &(struct clk_init_data){
3015 .name = "gcc_ufs_tx_symbol_1_clk",
3016 .parent_names = (const char *[]){
3017 "ufs_tx_symbol_1_clk_src",
3020 .flags = CLK_SET_RATE_PARENT,
3021 .ops = &clk_branch2_ops,
3026 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
3029 .enable_reg = 0x04ac,
3030 .enable_mask = BIT(0),
3031 .hw.init = &(struct clk_init_data){
3032 .name = "gcc_usb2a_phy_sleep_clk",
3033 .parent_names = (const char *[]){
3037 .ops = &clk_branch2_ops,
3042 static struct clk_branch gcc_usb2b_phy_sleep_clk = {
3045 .enable_reg = 0x04b4,
3046 .enable_mask = BIT(0),
3047 .hw.init = &(struct clk_init_data){
3048 .name = "gcc_usb2b_phy_sleep_clk",
3049 .parent_names = (const char *[]){
3053 .ops = &clk_branch2_ops,
3058 static struct clk_branch gcc_usb30_master_clk = {
3061 .enable_reg = 0x03c8,
3062 .enable_mask = BIT(0),
3063 .hw.init = &(struct clk_init_data){
3064 .name = "gcc_usb30_master_clk",
3065 .parent_names = (const char *[]){
3066 "usb30_master_clk_src",
3069 .flags = CLK_SET_RATE_PARENT,
3070 .ops = &clk_branch2_ops,
3075 static struct clk_branch gcc_usb30_sec_master_clk = {
3078 .enable_reg = 0x1bc8,
3079 .enable_mask = BIT(0),
3080 .hw.init = &(struct clk_init_data){
3081 .name = "gcc_usb30_sec_master_clk",
3082 .parent_names = (const char *[]){
3083 "usb30_sec_master_clk_src",
3086 .flags = CLK_SET_RATE_PARENT,
3087 .ops = &clk_branch2_ops,
3092 static struct clk_branch gcc_usb30_mock_utmi_clk = {
3095 .enable_reg = 0x03d0,
3096 .enable_mask = BIT(0),
3097 .hw.init = &(struct clk_init_data){
3098 .name = "gcc_usb30_mock_utmi_clk",
3099 .parent_names = (const char *[]){
3100 "usb30_mock_utmi_clk_src",
3103 .flags = CLK_SET_RATE_PARENT,
3104 .ops = &clk_branch2_ops,
3109 static struct clk_branch gcc_usb30_sleep_clk = {
3112 .enable_reg = 0x03cc,
3113 .enable_mask = BIT(0),
3114 .hw.init = &(struct clk_init_data){
3115 .name = "gcc_usb30_sleep_clk",
3116 .parent_names = (const char *[]){
3120 .ops = &clk_branch2_ops,
3125 static struct clk_branch gcc_usb_hs_ahb_clk = {
3128 .enable_reg = 0x0488,
3129 .enable_mask = BIT(0),
3130 .hw.init = &(struct clk_init_data){
3131 .name = "gcc_usb_hs_ahb_clk",
3132 .parent_names = (const char *[]){
3133 "periph_noc_clk_src",
3136 .ops = &clk_branch2_ops,
3141 static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
3144 .enable_reg = 0x048c,
3145 .enable_mask = BIT(0),
3146 .hw.init = &(struct clk_init_data){
3147 .name = "gcc_usb_hs_inactivity_timers_clk",
3148 .parent_names = (const char *[]){
3152 .flags = CLK_SET_RATE_PARENT,
3153 .ops = &clk_branch2_ops,
3158 static struct clk_branch gcc_usb_hs_system_clk = {
3161 .enable_reg = 0x0484,
3162 .enable_mask = BIT(0),
3163 .hw.init = &(struct clk_init_data){
3164 .name = "gcc_usb_hs_system_clk",
3165 .parent_names = (const char *[]){
3166 "usb_hs_system_clk_src",
3169 .flags = CLK_SET_RATE_PARENT,
3170 .ops = &clk_branch2_ops,
3175 static struct clk_branch gcc_usb_hsic_ahb_clk = {
3178 .enable_reg = 0x0408,
3179 .enable_mask = BIT(0),
3180 .hw.init = &(struct clk_init_data){
3181 .name = "gcc_usb_hsic_ahb_clk",
3182 .parent_names = (const char *[]){
3183 "periph_noc_clk_src",
3186 .ops = &clk_branch2_ops,
3191 static struct clk_branch gcc_usb_hsic_clk = {
3194 .enable_reg = 0x0410,
3195 .enable_mask = BIT(0),
3196 .hw.init = &(struct clk_init_data){
3197 .name = "gcc_usb_hsic_clk",
3198 .parent_names = (const char *[]){
3202 .flags = CLK_SET_RATE_PARENT,
3203 .ops = &clk_branch2_ops,
3208 static struct clk_branch gcc_usb_hsic_io_cal_clk = {
3211 .enable_reg = 0x0414,
3212 .enable_mask = BIT(0),
3213 .hw.init = &(struct clk_init_data){
3214 .name = "gcc_usb_hsic_io_cal_clk",
3215 .parent_names = (const char *[]){
3216 "usb_hsic_io_cal_clk_src",
3219 .flags = CLK_SET_RATE_PARENT,
3220 .ops = &clk_branch2_ops,
3225 static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
3228 .enable_reg = 0x0418,
3229 .enable_mask = BIT(0),
3230 .hw.init = &(struct clk_init_data){
3231 .name = "gcc_usb_hsic_io_cal_sleep_clk",
3232 .parent_names = (const char *[]){
3236 .ops = &clk_branch2_ops,
3241 static struct clk_branch gcc_usb_hsic_system_clk = {
3244 .enable_reg = 0x040c,
3245 .enable_mask = BIT(0),
3246 .hw.init = &(struct clk_init_data){
3247 .name = "gcc_usb_hsic_system_clk",
3248 .parent_names = (const char *[]){
3249 "usb_hsic_system_clk_src",
3252 .flags = CLK_SET_RATE_PARENT,
3253 .ops = &clk_branch2_ops,
3258 static struct gdsc usb_hs_hsic_gdsc = {
3261 .name = "usb_hs_hsic",
3263 .pwrsts = PWRSTS_OFF_ON,
3266 static struct gdsc pcie0_gdsc = {
3271 .pwrsts = PWRSTS_OFF_ON,
3274 static struct gdsc pcie1_gdsc = {
3279 .pwrsts = PWRSTS_OFF_ON,
3282 static struct gdsc usb30_gdsc = {
3287 .pwrsts = PWRSTS_OFF_ON,
3290 static struct clk_regmap *gcc_apq8084_clocks[] = {
3291 [GPLL0] = &gpll0.clkr,
3292 [GPLL0_VOTE] = &gpll0_vote,
3293 [GPLL1] = &gpll1.clkr,
3294 [GPLL1_VOTE] = &gpll1_vote,
3295 [GPLL4] = &gpll4.clkr,
3296 [GPLL4_VOTE] = &gpll4_vote,
3297 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
3298 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
3299 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
3300 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
3301 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3302 [USB30_SEC_MASTER_CLK_SRC] = &usb30_sec_master_clk_src.clkr,
3303 [USB_HSIC_AHB_CLK_SRC] = &usb_hsic_ahb_clk_src.clkr,
3304 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3305 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3306 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3307 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3308 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3309 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3310 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3311 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3312 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3313 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3314 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3315 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3316 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3317 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3318 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3319 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3320 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3321 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3322 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3323 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3324 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3325 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3326 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3327 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3328 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3329 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3330 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
3331 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
3332 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
3333 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
3334 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3335 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3336 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
3337 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
3338 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
3339 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
3340 [CE1_CLK_SRC] = &ce1_clk_src.clkr,
3341 [CE2_CLK_SRC] = &ce2_clk_src.clkr,
3342 [CE3_CLK_SRC] = &ce3_clk_src.clkr,
3343 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3344 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3345 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3346 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
3347 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
3348 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
3349 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
3350 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3351 [SATA_ASIC0_CLK_SRC] = &sata_asic0_clk_src.clkr,
3352 [SATA_PMALIVE_CLK_SRC] = &sata_pmalive_clk_src.clkr,
3353 [SATA_RX_CLK_SRC] = &sata_rx_clk_src.clkr,
3354 [SATA_RX_OOB_CLK_SRC] = &sata_rx_oob_clk_src.clkr,
3355 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3356 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3357 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
3358 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
3359 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
3360 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
3361 [USB30_SEC_MOCK_UTMI_CLK_SRC] = &usb30_sec_mock_utmi_clk_src.clkr,
3362 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3363 [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
3364 [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
3365 [USB_HSIC_MOCK_UTMI_CLK_SRC] = &usb_hsic_mock_utmi_clk_src.clkr,
3366 [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
3367 [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
3368 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3369 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3370 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3371 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3372 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3373 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3374 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3375 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3376 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3377 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3378 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3379 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3380 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3381 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3382 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3383 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3384 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3385 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3386 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3387 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3388 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3389 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3390 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3391 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3392 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3393 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3394 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3395 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3396 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
3397 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
3398 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
3399 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
3400 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3401 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3402 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
3403 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
3404 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
3405 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
3406 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3407 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3408 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3409 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3410 [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr,
3411 [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr,
3412 [GCC_CE2_CLK] = &gcc_ce2_clk.clkr,
3413 [GCC_CE3_AHB_CLK] = &gcc_ce3_ahb_clk.clkr,
3414 [GCC_CE3_AXI_CLK] = &gcc_ce3_axi_clk.clkr,
3415 [GCC_CE3_CLK] = &gcc_ce3_clk.clkr,
3416 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3417 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3418 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3419 [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr,
3420 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3421 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3422 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3423 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3424 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3425 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3426 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3427 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3428 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3429 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3430 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3431 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3432 [GCC_PERIPH_NOC_USB_HSIC_AHB_CLK] = &gcc_periph_noc_usb_hsic_ahb_clk.clkr,
3433 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3434 [GCC_SATA_ASIC0_CLK] = &gcc_sata_asic0_clk.clkr,
3435 [GCC_SATA_AXI_CLK] = &gcc_sata_axi_clk.clkr,
3436 [GCC_SATA_CFG_AHB_CLK] = &gcc_sata_cfg_ahb_clk.clkr,
3437 [GCC_SATA_PMALIVE_CLK] = &gcc_sata_pmalive_clk.clkr,
3438 [GCC_SATA_RX_CLK] = &gcc_sata_rx_clk.clkr,
3439 [GCC_SATA_RX_OOB_CLK] = &gcc_sata_rx_oob_clk.clkr,
3440 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3441 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3442 [GCC_SDCC1_CDCCAL_FF_CLK] = &gcc_sdcc1_cdccal_ff_clk.clkr,
3443 [GCC_SDCC1_CDCCAL_SLEEP_CLK] = &gcc_sdcc1_cdccal_sleep_clk.clkr,
3444 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3445 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3446 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3447 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3448 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3449 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3450 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
3451 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
3452 [GCC_SYS_NOC_USB3_SEC_AXI_CLK] = &gcc_sys_noc_usb3_sec_axi_clk.clkr,
3453 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3454 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3455 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3456 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
3457 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
3458 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
3459 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
3460 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
3461 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
3462 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
3463 [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
3464 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3465 [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr,
3466 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
3467 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
3468 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
3469 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3470 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3471 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3472 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3473 [GCC_USB_HS_INACTIVITY_TIMERS_CLK] = &gcc_usb_hs_inactivity_timers_clk.clkr,
3474 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3475 [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
3476 [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
3477 [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
3478 [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
3479 [GCC_USB_HSIC_MOCK_UTMI_CLK] = &gcc_usb_hsic_mock_utmi_clk.clkr,
3480 [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
3483 static struct gdsc *gcc_apq8084_gdscs[] = {
3484 [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
3485 [PCIE0_GDSC] = &pcie0_gdsc,
3486 [PCIE1_GDSC] = &pcie1_gdsc,
3487 [USB30_GDSC] = &usb30_gdsc,
3490 static const struct qcom_reset_map gcc_apq8084_resets[] = {
3491 [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
3492 [GCC_CONFIG_NOC_BCR] = { 0x0140 },
3493 [GCC_PERIPH_NOC_BCR] = { 0x0180 },
3494 [GCC_IMEM_BCR] = { 0x0200 },
3495 [GCC_MMSS_BCR] = { 0x0240 },
3496 [GCC_QDSS_BCR] = { 0x0300 },
3497 [GCC_USB_30_BCR] = { 0x03c0 },
3498 [GCC_USB3_PHY_BCR] = { 0x03fc },
3499 [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
3500 [GCC_USB_HS_BCR] = { 0x0480 },
3501 [GCC_USB2A_PHY_BCR] = { 0x04a8 },
3502 [GCC_USB2B_PHY_BCR] = { 0x04b0 },
3503 [GCC_SDCC1_BCR] = { 0x04c0 },
3504 [GCC_SDCC2_BCR] = { 0x0500 },
3505 [GCC_SDCC3_BCR] = { 0x0540 },
3506 [GCC_SDCC4_BCR] = { 0x0580 },
3507 [GCC_BLSP1_BCR] = { 0x05c0 },
3508 [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
3509 [GCC_BLSP1_UART1_BCR] = { 0x0680 },
3510 [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
3511 [GCC_BLSP1_UART2_BCR] = { 0x0700 },
3512 [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
3513 [GCC_BLSP1_UART3_BCR] = { 0x0780 },
3514 [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
3515 [GCC_BLSP1_UART4_BCR] = { 0x0800 },
3516 [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
3517 [GCC_BLSP1_UART5_BCR] = { 0x0880 },
3518 [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
3519 [GCC_BLSP1_UART6_BCR] = { 0x0900 },
3520 [GCC_BLSP2_BCR] = { 0x0940 },
3521 [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
3522 [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
3523 [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
3524 [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
3525 [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
3526 [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
3527 [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
3528 [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
3529 [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
3530 [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
3531 [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
3532 [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
3533 [GCC_PDM_BCR] = { 0x0cc0 },
3534 [GCC_PRNG_BCR] = { 0x0d00 },
3535 [GCC_BAM_DMA_BCR] = { 0x0d40 },
3536 [GCC_TSIF_BCR] = { 0x0d80 },
3537 [GCC_TCSR_BCR] = { 0x0dc0 },
3538 [GCC_BOOT_ROM_BCR] = { 0x0e00 },
3539 [GCC_MSG_RAM_BCR] = { 0x0e40 },
3540 [GCC_TLMM_BCR] = { 0x0e80 },
3541 [GCC_MPM_BCR] = { 0x0ec0 },
3542 [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
3543 [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
3544 [GCC_SEC_CTRL_BCR] = { 0x0f40 },
3545 [GCC_SPMI_BCR] = { 0x0fc0 },
3546 [GCC_SPDM_BCR] = { 0x1000 },
3547 [GCC_CE1_BCR] = { 0x1040 },
3548 [GCC_CE2_BCR] = { 0x1080 },
3549 [GCC_BIMC_BCR] = { 0x1100 },
3550 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
3551 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
3552 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
3553 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
3554 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
3555 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
3556 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
3557 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
3558 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
3559 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
3560 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
3561 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
3562 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
3563 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
3564 [GCC_DEHR_BCR] = { 0x1300 },
3565 [GCC_RBCPR_BCR] = { 0x1380 },
3566 [GCC_MSS_RESTART] = { 0x1680 },
3567 [GCC_LPASS_RESTART] = { 0x16c0 },
3568 [GCC_WCSS_RESTART] = { 0x1700 },
3569 [GCC_VENUS_RESTART] = { 0x1740 },
3570 [GCC_COPSS_SMMU_BCR] = { 0x1a40 },
3571 [GCC_SPSS_BCR] = { 0x1a80 },
3572 [GCC_PCIE_0_BCR] = { 0x1ac0 },
3573 [GCC_PCIE_0_PHY_BCR] = { 0x1b00 },
3574 [GCC_PCIE_1_BCR] = { 0x1b40 },
3575 [GCC_PCIE_1_PHY_BCR] = { 0x1b80 },
3576 [GCC_USB_30_SEC_BCR] = { 0x1bc0 },
3577 [GCC_USB3_SEC_PHY_BCR] = { 0x1bfc },
3578 [GCC_SATA_BCR] = { 0x1c40 },
3579 [GCC_CE3_BCR] = { 0x1d00 },
3580 [GCC_UFS_BCR] = { 0x1d40 },
3581 [GCC_USB30_PHY_COM_BCR] = { 0x1e80 },
3584 static const struct regmap_config gcc_apq8084_regmap_config = {
3588 .max_register = 0x1fc0,
3592 static const struct qcom_cc_desc gcc_apq8084_desc = {
3593 .config = &gcc_apq8084_regmap_config,
3594 .clks = gcc_apq8084_clocks,
3595 .num_clks = ARRAY_SIZE(gcc_apq8084_clocks),
3596 .resets = gcc_apq8084_resets,
3597 .num_resets = ARRAY_SIZE(gcc_apq8084_resets),
3598 .gdscs = gcc_apq8084_gdscs,
3599 .num_gdscs = ARRAY_SIZE(gcc_apq8084_gdscs),
3602 static const struct of_device_id gcc_apq8084_match_table[] = {
3603 { .compatible = "qcom,gcc-apq8084" },
3606 MODULE_DEVICE_TABLE(of, gcc_apq8084_match_table);
3608 static int gcc_apq8084_probe(struct platform_device *pdev)
3611 struct device *dev = &pdev->dev;
3613 ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
3617 ret = qcom_cc_register_sleep_clk(dev);
3621 return qcom_cc_probe(pdev, &gcc_apq8084_desc);
3624 static struct platform_driver gcc_apq8084_driver = {
3625 .probe = gcc_apq8084_probe,
3627 .name = "gcc-apq8084",
3628 .of_match_table = gcc_apq8084_match_table,
3632 static int __init gcc_apq8084_init(void)
3634 return platform_driver_register(&gcc_apq8084_driver);
3636 core_initcall(gcc_apq8084_init);
3638 static void __exit gcc_apq8084_exit(void)
3640 platform_driver_unregister(&gcc_apq8084_driver);
3642 module_exit(gcc_apq8084_exit);
3644 MODULE_DESCRIPTION("QCOM GCC APQ8084 Driver");
3645 MODULE_LICENSE("GPL v2");
3646 MODULE_ALIAS("platform:gcc-apq8084");