2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
26 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
35 static struct clk_pll pll0 = {
43 .clkr.hw.init = &(struct clk_init_data){
45 .parent_names = (const char *[]){ "pxo" },
51 static struct clk_regmap pll0_vote = {
53 .enable_mask = BIT(0),
54 .hw.init = &(struct clk_init_data){
56 .parent_names = (const char *[]){ "pll0" },
58 .ops = &clk_pll_vote_ops,
62 static struct clk_pll pll3 = {
70 .clkr.hw.init = &(struct clk_init_data){
72 .parent_names = (const char *[]){ "pxo" },
78 static struct clk_regmap pll4_vote = {
80 .enable_mask = BIT(4),
81 .hw.init = &(struct clk_init_data){
83 .parent_names = (const char *[]){ "pll4" },
85 .ops = &clk_pll_vote_ops,
89 static struct clk_pll pll8 = {
97 .clkr.hw.init = &(struct clk_init_data){
99 .parent_names = (const char *[]){ "pxo" },
105 static struct clk_regmap pll8_vote = {
106 .enable_reg = 0x34c0,
107 .enable_mask = BIT(8),
108 .hw.init = &(struct clk_init_data){
110 .parent_names = (const char *[]){ "pll8" },
112 .ops = &clk_pll_vote_ops,
116 static struct clk_pll pll14 = {
120 .config_reg = 0x31d4,
122 .status_reg = 0x31d8,
124 .clkr.hw.init = &(struct clk_init_data){
126 .parent_names = (const char *[]){ "pxo" },
132 static struct clk_regmap pll14_vote = {
133 .enable_reg = 0x34c0,
134 .enable_mask = BIT(14),
135 .hw.init = &(struct clk_init_data){
136 .name = "pll14_vote",
137 .parent_names = (const char *[]){ "pll14" },
139 .ops = &clk_pll_vote_ops,
151 static const struct parent_map gcc_pxo_pll8_map[] = {
156 static const char *gcc_pxo_pll8[] = {
161 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
167 static const char *gcc_pxo_pll8_cxo[] = {
173 static const struct parent_map gcc_pxo_pll3_map[] = {
178 static const struct parent_map gcc_pxo_pll3_sata_map[] = {
183 static const char *gcc_pxo_pll3[] = {
188 static const struct parent_map gcc_pxo_pll8_pll0[] = {
194 static const char *gcc_pxo_pll8_pll0_map[] = {
200 static struct freq_tbl clk_tbl_gsbi_uart[] = {
201 { 1843200, P_PLL8, 2, 6, 625 },
202 { 3686400, P_PLL8, 2, 12, 625 },
203 { 7372800, P_PLL8, 2, 24, 625 },
204 { 14745600, P_PLL8, 2, 48, 625 },
205 { 16000000, P_PLL8, 4, 1, 6 },
206 { 24000000, P_PLL8, 4, 1, 4 },
207 { 32000000, P_PLL8, 4, 1, 3 },
208 { 40000000, P_PLL8, 1, 5, 48 },
209 { 46400000, P_PLL8, 1, 29, 240 },
210 { 48000000, P_PLL8, 4, 1, 2 },
211 { 51200000, P_PLL8, 1, 2, 15 },
212 { 56000000, P_PLL8, 1, 7, 48 },
213 { 58982400, P_PLL8, 1, 96, 625 },
214 { 64000000, P_PLL8, 2, 1, 3 },
218 static struct clk_rcg gsbi1_uart_src = {
223 .mnctr_reset_bit = 7,
224 .mnctr_mode_shift = 5,
235 .parent_map = gcc_pxo_pll8_map,
237 .freq_tbl = clk_tbl_gsbi_uart,
239 .enable_reg = 0x29d4,
240 .enable_mask = BIT(11),
241 .hw.init = &(struct clk_init_data){
242 .name = "gsbi1_uart_src",
243 .parent_names = gcc_pxo_pll8,
246 .flags = CLK_SET_PARENT_GATE,
251 static struct clk_branch gsbi1_uart_clk = {
255 .enable_reg = 0x29d4,
256 .enable_mask = BIT(9),
257 .hw.init = &(struct clk_init_data){
258 .name = "gsbi1_uart_clk",
259 .parent_names = (const char *[]){
263 .ops = &clk_branch_ops,
264 .flags = CLK_SET_RATE_PARENT,
269 static struct clk_rcg gsbi2_uart_src = {
274 .mnctr_reset_bit = 7,
275 .mnctr_mode_shift = 5,
286 .parent_map = gcc_pxo_pll8_map,
288 .freq_tbl = clk_tbl_gsbi_uart,
290 .enable_reg = 0x29f4,
291 .enable_mask = BIT(11),
292 .hw.init = &(struct clk_init_data){
293 .name = "gsbi2_uart_src",
294 .parent_names = gcc_pxo_pll8,
297 .flags = CLK_SET_PARENT_GATE,
302 static struct clk_branch gsbi2_uart_clk = {
306 .enable_reg = 0x29f4,
307 .enable_mask = BIT(9),
308 .hw.init = &(struct clk_init_data){
309 .name = "gsbi2_uart_clk",
310 .parent_names = (const char *[]){
314 .ops = &clk_branch_ops,
315 .flags = CLK_SET_RATE_PARENT,
320 static struct clk_rcg gsbi4_uart_src = {
325 .mnctr_reset_bit = 7,
326 .mnctr_mode_shift = 5,
337 .parent_map = gcc_pxo_pll8_map,
339 .freq_tbl = clk_tbl_gsbi_uart,
341 .enable_reg = 0x2a34,
342 .enable_mask = BIT(11),
343 .hw.init = &(struct clk_init_data){
344 .name = "gsbi4_uart_src",
345 .parent_names = gcc_pxo_pll8,
348 .flags = CLK_SET_PARENT_GATE,
353 static struct clk_branch gsbi4_uart_clk = {
357 .enable_reg = 0x2a34,
358 .enable_mask = BIT(9),
359 .hw.init = &(struct clk_init_data){
360 .name = "gsbi4_uart_clk",
361 .parent_names = (const char *[]){
365 .ops = &clk_branch_ops,
366 .flags = CLK_SET_RATE_PARENT,
371 static struct clk_rcg gsbi5_uart_src = {
376 .mnctr_reset_bit = 7,
377 .mnctr_mode_shift = 5,
388 .parent_map = gcc_pxo_pll8_map,
390 .freq_tbl = clk_tbl_gsbi_uart,
392 .enable_reg = 0x2a54,
393 .enable_mask = BIT(11),
394 .hw.init = &(struct clk_init_data){
395 .name = "gsbi5_uart_src",
396 .parent_names = gcc_pxo_pll8,
399 .flags = CLK_SET_PARENT_GATE,
404 static struct clk_branch gsbi5_uart_clk = {
408 .enable_reg = 0x2a54,
409 .enable_mask = BIT(9),
410 .hw.init = &(struct clk_init_data){
411 .name = "gsbi5_uart_clk",
412 .parent_names = (const char *[]){
416 .ops = &clk_branch_ops,
417 .flags = CLK_SET_RATE_PARENT,
422 static struct clk_rcg gsbi6_uart_src = {
427 .mnctr_reset_bit = 7,
428 .mnctr_mode_shift = 5,
439 .parent_map = gcc_pxo_pll8_map,
441 .freq_tbl = clk_tbl_gsbi_uart,
443 .enable_reg = 0x2a74,
444 .enable_mask = BIT(11),
445 .hw.init = &(struct clk_init_data){
446 .name = "gsbi6_uart_src",
447 .parent_names = gcc_pxo_pll8,
450 .flags = CLK_SET_PARENT_GATE,
455 static struct clk_branch gsbi6_uart_clk = {
459 .enable_reg = 0x2a74,
460 .enable_mask = BIT(9),
461 .hw.init = &(struct clk_init_data){
462 .name = "gsbi6_uart_clk",
463 .parent_names = (const char *[]){
467 .ops = &clk_branch_ops,
468 .flags = CLK_SET_RATE_PARENT,
473 static struct clk_rcg gsbi7_uart_src = {
478 .mnctr_reset_bit = 7,
479 .mnctr_mode_shift = 5,
490 .parent_map = gcc_pxo_pll8_map,
492 .freq_tbl = clk_tbl_gsbi_uart,
494 .enable_reg = 0x2a94,
495 .enable_mask = BIT(11),
496 .hw.init = &(struct clk_init_data){
497 .name = "gsbi7_uart_src",
498 .parent_names = gcc_pxo_pll8,
501 .flags = CLK_SET_PARENT_GATE,
506 static struct clk_branch gsbi7_uart_clk = {
510 .enable_reg = 0x2a94,
511 .enable_mask = BIT(9),
512 .hw.init = &(struct clk_init_data){
513 .name = "gsbi7_uart_clk",
514 .parent_names = (const char *[]){
518 .ops = &clk_branch_ops,
519 .flags = CLK_SET_RATE_PARENT,
524 static struct freq_tbl clk_tbl_gsbi_qup[] = {
525 { 1100000, P_PXO, 1, 2, 49 },
526 { 5400000, P_PXO, 1, 1, 5 },
527 { 10800000, P_PXO, 1, 2, 5 },
528 { 15060000, P_PLL8, 1, 2, 51 },
529 { 24000000, P_PLL8, 4, 1, 4 },
530 { 25000000, P_PXO, 1, 0, 0 },
531 { 25600000, P_PLL8, 1, 1, 15 },
532 { 48000000, P_PLL8, 4, 1, 2 },
533 { 51200000, P_PLL8, 1, 2, 15 },
537 static struct clk_rcg gsbi1_qup_src = {
542 .mnctr_reset_bit = 7,
543 .mnctr_mode_shift = 5,
554 .parent_map = gcc_pxo_pll8_map,
556 .freq_tbl = clk_tbl_gsbi_qup,
558 .enable_reg = 0x29cc,
559 .enable_mask = BIT(11),
560 .hw.init = &(struct clk_init_data){
561 .name = "gsbi1_qup_src",
562 .parent_names = gcc_pxo_pll8,
565 .flags = CLK_SET_PARENT_GATE,
570 static struct clk_branch gsbi1_qup_clk = {
574 .enable_reg = 0x29cc,
575 .enable_mask = BIT(9),
576 .hw.init = &(struct clk_init_data){
577 .name = "gsbi1_qup_clk",
578 .parent_names = (const char *[]){ "gsbi1_qup_src" },
580 .ops = &clk_branch_ops,
581 .flags = CLK_SET_RATE_PARENT,
586 static struct clk_rcg gsbi2_qup_src = {
591 .mnctr_reset_bit = 7,
592 .mnctr_mode_shift = 5,
603 .parent_map = gcc_pxo_pll8_map,
605 .freq_tbl = clk_tbl_gsbi_qup,
607 .enable_reg = 0x29ec,
608 .enable_mask = BIT(11),
609 .hw.init = &(struct clk_init_data){
610 .name = "gsbi2_qup_src",
611 .parent_names = gcc_pxo_pll8,
614 .flags = CLK_SET_PARENT_GATE,
619 static struct clk_branch gsbi2_qup_clk = {
623 .enable_reg = 0x29ec,
624 .enable_mask = BIT(9),
625 .hw.init = &(struct clk_init_data){
626 .name = "gsbi2_qup_clk",
627 .parent_names = (const char *[]){ "gsbi2_qup_src" },
629 .ops = &clk_branch_ops,
630 .flags = CLK_SET_RATE_PARENT,
635 static struct clk_rcg gsbi4_qup_src = {
640 .mnctr_reset_bit = 7,
641 .mnctr_mode_shift = 5,
652 .parent_map = gcc_pxo_pll8_map,
654 .freq_tbl = clk_tbl_gsbi_qup,
656 .enable_reg = 0x2a2c,
657 .enable_mask = BIT(11),
658 .hw.init = &(struct clk_init_data){
659 .name = "gsbi4_qup_src",
660 .parent_names = gcc_pxo_pll8,
663 .flags = CLK_SET_PARENT_GATE,
668 static struct clk_branch gsbi4_qup_clk = {
672 .enable_reg = 0x2a2c,
673 .enable_mask = BIT(9),
674 .hw.init = &(struct clk_init_data){
675 .name = "gsbi4_qup_clk",
676 .parent_names = (const char *[]){ "gsbi4_qup_src" },
678 .ops = &clk_branch_ops,
679 .flags = CLK_SET_RATE_PARENT,
684 static struct clk_rcg gsbi5_qup_src = {
689 .mnctr_reset_bit = 7,
690 .mnctr_mode_shift = 5,
701 .parent_map = gcc_pxo_pll8_map,
703 .freq_tbl = clk_tbl_gsbi_qup,
705 .enable_reg = 0x2a4c,
706 .enable_mask = BIT(11),
707 .hw.init = &(struct clk_init_data){
708 .name = "gsbi5_qup_src",
709 .parent_names = gcc_pxo_pll8,
712 .flags = CLK_SET_PARENT_GATE,
717 static struct clk_branch gsbi5_qup_clk = {
721 .enable_reg = 0x2a4c,
722 .enable_mask = BIT(9),
723 .hw.init = &(struct clk_init_data){
724 .name = "gsbi5_qup_clk",
725 .parent_names = (const char *[]){ "gsbi5_qup_src" },
727 .ops = &clk_branch_ops,
728 .flags = CLK_SET_RATE_PARENT,
733 static struct clk_rcg gsbi6_qup_src = {
738 .mnctr_reset_bit = 7,
739 .mnctr_mode_shift = 5,
750 .parent_map = gcc_pxo_pll8_map,
752 .freq_tbl = clk_tbl_gsbi_qup,
754 .enable_reg = 0x2a6c,
755 .enable_mask = BIT(11),
756 .hw.init = &(struct clk_init_data){
757 .name = "gsbi6_qup_src",
758 .parent_names = gcc_pxo_pll8,
761 .flags = CLK_SET_PARENT_GATE,
766 static struct clk_branch gsbi6_qup_clk = {
770 .enable_reg = 0x2a6c,
771 .enable_mask = BIT(9),
772 .hw.init = &(struct clk_init_data){
773 .name = "gsbi6_qup_clk",
774 .parent_names = (const char *[]){ "gsbi6_qup_src" },
776 .ops = &clk_branch_ops,
777 .flags = CLK_SET_RATE_PARENT,
782 static struct clk_rcg gsbi7_qup_src = {
787 .mnctr_reset_bit = 7,
788 .mnctr_mode_shift = 5,
799 .parent_map = gcc_pxo_pll8_map,
801 .freq_tbl = clk_tbl_gsbi_qup,
803 .enable_reg = 0x2a8c,
804 .enable_mask = BIT(11),
805 .hw.init = &(struct clk_init_data){
806 .name = "gsbi7_qup_src",
807 .parent_names = gcc_pxo_pll8,
810 .flags = CLK_SET_PARENT_GATE,
815 static struct clk_branch gsbi7_qup_clk = {
819 .enable_reg = 0x2a8c,
820 .enable_mask = BIT(9),
821 .hw.init = &(struct clk_init_data){
822 .name = "gsbi7_qup_clk",
823 .parent_names = (const char *[]){ "gsbi7_qup_src" },
825 .ops = &clk_branch_ops,
826 .flags = CLK_SET_RATE_PARENT,
831 static struct clk_branch gsbi1_h_clk = {
837 .enable_reg = 0x29c0,
838 .enable_mask = BIT(4),
839 .hw.init = &(struct clk_init_data){
840 .name = "gsbi1_h_clk",
841 .ops = &clk_branch_ops,
842 .flags = CLK_IS_ROOT,
847 static struct clk_branch gsbi2_h_clk = {
853 .enable_reg = 0x29e0,
854 .enable_mask = BIT(4),
855 .hw.init = &(struct clk_init_data){
856 .name = "gsbi2_h_clk",
857 .ops = &clk_branch_ops,
858 .flags = CLK_IS_ROOT,
863 static struct clk_branch gsbi4_h_clk = {
869 .enable_reg = 0x2a20,
870 .enable_mask = BIT(4),
871 .hw.init = &(struct clk_init_data){
872 .name = "gsbi4_h_clk",
873 .ops = &clk_branch_ops,
874 .flags = CLK_IS_ROOT,
879 static struct clk_branch gsbi5_h_clk = {
885 .enable_reg = 0x2a40,
886 .enable_mask = BIT(4),
887 .hw.init = &(struct clk_init_data){
888 .name = "gsbi5_h_clk",
889 .ops = &clk_branch_ops,
890 .flags = CLK_IS_ROOT,
895 static struct clk_branch gsbi6_h_clk = {
901 .enable_reg = 0x2a60,
902 .enable_mask = BIT(4),
903 .hw.init = &(struct clk_init_data){
904 .name = "gsbi6_h_clk",
905 .ops = &clk_branch_ops,
906 .flags = CLK_IS_ROOT,
911 static struct clk_branch gsbi7_h_clk = {
917 .enable_reg = 0x2a80,
918 .enable_mask = BIT(4),
919 .hw.init = &(struct clk_init_data){
920 .name = "gsbi7_h_clk",
921 .ops = &clk_branch_ops,
922 .flags = CLK_IS_ROOT,
927 static const struct freq_tbl clk_tbl_gp[] = {
928 { 12500000, P_PXO, 2, 0, 0 },
929 { 25000000, P_PXO, 1, 0, 0 },
930 { 64000000, P_PLL8, 2, 1, 3 },
931 { 76800000, P_PLL8, 1, 1, 5 },
932 { 96000000, P_PLL8, 4, 0, 0 },
933 { 128000000, P_PLL8, 3, 0, 0 },
934 { 192000000, P_PLL8, 2, 0, 0 },
938 static struct clk_rcg gp0_src = {
943 .mnctr_reset_bit = 7,
944 .mnctr_mode_shift = 5,
955 .parent_map = gcc_pxo_pll8_cxo_map,
957 .freq_tbl = clk_tbl_gp,
959 .enable_reg = 0x2d24,
960 .enable_mask = BIT(11),
961 .hw.init = &(struct clk_init_data){
963 .parent_names = gcc_pxo_pll8_cxo,
966 .flags = CLK_SET_PARENT_GATE,
971 static struct clk_branch gp0_clk = {
975 .enable_reg = 0x2d24,
976 .enable_mask = BIT(9),
977 .hw.init = &(struct clk_init_data){
979 .parent_names = (const char *[]){ "gp0_src" },
981 .ops = &clk_branch_ops,
982 .flags = CLK_SET_RATE_PARENT,
987 static struct clk_rcg gp1_src = {
992 .mnctr_reset_bit = 7,
993 .mnctr_mode_shift = 5,
1004 .parent_map = gcc_pxo_pll8_cxo_map,
1006 .freq_tbl = clk_tbl_gp,
1008 .enable_reg = 0x2d44,
1009 .enable_mask = BIT(11),
1010 .hw.init = &(struct clk_init_data){
1012 .parent_names = gcc_pxo_pll8_cxo,
1014 .ops = &clk_rcg_ops,
1015 .flags = CLK_SET_RATE_GATE,
1020 static struct clk_branch gp1_clk = {
1024 .enable_reg = 0x2d44,
1025 .enable_mask = BIT(9),
1026 .hw.init = &(struct clk_init_data){
1028 .parent_names = (const char *[]){ "gp1_src" },
1030 .ops = &clk_branch_ops,
1031 .flags = CLK_SET_RATE_PARENT,
1036 static struct clk_rcg gp2_src = {
1041 .mnctr_reset_bit = 7,
1042 .mnctr_mode_shift = 5,
1053 .parent_map = gcc_pxo_pll8_cxo_map,
1055 .freq_tbl = clk_tbl_gp,
1057 .enable_reg = 0x2d64,
1058 .enable_mask = BIT(11),
1059 .hw.init = &(struct clk_init_data){
1061 .parent_names = gcc_pxo_pll8_cxo,
1063 .ops = &clk_rcg_ops,
1064 .flags = CLK_SET_RATE_GATE,
1069 static struct clk_branch gp2_clk = {
1073 .enable_reg = 0x2d64,
1074 .enable_mask = BIT(9),
1075 .hw.init = &(struct clk_init_data){
1077 .parent_names = (const char *[]){ "gp2_src" },
1079 .ops = &clk_branch_ops,
1080 .flags = CLK_SET_RATE_PARENT,
1085 static struct clk_branch pmem_clk = {
1091 .enable_reg = 0x25a0,
1092 .enable_mask = BIT(4),
1093 .hw.init = &(struct clk_init_data){
1095 .ops = &clk_branch_ops,
1096 .flags = CLK_IS_ROOT,
1101 static struct clk_rcg prng_src = {
1109 .parent_map = gcc_pxo_pll8_map,
1112 .hw.init = &(struct clk_init_data){
1114 .parent_names = gcc_pxo_pll8,
1116 .ops = &clk_rcg_ops,
1121 static struct clk_branch prng_clk = {
1123 .halt_check = BRANCH_HALT_VOTED,
1126 .enable_reg = 0x3080,
1127 .enable_mask = BIT(10),
1128 .hw.init = &(struct clk_init_data){
1130 .parent_names = (const char *[]){ "prng_src" },
1132 .ops = &clk_branch_ops,
1137 static const struct freq_tbl clk_tbl_sdc[] = {
1138 { 200000, P_PXO, 2, 2, 125 },
1139 { 400000, P_PLL8, 4, 1, 240 },
1140 { 16000000, P_PLL8, 4, 1, 6 },
1141 { 17070000, P_PLL8, 1, 2, 45 },
1142 { 20210000, P_PLL8, 1, 1, 19 },
1143 { 24000000, P_PLL8, 4, 1, 4 },
1144 { 48000000, P_PLL8, 4, 1, 2 },
1145 { 64000000, P_PLL8, 3, 1, 2 },
1146 { 96000000, P_PLL8, 4, 0, 0 },
1147 { 192000000, P_PLL8, 2, 0, 0 },
1151 static struct clk_rcg sdc1_src = {
1156 .mnctr_reset_bit = 7,
1157 .mnctr_mode_shift = 5,
1168 .parent_map = gcc_pxo_pll8_map,
1170 .freq_tbl = clk_tbl_sdc,
1172 .enable_reg = 0x282c,
1173 .enable_mask = BIT(11),
1174 .hw.init = &(struct clk_init_data){
1176 .parent_names = gcc_pxo_pll8,
1178 .ops = &clk_rcg_ops,
1179 .flags = CLK_SET_RATE_GATE,
1184 static struct clk_branch sdc1_clk = {
1188 .enable_reg = 0x282c,
1189 .enable_mask = BIT(9),
1190 .hw.init = &(struct clk_init_data){
1192 .parent_names = (const char *[]){ "sdc1_src" },
1194 .ops = &clk_branch_ops,
1195 .flags = CLK_SET_RATE_PARENT,
1200 static struct clk_rcg sdc3_src = {
1205 .mnctr_reset_bit = 7,
1206 .mnctr_mode_shift = 5,
1217 .parent_map = gcc_pxo_pll8_map,
1219 .freq_tbl = clk_tbl_sdc,
1221 .enable_reg = 0x286c,
1222 .enable_mask = BIT(11),
1223 .hw.init = &(struct clk_init_data){
1225 .parent_names = gcc_pxo_pll8,
1227 .ops = &clk_rcg_ops,
1228 .flags = CLK_SET_RATE_GATE,
1233 static struct clk_branch sdc3_clk = {
1237 .enable_reg = 0x286c,
1238 .enable_mask = BIT(9),
1239 .hw.init = &(struct clk_init_data){
1241 .parent_names = (const char *[]){ "sdc3_src" },
1243 .ops = &clk_branch_ops,
1244 .flags = CLK_SET_RATE_PARENT,
1249 static struct clk_branch sdc1_h_clk = {
1255 .enable_reg = 0x2820,
1256 .enable_mask = BIT(4),
1257 .hw.init = &(struct clk_init_data){
1258 .name = "sdc1_h_clk",
1259 .ops = &clk_branch_ops,
1260 .flags = CLK_IS_ROOT,
1265 static struct clk_branch sdc3_h_clk = {
1271 .enable_reg = 0x2860,
1272 .enable_mask = BIT(4),
1273 .hw.init = &(struct clk_init_data){
1274 .name = "sdc3_h_clk",
1275 .ops = &clk_branch_ops,
1276 .flags = CLK_IS_ROOT,
1281 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1282 { 105000, P_PXO, 1, 1, 256 },
1286 static struct clk_rcg tsif_ref_src = {
1291 .mnctr_reset_bit = 7,
1292 .mnctr_mode_shift = 5,
1303 .parent_map = gcc_pxo_pll8_map,
1305 .freq_tbl = clk_tbl_tsif_ref,
1307 .enable_reg = 0x2710,
1308 .enable_mask = BIT(11),
1309 .hw.init = &(struct clk_init_data){
1310 .name = "tsif_ref_src",
1311 .parent_names = gcc_pxo_pll8,
1313 .ops = &clk_rcg_ops,
1314 .flags = CLK_SET_RATE_GATE,
1319 static struct clk_branch tsif_ref_clk = {
1323 .enable_reg = 0x2710,
1324 .enable_mask = BIT(9),
1325 .hw.init = &(struct clk_init_data){
1326 .name = "tsif_ref_clk",
1327 .parent_names = (const char *[]){ "tsif_ref_src" },
1329 .ops = &clk_branch_ops,
1330 .flags = CLK_SET_RATE_PARENT,
1335 static struct clk_branch tsif_h_clk = {
1341 .enable_reg = 0x2700,
1342 .enable_mask = BIT(4),
1343 .hw.init = &(struct clk_init_data){
1344 .name = "tsif_h_clk",
1345 .ops = &clk_branch_ops,
1346 .flags = CLK_IS_ROOT,
1351 static struct clk_branch dma_bam_h_clk = {
1357 .enable_reg = 0x25c0,
1358 .enable_mask = BIT(4),
1359 .hw.init = &(struct clk_init_data){
1360 .name = "dma_bam_h_clk",
1361 .ops = &clk_branch_ops,
1362 .flags = CLK_IS_ROOT,
1367 static struct clk_branch adm0_clk = {
1369 .halt_check = BRANCH_HALT_VOTED,
1372 .enable_reg = 0x3080,
1373 .enable_mask = BIT(2),
1374 .hw.init = &(struct clk_init_data){
1376 .ops = &clk_branch_ops,
1377 .flags = CLK_IS_ROOT,
1382 static struct clk_branch adm0_pbus_clk = {
1386 .halt_check = BRANCH_HALT_VOTED,
1389 .enable_reg = 0x3080,
1390 .enable_mask = BIT(3),
1391 .hw.init = &(struct clk_init_data){
1392 .name = "adm0_pbus_clk",
1393 .ops = &clk_branch_ops,
1394 .flags = CLK_IS_ROOT,
1399 static struct clk_branch pmic_arb0_h_clk = {
1401 .halt_check = BRANCH_HALT_VOTED,
1404 .enable_reg = 0x3080,
1405 .enable_mask = BIT(8),
1406 .hw.init = &(struct clk_init_data){
1407 .name = "pmic_arb0_h_clk",
1408 .ops = &clk_branch_ops,
1409 .flags = CLK_IS_ROOT,
1414 static struct clk_branch pmic_arb1_h_clk = {
1416 .halt_check = BRANCH_HALT_VOTED,
1419 .enable_reg = 0x3080,
1420 .enable_mask = BIT(9),
1421 .hw.init = &(struct clk_init_data){
1422 .name = "pmic_arb1_h_clk",
1423 .ops = &clk_branch_ops,
1424 .flags = CLK_IS_ROOT,
1429 static struct clk_branch pmic_ssbi2_clk = {
1431 .halt_check = BRANCH_HALT_VOTED,
1434 .enable_reg = 0x3080,
1435 .enable_mask = BIT(7),
1436 .hw.init = &(struct clk_init_data){
1437 .name = "pmic_ssbi2_clk",
1438 .ops = &clk_branch_ops,
1439 .flags = CLK_IS_ROOT,
1444 static struct clk_branch rpm_msg_ram_h_clk = {
1448 .halt_check = BRANCH_HALT_VOTED,
1451 .enable_reg = 0x3080,
1452 .enable_mask = BIT(6),
1453 .hw.init = &(struct clk_init_data){
1454 .name = "rpm_msg_ram_h_clk",
1455 .ops = &clk_branch_ops,
1456 .flags = CLK_IS_ROOT,
1461 static const struct freq_tbl clk_tbl_pcie_ref[] = {
1462 { 100000000, P_PLL3, 12, 0, 0 },
1466 static struct clk_rcg pcie_ref_src = {
1474 .parent_map = gcc_pxo_pll3_map,
1476 .freq_tbl = clk_tbl_pcie_ref,
1478 .enable_reg = 0x3860,
1479 .enable_mask = BIT(11),
1480 .hw.init = &(struct clk_init_data){
1481 .name = "pcie_ref_src",
1482 .parent_names = gcc_pxo_pll3,
1484 .ops = &clk_rcg_ops,
1485 .flags = CLK_SET_RATE_GATE,
1490 static struct clk_branch pcie_ref_src_clk = {
1494 .enable_reg = 0x3860,
1495 .enable_mask = BIT(9),
1496 .hw.init = &(struct clk_init_data){
1497 .name = "pcie_ref_src_clk",
1498 .parent_names = (const char *[]){ "pcie_ref_src" },
1500 .ops = &clk_branch_ops,
1501 .flags = CLK_SET_RATE_PARENT,
1506 static struct clk_branch pcie_a_clk = {
1510 .enable_reg = 0x22c0,
1511 .enable_mask = BIT(4),
1512 .hw.init = &(struct clk_init_data){
1513 .name = "pcie_a_clk",
1514 .ops = &clk_branch_ops,
1515 .flags = CLK_IS_ROOT,
1520 static struct clk_branch pcie_aux_clk = {
1524 .enable_reg = 0x22c8,
1525 .enable_mask = BIT(4),
1526 .hw.init = &(struct clk_init_data){
1527 .name = "pcie_aux_clk",
1528 .ops = &clk_branch_ops,
1529 .flags = CLK_IS_ROOT,
1534 static struct clk_branch pcie_h_clk = {
1538 .enable_reg = 0x22cc,
1539 .enable_mask = BIT(4),
1540 .hw.init = &(struct clk_init_data){
1541 .name = "pcie_h_clk",
1542 .ops = &clk_branch_ops,
1543 .flags = CLK_IS_ROOT,
1548 static struct clk_branch pcie_phy_clk = {
1552 .enable_reg = 0x22d0,
1553 .enable_mask = BIT(4),
1554 .hw.init = &(struct clk_init_data){
1555 .name = "pcie_phy_clk",
1556 .ops = &clk_branch_ops,
1557 .flags = CLK_IS_ROOT,
1562 static struct clk_rcg pcie1_ref_src = {
1570 .parent_map = gcc_pxo_pll3_map,
1572 .freq_tbl = clk_tbl_pcie_ref,
1574 .enable_reg = 0x3aa0,
1575 .enable_mask = BIT(11),
1576 .hw.init = &(struct clk_init_data){
1577 .name = "pcie1_ref_src",
1578 .parent_names = gcc_pxo_pll3,
1580 .ops = &clk_rcg_ops,
1581 .flags = CLK_SET_RATE_GATE,
1586 static struct clk_branch pcie1_ref_src_clk = {
1590 .enable_reg = 0x3aa0,
1591 .enable_mask = BIT(9),
1592 .hw.init = &(struct clk_init_data){
1593 .name = "pcie1_ref_src_clk",
1594 .parent_names = (const char *[]){ "pcie1_ref_src" },
1596 .ops = &clk_branch_ops,
1597 .flags = CLK_SET_RATE_PARENT,
1602 static struct clk_branch pcie1_a_clk = {
1606 .enable_reg = 0x3a80,
1607 .enable_mask = BIT(4),
1608 .hw.init = &(struct clk_init_data){
1609 .name = "pcie1_a_clk",
1610 .ops = &clk_branch_ops,
1611 .flags = CLK_IS_ROOT,
1616 static struct clk_branch pcie1_aux_clk = {
1620 .enable_reg = 0x3a88,
1621 .enable_mask = BIT(4),
1622 .hw.init = &(struct clk_init_data){
1623 .name = "pcie1_aux_clk",
1624 .ops = &clk_branch_ops,
1625 .flags = CLK_IS_ROOT,
1630 static struct clk_branch pcie1_h_clk = {
1634 .enable_reg = 0x3a8c,
1635 .enable_mask = BIT(4),
1636 .hw.init = &(struct clk_init_data){
1637 .name = "pcie1_h_clk",
1638 .ops = &clk_branch_ops,
1639 .flags = CLK_IS_ROOT,
1644 static struct clk_branch pcie1_phy_clk = {
1648 .enable_reg = 0x3a90,
1649 .enable_mask = BIT(4),
1650 .hw.init = &(struct clk_init_data){
1651 .name = "pcie1_phy_clk",
1652 .ops = &clk_branch_ops,
1653 .flags = CLK_IS_ROOT,
1658 static struct clk_rcg pcie2_ref_src = {
1666 .parent_map = gcc_pxo_pll3_map,
1668 .freq_tbl = clk_tbl_pcie_ref,
1670 .enable_reg = 0x3ae0,
1671 .enable_mask = BIT(11),
1672 .hw.init = &(struct clk_init_data){
1673 .name = "pcie2_ref_src",
1674 .parent_names = gcc_pxo_pll3,
1676 .ops = &clk_rcg_ops,
1677 .flags = CLK_SET_RATE_GATE,
1682 static struct clk_branch pcie2_ref_src_clk = {
1686 .enable_reg = 0x3ae0,
1687 .enable_mask = BIT(9),
1688 .hw.init = &(struct clk_init_data){
1689 .name = "pcie2_ref_src_clk",
1690 .parent_names = (const char *[]){ "pcie2_ref_src" },
1692 .ops = &clk_branch_ops,
1693 .flags = CLK_SET_RATE_PARENT,
1698 static struct clk_branch pcie2_a_clk = {
1702 .enable_reg = 0x3ac0,
1703 .enable_mask = BIT(4),
1704 .hw.init = &(struct clk_init_data){
1705 .name = "pcie2_a_clk",
1706 .ops = &clk_branch_ops,
1707 .flags = CLK_IS_ROOT,
1712 static struct clk_branch pcie2_aux_clk = {
1716 .enable_reg = 0x3ac8,
1717 .enable_mask = BIT(4),
1718 .hw.init = &(struct clk_init_data){
1719 .name = "pcie2_aux_clk",
1720 .ops = &clk_branch_ops,
1721 .flags = CLK_IS_ROOT,
1726 static struct clk_branch pcie2_h_clk = {
1730 .enable_reg = 0x3acc,
1731 .enable_mask = BIT(4),
1732 .hw.init = &(struct clk_init_data){
1733 .name = "pcie2_h_clk",
1734 .ops = &clk_branch_ops,
1735 .flags = CLK_IS_ROOT,
1740 static struct clk_branch pcie2_phy_clk = {
1744 .enable_reg = 0x3ad0,
1745 .enable_mask = BIT(4),
1746 .hw.init = &(struct clk_init_data){
1747 .name = "pcie2_phy_clk",
1748 .ops = &clk_branch_ops,
1749 .flags = CLK_IS_ROOT,
1754 static const struct freq_tbl clk_tbl_sata_ref[] = {
1755 { 100000000, P_PLL3, 12, 0, 0 },
1759 static struct clk_rcg sata_ref_src = {
1767 .parent_map = gcc_pxo_pll3_sata_map,
1769 .freq_tbl = clk_tbl_sata_ref,
1771 .enable_reg = 0x2c08,
1772 .enable_mask = BIT(7),
1773 .hw.init = &(struct clk_init_data){
1774 .name = "sata_ref_src",
1775 .parent_names = gcc_pxo_pll3,
1777 .ops = &clk_rcg_ops,
1778 .flags = CLK_SET_RATE_GATE,
1783 static struct clk_branch sata_rxoob_clk = {
1787 .enable_reg = 0x2c0c,
1788 .enable_mask = BIT(4),
1789 .hw.init = &(struct clk_init_data){
1790 .name = "sata_rxoob_clk",
1791 .parent_names = (const char *[]){ "sata_ref_src" },
1793 .ops = &clk_branch_ops,
1794 .flags = CLK_SET_RATE_PARENT,
1799 static struct clk_branch sata_pmalive_clk = {
1803 .enable_reg = 0x2c10,
1804 .enable_mask = BIT(4),
1805 .hw.init = &(struct clk_init_data){
1806 .name = "sata_pmalive_clk",
1807 .parent_names = (const char *[]){ "sata_ref_src" },
1809 .ops = &clk_branch_ops,
1810 .flags = CLK_SET_RATE_PARENT,
1815 static struct clk_branch sata_phy_ref_clk = {
1819 .enable_reg = 0x2c14,
1820 .enable_mask = BIT(4),
1821 .hw.init = &(struct clk_init_data){
1822 .name = "sata_phy_ref_clk",
1823 .parent_names = (const char *[]){ "pxo" },
1825 .ops = &clk_branch_ops,
1830 static struct clk_branch sata_a_clk = {
1834 .enable_reg = 0x2c20,
1835 .enable_mask = BIT(4),
1836 .hw.init = &(struct clk_init_data){
1837 .name = "sata_a_clk",
1838 .ops = &clk_branch_ops,
1839 .flags = CLK_IS_ROOT,
1844 static struct clk_branch sata_h_clk = {
1848 .enable_reg = 0x2c00,
1849 .enable_mask = BIT(4),
1850 .hw.init = &(struct clk_init_data){
1851 .name = "sata_h_clk",
1852 .ops = &clk_branch_ops,
1853 .flags = CLK_IS_ROOT,
1858 static struct clk_branch sfab_sata_s_h_clk = {
1862 .enable_reg = 0x2480,
1863 .enable_mask = BIT(4),
1864 .hw.init = &(struct clk_init_data){
1865 .name = "sfab_sata_s_h_clk",
1866 .ops = &clk_branch_ops,
1867 .flags = CLK_IS_ROOT,
1872 static struct clk_branch sata_phy_cfg_clk = {
1876 .enable_reg = 0x2c40,
1877 .enable_mask = BIT(4),
1878 .hw.init = &(struct clk_init_data){
1879 .name = "sata_phy_cfg_clk",
1880 .ops = &clk_branch_ops,
1881 .flags = CLK_IS_ROOT,
1886 static const struct freq_tbl clk_tbl_usb30_master[] = {
1887 { 125000000, P_PLL0, 1, 5, 32 },
1891 static struct clk_rcg usb30_master_clk_src = {
1896 .mnctr_reset_bit = 7,
1897 .mnctr_mode_shift = 5,
1908 .parent_map = gcc_pxo_pll8_pll0,
1910 .freq_tbl = clk_tbl_usb30_master,
1912 .enable_reg = 0x3b2c,
1913 .enable_mask = BIT(11),
1914 .hw.init = &(struct clk_init_data){
1915 .name = "usb30_master_ref_src",
1916 .parent_names = gcc_pxo_pll8_pll0_map,
1918 .ops = &clk_rcg_ops,
1919 .flags = CLK_SET_RATE_GATE,
1924 static struct clk_branch usb30_0_branch_clk = {
1928 .enable_reg = 0x3b24,
1929 .enable_mask = BIT(4),
1930 .hw.init = &(struct clk_init_data){
1931 .name = "usb30_0_branch_clk",
1932 .parent_names = (const char *[]){ "usb30_master_ref_src", },
1934 .ops = &clk_branch_ops,
1935 .flags = CLK_SET_RATE_PARENT,
1940 static struct clk_branch usb30_1_branch_clk = {
1944 .enable_reg = 0x3b34,
1945 .enable_mask = BIT(4),
1946 .hw.init = &(struct clk_init_data){
1947 .name = "usb30_1_branch_clk",
1948 .parent_names = (const char *[]){ "usb30_master_ref_src", },
1950 .ops = &clk_branch_ops,
1951 .flags = CLK_SET_RATE_PARENT,
1956 static const struct freq_tbl clk_tbl_usb30_utmi[] = {
1957 { 60000000, P_PLL8, 1, 5, 32 },
1961 static struct clk_rcg usb30_utmi_clk = {
1966 .mnctr_reset_bit = 7,
1967 .mnctr_mode_shift = 5,
1978 .parent_map = gcc_pxo_pll8_pll0,
1980 .freq_tbl = clk_tbl_usb30_utmi,
1982 .enable_reg = 0x3b44,
1983 .enable_mask = BIT(11),
1984 .hw.init = &(struct clk_init_data){
1985 .name = "usb30_utmi_clk",
1986 .parent_names = gcc_pxo_pll8_pll0_map,
1988 .ops = &clk_rcg_ops,
1989 .flags = CLK_SET_RATE_GATE,
1994 static struct clk_branch usb30_0_utmi_clk_ctl = {
1998 .enable_reg = 0x3b48,
1999 .enable_mask = BIT(4),
2000 .hw.init = &(struct clk_init_data){
2001 .name = "usb30_0_utmi_clk_ctl",
2002 .parent_names = (const char *[]){ "usb30_utmi_clk", },
2004 .ops = &clk_branch_ops,
2005 .flags = CLK_SET_RATE_PARENT,
2010 static struct clk_branch usb30_1_utmi_clk_ctl = {
2014 .enable_reg = 0x3b4c,
2015 .enable_mask = BIT(4),
2016 .hw.init = &(struct clk_init_data){
2017 .name = "usb30_1_utmi_clk_ctl",
2018 .parent_names = (const char *[]){ "usb30_utmi_clk", },
2020 .ops = &clk_branch_ops,
2021 .flags = CLK_SET_RATE_PARENT,
2026 static const struct freq_tbl clk_tbl_usb[] = {
2027 { 60000000, P_PLL8, 1, 5, 32 },
2031 static struct clk_rcg usb_hs1_xcvr_clk_src = {
2036 .mnctr_reset_bit = 7,
2037 .mnctr_mode_shift = 5,
2048 .parent_map = gcc_pxo_pll8_pll0,
2050 .freq_tbl = clk_tbl_usb,
2052 .enable_reg = 0x2968,
2053 .enable_mask = BIT(11),
2054 .hw.init = &(struct clk_init_data){
2055 .name = "usb_hs1_xcvr_src",
2056 .parent_names = gcc_pxo_pll8_pll0_map,
2058 .ops = &clk_rcg_ops,
2059 .flags = CLK_SET_RATE_GATE,
2064 static struct clk_branch usb_hs1_xcvr_clk = {
2068 .enable_reg = 0x290c,
2069 .enable_mask = BIT(9),
2070 .hw.init = &(struct clk_init_data){
2071 .name = "usb_hs1_xcvr_clk",
2072 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
2074 .ops = &clk_branch_ops,
2075 .flags = CLK_SET_RATE_PARENT,
2080 static struct clk_branch usb_hs1_h_clk = {
2086 .enable_reg = 0x2900,
2087 .enable_mask = BIT(4),
2088 .hw.init = &(struct clk_init_data){
2089 .name = "usb_hs1_h_clk",
2090 .ops = &clk_branch_ops,
2091 .flags = CLK_IS_ROOT,
2096 static struct clk_rcg usb_fs1_xcvr_clk_src = {
2101 .mnctr_reset_bit = 7,
2102 .mnctr_mode_shift = 5,
2113 .parent_map = gcc_pxo_pll8_pll0,
2115 .freq_tbl = clk_tbl_usb,
2117 .enable_reg = 0x2968,
2118 .enable_mask = BIT(11),
2119 .hw.init = &(struct clk_init_data){
2120 .name = "usb_fs1_xcvr_src",
2121 .parent_names = gcc_pxo_pll8_pll0_map,
2123 .ops = &clk_rcg_ops,
2124 .flags = CLK_SET_RATE_GATE,
2129 static struct clk_branch usb_fs1_xcvr_clk = {
2133 .enable_reg = 0x2968,
2134 .enable_mask = BIT(9),
2135 .hw.init = &(struct clk_init_data){
2136 .name = "usb_fs1_xcvr_clk",
2137 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2139 .ops = &clk_branch_ops,
2140 .flags = CLK_SET_RATE_PARENT,
2145 static struct clk_branch usb_fs1_sys_clk = {
2149 .enable_reg = 0x296c,
2150 .enable_mask = BIT(4),
2151 .hw.init = &(struct clk_init_data){
2152 .name = "usb_fs1_sys_clk",
2153 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2155 .ops = &clk_branch_ops,
2156 .flags = CLK_SET_RATE_PARENT,
2161 static struct clk_branch usb_fs1_h_clk = {
2165 .enable_reg = 0x2960,
2166 .enable_mask = BIT(4),
2167 .hw.init = &(struct clk_init_data){
2168 .name = "usb_fs1_h_clk",
2169 .ops = &clk_branch_ops,
2170 .flags = CLK_IS_ROOT,
2175 static struct clk_branch ebi2_clk = {
2181 .enable_reg = 0x3b00,
2182 .enable_mask = BIT(4),
2183 .hw.init = &(struct clk_init_data){
2185 .ops = &clk_branch_ops,
2186 .flags = CLK_IS_ROOT,
2191 static struct clk_branch ebi2_aon_clk = {
2195 .enable_reg = 0x3b00,
2196 .enable_mask = BIT(8),
2197 .hw.init = &(struct clk_init_data){
2198 .name = "ebi2_always_on_clk",
2199 .ops = &clk_branch_ops,
2200 .flags = CLK_IS_ROOT,
2205 static struct clk_regmap *gcc_ipq806x_clks[] = {
2206 [PLL0] = &pll0.clkr,
2207 [PLL0_VOTE] = &pll0_vote,
2208 [PLL3] = &pll3.clkr,
2209 [PLL4_VOTE] = &pll4_vote,
2210 [PLL8] = &pll8.clkr,
2211 [PLL8_VOTE] = &pll8_vote,
2212 [PLL14] = &pll14.clkr,
2213 [PLL14_VOTE] = &pll14_vote,
2214 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2215 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2216 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2217 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2218 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2219 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2220 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2221 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2222 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2223 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2224 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2225 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2226 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2227 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2228 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2229 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2230 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2231 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2232 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2233 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2234 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2235 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2236 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2237 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2238 [GP0_SRC] = &gp0_src.clkr,
2239 [GP0_CLK] = &gp0_clk.clkr,
2240 [GP1_SRC] = &gp1_src.clkr,
2241 [GP1_CLK] = &gp1_clk.clkr,
2242 [GP2_SRC] = &gp2_src.clkr,
2243 [GP2_CLK] = &gp2_clk.clkr,
2244 [PMEM_A_CLK] = &pmem_clk.clkr,
2245 [PRNG_SRC] = &prng_src.clkr,
2246 [PRNG_CLK] = &prng_clk.clkr,
2247 [SDC1_SRC] = &sdc1_src.clkr,
2248 [SDC1_CLK] = &sdc1_clk.clkr,
2249 [SDC3_SRC] = &sdc3_src.clkr,
2250 [SDC3_CLK] = &sdc3_clk.clkr,
2251 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2252 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2253 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
2254 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2255 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2256 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2257 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2258 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2259 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2260 [TSIF_H_CLK] = &tsif_h_clk.clkr,
2261 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2262 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2263 [ADM0_CLK] = &adm0_clk.clkr,
2264 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2265 [PCIE_A_CLK] = &pcie_a_clk.clkr,
2266 [PCIE_AUX_CLK] = &pcie_aux_clk.clkr,
2267 [PCIE_H_CLK] = &pcie_h_clk.clkr,
2268 [PCIE_PHY_CLK] = &pcie_phy_clk.clkr,
2269 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
2270 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2271 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2272 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2273 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2274 [SATA_H_CLK] = &sata_h_clk.clkr,
2275 [SATA_CLK_SRC] = &sata_ref_src.clkr,
2276 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
2277 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
2278 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
2279 [SATA_A_CLK] = &sata_a_clk.clkr,
2280 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
2281 [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr,
2282 [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr,
2283 [PCIE_1_A_CLK] = &pcie1_a_clk.clkr,
2284 [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr,
2285 [PCIE_1_H_CLK] = &pcie1_h_clk.clkr,
2286 [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr,
2287 [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr,
2288 [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr,
2289 [PCIE_2_A_CLK] = &pcie2_a_clk.clkr,
2290 [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr,
2291 [PCIE_2_H_CLK] = &pcie2_h_clk.clkr,
2292 [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr,
2293 [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr,
2294 [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr,
2295 [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr,
2296 [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr,
2297 [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr,
2298 [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr,
2299 [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr,
2300 [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr,
2301 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2302 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr,
2303 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2304 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2305 [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
2306 [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
2307 [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
2308 [EBI2_CLK] = &ebi2_clk.clkr,
2309 [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
2312 static const struct qcom_reset_map gcc_ipq806x_resets[] = {
2313 [QDSS_STM_RESET] = { 0x2060, 6 },
2314 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2315 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2316 [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
2317 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
2318 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
2319 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2320 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2321 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
2322 [ADM0_C2_RESET] = { 0x220c, 4 },
2323 [ADM0_C1_RESET] = { 0x220c, 3 },
2324 [ADM0_C0_RESET] = { 0x220c, 2 },
2325 [ADM0_PBUS_RESET] = { 0x220c, 1 },
2326 [ADM0_RESET] = { 0x220c, 0 },
2327 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
2328 [QDSS_POR_RESET] = { 0x2260, 4 },
2329 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
2330 [QDSS_HRESET_RESET] = { 0x2260, 2 },
2331 [QDSS_AXI_RESET] = { 0x2260, 1 },
2332 [QDSS_DBG_RESET] = { 0x2260, 0 },
2333 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
2334 [SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
2335 [PCIE_EXT_RESET] = { 0x22dc, 6 },
2336 [PCIE_PHY_RESET] = { 0x22dc, 5 },
2337 [PCIE_PCI_RESET] = { 0x22dc, 4 },
2338 [PCIE_POR_RESET] = { 0x22dc, 3 },
2339 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
2340 [PCIE_ACLK_RESET] = { 0x22dc, 0 },
2341 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
2342 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2343 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2344 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2345 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
2346 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2347 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2348 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2349 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2350 [DFAB_ARB0_RESET] = { 0x2560, 7 },
2351 [DFAB_ARB1_RESET] = { 0x2564, 7 },
2352 [PPSS_PROC_RESET] = { 0x2594, 1 },
2353 [PPSS_RESET] = { 0x2594, 0 },
2354 [DMA_BAM_RESET] = { 0x25c0, 7 },
2355 [SPS_TIC_H_RESET] = { 0x2600, 7 },
2356 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2357 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2358 [TSIF_H_RESET] = { 0x2700, 7 },
2359 [CE1_H_RESET] = { 0x2720, 7 },
2360 [CE1_CORE_RESET] = { 0x2724, 7 },
2361 [CE1_SLEEP_RESET] = { 0x2728, 7 },
2362 [CE2_H_RESET] = { 0x2740, 7 },
2363 [CE2_CORE_RESET] = { 0x2744, 7 },
2364 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2365 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2366 [RPM_PROC_RESET] = { 0x27c0, 7 },
2367 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2368 [SDC1_RESET] = { 0x2830, 0 },
2369 [SDC2_RESET] = { 0x2850, 0 },
2370 [SDC3_RESET] = { 0x2870, 0 },
2371 [SDC4_RESET] = { 0x2890, 0 },
2372 [USB_HS1_RESET] = { 0x2910, 0 },
2373 [USB_HSIC_RESET] = { 0x2934, 0 },
2374 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2375 [USB_FS1_RESET] = { 0x2974, 0 },
2376 [GSBI1_RESET] = { 0x29dc, 0 },
2377 [GSBI2_RESET] = { 0x29fc, 0 },
2378 [GSBI3_RESET] = { 0x2a1c, 0 },
2379 [GSBI4_RESET] = { 0x2a3c, 0 },
2380 [GSBI5_RESET] = { 0x2a5c, 0 },
2381 [GSBI6_RESET] = { 0x2a7c, 0 },
2382 [GSBI7_RESET] = { 0x2a9c, 0 },
2383 [SPDM_RESET] = { 0x2b6c, 0 },
2384 [SEC_CTRL_RESET] = { 0x2b80, 7 },
2385 [TLMM_H_RESET] = { 0x2ba0, 7 },
2386 [SFAB_SATA_M_RESET] = { 0x2c18, 0 },
2387 [SATA_RESET] = { 0x2c1c, 0 },
2388 [TSSC_RESET] = { 0x2ca0, 7 },
2389 [PDM_RESET] = { 0x2cc0, 12 },
2390 [MPM_H_RESET] = { 0x2da0, 7 },
2391 [MPM_RESET] = { 0x2da4, 0 },
2392 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2393 [PRNG_RESET] = { 0x2e80, 12 },
2394 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
2395 [SFAB_CE3_S_RESET] = { 0x36c8, 0 },
2396 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
2397 [PCIE_1_M_RESET] = { 0x3a98, 1 },
2398 [PCIE_1_S_RESET] = { 0x3a98, 0 },
2399 [PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
2400 [PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
2401 [PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
2402 [PCIE_1_POR_RESET] = { 0x3a9c, 3 },
2403 [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
2404 [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
2405 [PCIE_2_M_RESET] = { 0x3ad8, 1 },
2406 [PCIE_2_S_RESET] = { 0x3ad8, 0 },
2407 [PCIE_2_EXT_RESET] = { 0x3adc, 6 },
2408 [PCIE_2_PHY_RESET] = { 0x3adc, 5 },
2409 [PCIE_2_PCI_RESET] = { 0x3adc, 4 },
2410 [PCIE_2_POR_RESET] = { 0x3adc, 3 },
2411 [PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
2412 [PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
2413 [SFAB_USB30_S_RESET] = { 0x3b54, 1 },
2414 [SFAB_USB30_M_RESET] = { 0x3b54, 0 },
2415 [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
2416 [USB30_0_MASTER_RESET] = { 0x3b50, 4 },
2417 [USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
2418 [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
2419 [USB30_0_POWERON_RESET] = { 0x3b50, 1 },
2420 [USB30_0_PHY_RESET] = { 0x3b50, 0 },
2421 [USB30_1_MASTER_RESET] = { 0x3b58, 4 },
2422 [USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
2423 [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
2424 [USB30_1_POWERON_RESET] = { 0x3b58, 1 },
2425 [USB30_1_PHY_RESET] = { 0x3b58, 0 },
2426 [NSSFB0_RESET] = { 0x3b60, 6 },
2427 [NSSFB1_RESET] = { 0x3b60, 7 },
2430 static const struct regmap_config gcc_ipq806x_regmap_config = {
2434 .max_register = 0x3e40,
2438 static const struct qcom_cc_desc gcc_ipq806x_desc = {
2439 .config = &gcc_ipq806x_regmap_config,
2440 .clks = gcc_ipq806x_clks,
2441 .num_clks = ARRAY_SIZE(gcc_ipq806x_clks),
2442 .resets = gcc_ipq806x_resets,
2443 .num_resets = ARRAY_SIZE(gcc_ipq806x_resets),
2446 static const struct of_device_id gcc_ipq806x_match_table[] = {
2447 { .compatible = "qcom,gcc-ipq8064" },
2450 MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);
2452 static int gcc_ipq806x_probe(struct platform_device *pdev)
2455 struct device *dev = &pdev->dev;
2457 /* Temporary until RPM clocks supported */
2458 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000);
2460 return PTR_ERR(clk);
2462 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 25000000);
2464 return PTR_ERR(clk);
2466 return qcom_cc_probe(pdev, &gcc_ipq806x_desc);
2469 static int gcc_ipq806x_remove(struct platform_device *pdev)
2471 qcom_cc_remove(pdev);
2475 static struct platform_driver gcc_ipq806x_driver = {
2476 .probe = gcc_ipq806x_probe,
2477 .remove = gcc_ipq806x_remove,
2479 .name = "gcc-ipq806x",
2480 .of_match_table = gcc_ipq806x_match_table,
2484 static int __init gcc_ipq806x_init(void)
2486 return platform_driver_register(&gcc_ipq806x_driver);
2488 core_initcall(gcc_ipq806x_init);
2490 static void __exit gcc_ipq806x_exit(void)
2492 platform_driver_unregister(&gcc_ipq806x_driver);
2494 module_exit(gcc_ipq806x_exit);
2496 MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver");
2497 MODULE_LICENSE("GPL v2");
2498 MODULE_ALIAS("platform:gcc-ipq806x");