drivers/clk/qcom/gcc-ipq806x.c

   1 /*
   2  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
  26 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
  27
  28 #include "common.h"
  29 #include "clk-regmap.h"
  30 #include "clk-pll.h"
  31 #include "clk-rcg.h"
  32 #include "clk-branch.h"
  33 #include "reset.h"
  34
  35 static struct clk_pll pll0 = {
  36         .l_reg = 0x30c4,
  37         .m_reg = 0x30c8,
  38         .n_reg = 0x30cc,
  39         .config_reg = 0x30d4,
  40         .mode_reg = 0x30c0,
  41         .status_reg = 0x30d8,
  42         .status_bit = 16,
  43         .clkr.hw.init = &(struct clk_init_data){
  44                 .name = "pll0",
  45                 .parent_names = (const char *[]){ "pxo" },
  46                 .num_parents = 1,
  47                 .ops = &clk_pll_ops,
  48         },
  49 };
  50
  51 static struct clk_regmap pll0_vote = {
  52         .enable_reg = 0x34c0,
  53         .enable_mask = BIT(0),
  54         .hw.init = &(struct clk_init_data){
  55                 .name = "pll0_vote",
  56                 .parent_names = (const char *[]){ "pll0" },
  57                 .num_parents = 1,
  58                 .ops = &clk_pll_vote_ops,
  59         },
  60 };
  61
  62 static struct clk_pll pll3 = {
  63         .l_reg = 0x3164,
  64         .m_reg = 0x3168,
  65         .n_reg = 0x316c,
  66         .config_reg = 0x3174,
  67         .mode_reg = 0x3160,
  68         .status_reg = 0x3178,
  69         .status_bit = 16,
  70         .clkr.hw.init = &(struct clk_init_data){
  71                 .name = "pll3",
  72                 .parent_names = (const char *[]){ "pxo" },
  73                 .num_parents = 1,
  74                 .ops = &clk_pll_ops,
  75         },
  76 };
  77
  78 static struct clk_regmap pll4_vote = {
  79         .enable_reg = 0x34c0,
  80         .enable_mask = BIT(4),
  81         .hw.init = &(struct clk_init_data){
  82                 .name = "pll4_vote",
  83                 .parent_names = (const char *[]){ "pll4" },
  84                 .num_parents = 1,
  85                 .ops = &clk_pll_vote_ops,
  86         },
  87 };
  88
  89 static struct clk_pll pll8 = {
  90         .l_reg = 0x3144,
  91         .m_reg = 0x3148,
  92         .n_reg = 0x314c,
  93         .config_reg = 0x3154,
  94         .mode_reg = 0x3140,
  95         .status_reg = 0x3158,
  96         .status_bit = 16,
  97         .clkr.hw.init = &(struct clk_init_data){
  98                 .name = "pll8",
  99                 .parent_names = (const char *[]){ "pxo" },
 100                 .num_parents = 1,
 101                 .ops = &clk_pll_ops,
 102         },
 103 };
 104
 105 static struct clk_regmap pll8_vote = {
 106         .enable_reg = 0x34c0,
 107         .enable_mask = BIT(8),
 108         .hw.init = &(struct clk_init_data){
 109                 .name = "pll8_vote",
 110                 .parent_names = (const char *[]){ "pll8" },
 111                 .num_parents = 1,
 112                 .ops = &clk_pll_vote_ops,
 113         },
 114 };
 115
 116 static struct clk_pll pll14 = {
 117         .l_reg = 0x31c4,
 118         .m_reg = 0x31c8,
 119         .n_reg = 0x31cc,
 120         .config_reg = 0x31d4,
 121         .mode_reg = 0x31c0,
 122         .status_reg = 0x31d8,
 123         .status_bit = 16,
 124         .clkr.hw.init = &(struct clk_init_data){
 125                 .name = "pll14",
 126                 .parent_names = (const char *[]){ "pxo" },
 127                 .num_parents = 1,
 128                 .ops = &clk_pll_ops,
 129         },
 130 };
 131
 132 static struct clk_regmap pll14_vote = {
 133         .enable_reg = 0x34c0,
 134         .enable_mask = BIT(14),
 135         .hw.init = &(struct clk_init_data){
 136                 .name = "pll14_vote",
 137                 .parent_names = (const char *[]){ "pll14" },
 138                 .num_parents = 1,
 139                 .ops = &clk_pll_vote_ops,
 140         },
 141 };
 142
 143 #define P_PXO   0
 144 #define P_PLL8  1
 145 #define P_PLL3  1
 146 #define P_PLL0  2
 147 #define P_CXO   2
 148
 149 static const u8 gcc_pxo_pll8_map[] = {
 150         [P_PXO]         = 0,
 151         [P_PLL8]        = 3,
 152 };
 153
 154 static const char *gcc_pxo_pll8[] = {
 155         "pxo",
 156         "pll8_vote",
 157 };
 158
 159 static const u8 gcc_pxo_pll8_cxo_map[] = {
 160         [P_PXO]         = 0,
 161         [P_PLL8]        = 3,
 162         [P_CXO]         = 5,
 163 };
 164
 165 static const char *gcc_pxo_pll8_cxo[] = {
 166         "pxo",
 167         "pll8_vote",
 168         "cxo",
 169 };
 170
 171 static const u8 gcc_pxo_pll3_map[] = {
 172         [P_PXO]         = 0,
 173         [P_PLL3]        = 1,
 174 };
 175
 176 static const u8 gcc_pxo_pll3_sata_map[] = {
 177         [P_PXO]         = 0,
 178         [P_PLL3]        = 6,
 179 };
 180
 181 static const char *gcc_pxo_pll3[] = {
 182         "pxo",
 183         "pll3",
 184 };
 185
 186 static const u8 gcc_pxo_pll8_pll0[] = {
 187         [P_PXO]         = 0,
 188         [P_PLL8]        = 3,
 189         [P_PLL0]        = 2,
 190 };
 191
 192 static const char *gcc_pxo_pll8_pll0_map[] = {
 193         "pxo",
 194         "pll8_vote",
 195         "pll0_vote",
 196 };
 197
 198 static struct freq_tbl clk_tbl_gsbi_uart[] = {
 199         {  1843200, P_PLL8, 2,  6, 625 },
 200         {  3686400, P_PLL8, 2, 12, 625 },
 201         {  7372800, P_PLL8, 2, 24, 625 },
 202         { 14745600, P_PLL8, 2, 48, 625 },
 203         { 16000000, P_PLL8, 4,  1,   6 },
 204         { 24000000, P_PLL8, 4,  1,   4 },
 205         { 32000000, P_PLL8, 4,  1,   3 },
 206         { 40000000, P_PLL8, 1,  5,  48 },
 207         { 46400000, P_PLL8, 1, 29, 240 },
 208         { 48000000, P_PLL8, 4,  1,   2 },
 209         { 51200000, P_PLL8, 1,  2,  15 },
 210         { 56000000, P_PLL8, 1,  7,  48 },
 211         { 58982400, P_PLL8, 1, 96, 625 },
 212         { 64000000, P_PLL8, 2,  1,   3 },
 213         { }
 214 };
 215
 216 static struct clk_rcg gsbi1_uart_src = {
 217         .ns_reg = 0x29d4,
 218         .md_reg = 0x29d0,
 219         .mn = {
 220                 .mnctr_en_bit = 8,
 221                 .mnctr_reset_bit = 7,
 222                 .mnctr_mode_shift = 5,
 223                 .n_val_shift = 16,
 224                 .m_val_shift = 16,
 225                 .width = 16,
 226         },
 227         .p = {
 228                 .pre_div_shift = 3,
 229                 .pre_div_width = 2,
 230         },
 231         .s = {
 232                 .src_sel_shift = 0,
 233                 .parent_map = gcc_pxo_pll8_map,
 234         },
 235         .freq_tbl = clk_tbl_gsbi_uart,
 236         .clkr = {
 237                 .enable_reg = 0x29d4,
 238                 .enable_mask = BIT(11),
 239                 .hw.init = &(struct clk_init_data){
 240                         .name = "gsbi1_uart_src",
 241                         .parent_names = gcc_pxo_pll8,
 242                         .num_parents = 2,
 243                         .ops = &clk_rcg_ops,
 244                         .flags = CLK_SET_PARENT_GATE,
 245                 },
 246         },
 247 };
 248
 249 static struct clk_branch gsbi1_uart_clk = {
 250         .halt_reg = 0x2fcc,
 251         .halt_bit = 12,
 252         .clkr = {
 253                 .enable_reg = 0x29d4,
 254                 .enable_mask = BIT(9),
 255                 .hw.init = &(struct clk_init_data){
 256                         .name = "gsbi1_uart_clk",
 257                         .parent_names = (const char *[]){
 258                                 "gsbi1_uart_src",
 259                         },
 260                         .num_parents = 1,
 261                         .ops = &clk_branch_ops,
 262                         .flags = CLK_SET_RATE_PARENT,
 263                 },
 264         },
 265 };
 266
 267 static struct clk_rcg gsbi2_uart_src = {
 268         .ns_reg = 0x29f4,
 269         .md_reg = 0x29f0,
 270         .mn = {
 271                 .mnctr_en_bit = 8,
 272                 .mnctr_reset_bit = 7,
 273                 .mnctr_mode_shift = 5,
 274                 .n_val_shift = 16,
 275                 .m_val_shift = 16,
 276                 .width = 16,
 277         },
 278         .p = {
 279                 .pre_div_shift = 3,
 280                 .pre_div_width = 2,
 281         },
 282         .s = {
 283                 .src_sel_shift = 0,
 284                 .parent_map = gcc_pxo_pll8_map,
 285         },
 286         .freq_tbl = clk_tbl_gsbi_uart,
 287         .clkr = {
 288                 .enable_reg = 0x29f4,
 289                 .enable_mask = BIT(11),
 290                 .hw.init = &(struct clk_init_data){
 291                         .name = "gsbi2_uart_src",
 292                         .parent_names = gcc_pxo_pll8,
 293                         .num_parents = 2,
 294                         .ops = &clk_rcg_ops,
 295                         .flags = CLK_SET_PARENT_GATE,
 296                 },
 297         },
 298 };
 299
 300 static struct clk_branch gsbi2_uart_clk = {
 301         .halt_reg = 0x2fcc,
 302         .halt_bit = 8,
 303         .clkr = {
 304                 .enable_reg = 0x29f4,
 305                 .enable_mask = BIT(9),
 306                 .hw.init = &(struct clk_init_data){
 307                         .name = "gsbi2_uart_clk",
 308                         .parent_names = (const char *[]){
 309                                 "gsbi2_uart_src",
 310                         },
 311                         .num_parents = 1,
 312                         .ops = &clk_branch_ops,
 313                         .flags = CLK_SET_RATE_PARENT,
 314                 },
 315         },
 316 };
 317
 318 static struct clk_rcg gsbi4_uart_src = {
 319         .ns_reg = 0x2a34,
 320         .md_reg = 0x2a30,
 321         .mn = {
 322                 .mnctr_en_bit = 8,
 323                 .mnctr_reset_bit = 7,
 324                 .mnctr_mode_shift = 5,
 325                 .n_val_shift = 16,
 326                 .m_val_shift = 16,
 327                 .width = 16,
 328         },
 329         .p = {
 330                 .pre_div_shift = 3,
 331                 .pre_div_width = 2,
 332         },
 333         .s = {
 334                 .src_sel_shift = 0,
 335                 .parent_map = gcc_pxo_pll8_map,
 336         },
 337         .freq_tbl = clk_tbl_gsbi_uart,
 338         .clkr = {
 339                 .enable_reg = 0x2a34,
 340                 .enable_mask = BIT(11),
 341                 .hw.init = &(struct clk_init_data){
 342                         .name = "gsbi4_uart_src",
 343                         .parent_names = gcc_pxo_pll8,
 344                         .num_parents = 2,
 345                         .ops = &clk_rcg_ops,
 346                         .flags = CLK_SET_PARENT_GATE,
 347                 },
 348         },
 349 };
 350
 351 static struct clk_branch gsbi4_uart_clk = {
 352         .halt_reg = 0x2fd0,
 353         .halt_bit = 26,
 354         .clkr = {
 355                 .enable_reg = 0x2a34,
 356                 .enable_mask = BIT(9),
 357                 .hw.init = &(struct clk_init_data){
 358                         .name = "gsbi4_uart_clk",
 359                         .parent_names = (const char *[]){
 360                                 "gsbi4_uart_src",
 361                         },
 362                         .num_parents = 1,
 363                         .ops = &clk_branch_ops,
 364                         .flags = CLK_SET_RATE_PARENT,
 365                 },
 366         },
 367 };
 368
 369 static struct clk_rcg gsbi5_uart_src = {
 370         .ns_reg = 0x2a54,
 371         .md_reg = 0x2a50,
 372         .mn = {
 373                 .mnctr_en_bit = 8,
 374                 .mnctr_reset_bit = 7,
 375                 .mnctr_mode_shift = 5,
 376                 .n_val_shift = 16,
 377                 .m_val_shift = 16,
 378                 .width = 16,
 379         },
 380         .p = {
 381                 .pre_div_shift = 3,
 382                 .pre_div_width = 2,
 383         },
 384         .s = {
 385                 .src_sel_shift = 0,
 386                 .parent_map = gcc_pxo_pll8_map,
 387         },
 388         .freq_tbl = clk_tbl_gsbi_uart,
 389         .clkr = {
 390                 .enable_reg = 0x2a54,
 391                 .enable_mask = BIT(11),
 392                 .hw.init = &(struct clk_init_data){
 393                         .name = "gsbi5_uart_src",
 394                         .parent_names = gcc_pxo_pll8,
 395                         .num_parents = 2,
 396                         .ops = &clk_rcg_ops,
 397                         .flags = CLK_SET_PARENT_GATE,
 398                 },
 399         },
 400 };
 401
 402 static struct clk_branch gsbi5_uart_clk = {
 403         .halt_reg = 0x2fd0,
 404         .halt_bit = 22,
 405         .clkr = {
 406                 .enable_reg = 0x2a54,
 407                 .enable_mask = BIT(9),
 408                 .hw.init = &(struct clk_init_data){
 409                         .name = "gsbi5_uart_clk",
 410                         .parent_names = (const char *[]){
 411                                 "gsbi5_uart_src",
 412                         },
 413                         .num_parents = 1,
 414                         .ops = &clk_branch_ops,
 415                         .flags = CLK_SET_RATE_PARENT,
 416                 },
 417         },
 418 };
 419
 420 static struct clk_rcg gsbi6_uart_src = {
 421         .ns_reg = 0x2a74,
 422         .md_reg = 0x2a70,
 423         .mn = {
 424                 .mnctr_en_bit = 8,
 425                 .mnctr_reset_bit = 7,
 426                 .mnctr_mode_shift = 5,
 427                 .n_val_shift = 16,
 428                 .m_val_shift = 16,
 429                 .width = 16,
 430         },
 431         .p = {
 432                 .pre_div_shift = 3,
 433                 .pre_div_width = 2,
 434         },
 435         .s = {
 436                 .src_sel_shift = 0,
 437                 .parent_map = gcc_pxo_pll8_map,
 438         },
 439         .freq_tbl = clk_tbl_gsbi_uart,
 440         .clkr = {
 441                 .enable_reg = 0x2a74,
 442                 .enable_mask = BIT(11),
 443                 .hw.init = &(struct clk_init_data){
 444                         .name = "gsbi6_uart_src",
 445                         .parent_names = gcc_pxo_pll8,
 446                         .num_parents = 2,
 447                         .ops = &clk_rcg_ops,
 448                         .flags = CLK_SET_PARENT_GATE,
 449                 },
 450         },
 451 };
 452
 453 static struct clk_branch gsbi6_uart_clk = {
 454         .halt_reg = 0x2fd0,
 455         .halt_bit = 18,
 456         .clkr = {
 457                 .enable_reg = 0x2a74,
 458                 .enable_mask = BIT(9),
 459                 .hw.init = &(struct clk_init_data){
 460                         .name = "gsbi6_uart_clk",
 461                         .parent_names = (const char *[]){
 462                                 "gsbi6_uart_src",
 463                         },
 464                         .num_parents = 1,
 465                         .ops = &clk_branch_ops,
 466                         .flags = CLK_SET_RATE_PARENT,
 467                 },
 468         },
 469 };
 470
 471 static struct clk_rcg gsbi7_uart_src = {
 472         .ns_reg = 0x2a94,
 473         .md_reg = 0x2a90,
 474         .mn = {
 475                 .mnctr_en_bit = 8,
 476                 .mnctr_reset_bit = 7,
 477                 .mnctr_mode_shift = 5,
 478                 .n_val_shift = 16,
 479                 .m_val_shift = 16,
 480                 .width = 16,
 481         },
 482         .p = {
 483                 .pre_div_shift = 3,
 484                 .pre_div_width = 2,
 485         },
 486         .s = {
 487                 .src_sel_shift = 0,
 488                 .parent_map = gcc_pxo_pll8_map,
 489         },
 490         .freq_tbl = clk_tbl_gsbi_uart,
 491         .clkr = {
 492                 .enable_reg = 0x2a94,
 493                 .enable_mask = BIT(11),
 494                 .hw.init = &(struct clk_init_data){
 495                         .name = "gsbi7_uart_src",
 496                         .parent_names = gcc_pxo_pll8,
 497                         .num_parents = 2,
 498                         .ops = &clk_rcg_ops,
 499                         .flags = CLK_SET_PARENT_GATE,
 500                 },
 501         },
 502 };
 503
 504 static struct clk_branch gsbi7_uart_clk = {
 505         .halt_reg = 0x2fd0,
 506         .halt_bit = 14,
 507         .clkr = {
 508                 .enable_reg = 0x2a94,
 509                 .enable_mask = BIT(9),
 510                 .hw.init = &(struct clk_init_data){
 511                         .name = "gsbi7_uart_clk",
 512                         .parent_names = (const char *[]){
 513                                 "gsbi7_uart_src",
 514                         },
 515                         .num_parents = 1,
 516                         .ops = &clk_branch_ops,
 517                         .flags = CLK_SET_RATE_PARENT,
 518                 },
 519         },
 520 };
 521
 522 static struct freq_tbl clk_tbl_gsbi_qup[] = {
 523         {  1100000, P_PXO,  1, 2, 49 },
 524         {  5400000, P_PXO,  1, 1,  5 },
 525         { 10800000, P_PXO,  1, 2,  5 },
 526         { 15060000, P_PLL8, 1, 2, 51 },
 527         { 24000000, P_PLL8, 4, 1,  4 },
 528         { 25600000, P_PLL8, 1, 1, 15 },
 529         { 27000000, P_PXO,  1, 0,  0 },
 530         { 48000000, P_PLL8, 4, 1,  2 },
 531         { 51200000, P_PLL8, 1, 2, 15 },
 532         { }
 533 };
 534
 535 static struct clk_rcg gsbi1_qup_src = {
 536         .ns_reg = 0x29cc,
 537         .md_reg = 0x29c8,
 538         .mn = {
 539                 .mnctr_en_bit = 8,
 540                 .mnctr_reset_bit = 7,
 541                 .mnctr_mode_shift = 5,
 542                 .n_val_shift = 16,
 543                 .m_val_shift = 16,
 544                 .width = 8,
 545         },
 546         .p = {
 547                 .pre_div_shift = 3,
 548                 .pre_div_width = 2,
 549         },
 550         .s = {
 551                 .src_sel_shift = 0,
 552                 .parent_map = gcc_pxo_pll8_map,
 553         },
 554         .freq_tbl = clk_tbl_gsbi_qup,
 555         .clkr = {
 556                 .enable_reg = 0x29cc,
 557                 .enable_mask = BIT(11),
 558                 .hw.init = &(struct clk_init_data){
 559                         .name = "gsbi1_qup_src",
 560                         .parent_names = gcc_pxo_pll8,
 561                         .num_parents = 2,
 562                         .ops = &clk_rcg_ops,
 563                         .flags = CLK_SET_PARENT_GATE,
 564                 },
 565         },
 566 };
 567
 568 static struct clk_branch gsbi1_qup_clk = {
 569         .halt_reg = 0x2fcc,
 570         .halt_bit = 11,
 571         .clkr = {
 572                 .enable_reg = 0x29cc,
 573                 .enable_mask = BIT(9),
 574                 .hw.init = &(struct clk_init_data){
 575                         .name = "gsbi1_qup_clk",
 576                         .parent_names = (const char *[]){ "gsbi1_qup_src" },
 577                         .num_parents = 1,
 578                         .ops = &clk_branch_ops,
 579                         .flags = CLK_SET_RATE_PARENT,
 580                 },
 581         },
 582 };
 583
 584 static struct clk_rcg gsbi2_qup_src = {
 585         .ns_reg = 0x29ec,
 586         .md_reg = 0x29e8,
 587         .mn = {
 588                 .mnctr_en_bit = 8,
 589                 .mnctr_reset_bit = 7,
 590                 .mnctr_mode_shift = 5,
 591                 .n_val_shift = 16,
 592                 .m_val_shift = 16,
 593                 .width = 8,
 594         },
 595         .p = {
 596                 .pre_div_shift = 3,
 597                 .pre_div_width = 2,
 598         },
 599         .s = {
 600                 .src_sel_shift = 0,
 601                 .parent_map = gcc_pxo_pll8_map,
 602         },
 603         .freq_tbl = clk_tbl_gsbi_qup,
 604         .clkr = {
 605                 .enable_reg = 0x29ec,
 606                 .enable_mask = BIT(11),
 607                 .hw.init = &(struct clk_init_data){
 608                         .name = "gsbi2_qup_src",
 609                         .parent_names = gcc_pxo_pll8,
 610                         .num_parents = 2,
 611                         .ops = &clk_rcg_ops,
 612                         .flags = CLK_SET_PARENT_GATE,
 613                 },
 614         },
 615 };
 616
 617 static struct clk_branch gsbi2_qup_clk = {
 618         .halt_reg = 0x2fcc,
 619         .halt_bit = 6,
 620         .clkr = {
 621                 .enable_reg = 0x29ec,
 622                 .enable_mask = BIT(9),
 623                 .hw.init = &(struct clk_init_data){
 624                         .name = "gsbi2_qup_clk",
 625                         .parent_names = (const char *[]){ "gsbi2_qup_src" },
 626                         .num_parents = 1,
 627                         .ops = &clk_branch_ops,
 628                         .flags = CLK_SET_RATE_PARENT,
 629                 },
 630         },
 631 };
 632
 633 static struct clk_rcg gsbi4_qup_src = {
 634         .ns_reg = 0x2a2c,
 635         .md_reg = 0x2a28,
 636         .mn = {
 637                 .mnctr_en_bit = 8,
 638                 .mnctr_reset_bit = 7,
 639                 .mnctr_mode_shift = 5,
 640                 .n_val_shift = 16,
 641                 .m_val_shift = 16,
 642                 .width = 8,
 643         },
 644         .p = {
 645                 .pre_div_shift = 3,
 646                 .pre_div_width = 2,
 647         },
 648         .s = {
 649                 .src_sel_shift = 0,
 650                 .parent_map = gcc_pxo_pll8_map,
 651         },
 652         .freq_tbl = clk_tbl_gsbi_qup,
 653         .clkr = {
 654                 .enable_reg = 0x2a2c,
 655                 .enable_mask = BIT(11),
 656                 .hw.init = &(struct clk_init_data){
 657                         .name = "gsbi4_qup_src",
 658                         .parent_names = gcc_pxo_pll8,
 659                         .num_parents = 2,
 660                         .ops = &clk_rcg_ops,
 661                         .flags = CLK_SET_PARENT_GATE,
 662                 },
 663         },
 664 };
 665
 666 static struct clk_branch gsbi4_qup_clk = {
 667         .halt_reg = 0x2fd0,
 668         .halt_bit = 24,
 669         .clkr = {
 670                 .enable_reg = 0x2a2c,
 671                 .enable_mask = BIT(9),
 672                 .hw.init = &(struct clk_init_data){
 673                         .name = "gsbi4_qup_clk",
 674                         .parent_names = (const char *[]){ "gsbi4_qup_src" },
 675                         .num_parents = 1,
 676                         .ops = &clk_branch_ops,
 677                         .flags = CLK_SET_RATE_PARENT,
 678                 },
 679         },
 680 };
 681
 682 static struct clk_rcg gsbi5_qup_src = {
 683         .ns_reg = 0x2a4c,
 684         .md_reg = 0x2a48,
 685         .mn = {
 686                 .mnctr_en_bit = 8,
 687                 .mnctr_reset_bit = 7,
 688                 .mnctr_mode_shift = 5,
 689                 .n_val_shift = 16,
 690                 .m_val_shift = 16,
 691                 .width = 8,
 692         },
 693         .p = {
 694                 .pre_div_shift = 3,
 695                 .pre_div_width = 2,
 696         },
 697         .s = {
 698                 .src_sel_shift = 0,
 699                 .parent_map = gcc_pxo_pll8_map,
 700         },
 701         .freq_tbl = clk_tbl_gsbi_qup,
 702         .clkr = {
 703                 .enable_reg = 0x2a4c,
 704                 .enable_mask = BIT(11),
 705                 .hw.init = &(struct clk_init_data){
 706                         .name = "gsbi5_qup_src",
 707                         .parent_names = gcc_pxo_pll8,
 708                         .num_parents = 2,
 709                         .ops = &clk_rcg_ops,
 710                         .flags = CLK_SET_PARENT_GATE,
 711                 },
 712         },
 713 };
 714
 715 static struct clk_branch gsbi5_qup_clk = {
 716         .halt_reg = 0x2fd0,
 717         .halt_bit = 20,
 718         .clkr = {
 719                 .enable_reg = 0x2a4c,
 720                 .enable_mask = BIT(9),
 721                 .hw.init = &(struct clk_init_data){
 722                         .name = "gsbi5_qup_clk",
 723                         .parent_names = (const char *[]){ "gsbi5_qup_src" },
 724                         .num_parents = 1,
 725                         .ops = &clk_branch_ops,
 726                         .flags = CLK_SET_RATE_PARENT,
 727                 },
 728         },
 729 };
 730
 731 static struct clk_rcg gsbi6_qup_src = {
 732         .ns_reg = 0x2a6c,
 733         .md_reg = 0x2a68,
 734         .mn = {
 735                 .mnctr_en_bit = 8,
 736                 .mnctr_reset_bit = 7,
 737                 .mnctr_mode_shift = 5,
 738                 .n_val_shift = 16,
 739                 .m_val_shift = 16,
 740                 .width = 8,
 741         },
 742         .p = {
 743                 .pre_div_shift = 3,
 744                 .pre_div_width = 2,
 745         },
 746         .s = {
 747                 .src_sel_shift = 0,
 748                 .parent_map = gcc_pxo_pll8_map,
 749         },
 750         .freq_tbl = clk_tbl_gsbi_qup,
 751         .clkr = {
 752                 .enable_reg = 0x2a6c,
 753                 .enable_mask = BIT(11),
 754                 .hw.init = &(struct clk_init_data){
 755                         .name = "gsbi6_qup_src",
 756                         .parent_names = gcc_pxo_pll8,
 757                         .num_parents = 2,
 758                         .ops = &clk_rcg_ops,
 759                         .flags = CLK_SET_PARENT_GATE,
 760                 },
 761         },
 762 };
 763
 764 static struct clk_branch gsbi6_qup_clk = {
 765         .halt_reg = 0x2fd0,
 766         .halt_bit = 16,
 767         .clkr = {
 768                 .enable_reg = 0x2a6c,
 769                 .enable_mask = BIT(9),
 770                 .hw.init = &(struct clk_init_data){
 771                         .name = "gsbi6_qup_clk",
 772                         .parent_names = (const char *[]){ "gsbi6_qup_src" },
 773                         .num_parents = 1,
 774                         .ops = &clk_branch_ops,
 775                         .flags = CLK_SET_RATE_PARENT,
 776                 },
 777         },
 778 };
 779
 780 static struct clk_rcg gsbi7_qup_src = {
 781         .ns_reg = 0x2a8c,
 782         .md_reg = 0x2a88,
 783         .mn = {
 784                 .mnctr_en_bit = 8,
 785                 .mnctr_reset_bit = 7,
 786                 .mnctr_mode_shift = 5,
 787                 .n_val_shift = 16,
 788                 .m_val_shift = 16,
 789                 .width = 8,
 790         },
 791         .p = {
 792                 .pre_div_shift = 3,
 793                 .pre_div_width = 2,
 794         },
 795         .s = {
 796                 .src_sel_shift = 0,
 797                 .parent_map = gcc_pxo_pll8_map,
 798         },
 799         .freq_tbl = clk_tbl_gsbi_qup,
 800         .clkr = {
 801                 .enable_reg = 0x2a8c,
 802                 .enable_mask = BIT(11),
 803                 .hw.init = &(struct clk_init_data){
 804                         .name = "gsbi7_qup_src",
 805                         .parent_names = gcc_pxo_pll8,
 806                         .num_parents = 2,
 807                         .ops = &clk_rcg_ops,
 808                         .flags = CLK_SET_PARENT_GATE,
 809                 },
 810         },
 811 };
 812
 813 static struct clk_branch gsbi7_qup_clk = {
 814         .halt_reg = 0x2fd0,
 815         .halt_bit = 12,
 816         .clkr = {
 817                 .enable_reg = 0x2a8c,
 818                 .enable_mask = BIT(9),
 819                 .hw.init = &(struct clk_init_data){
 820                         .name = "gsbi7_qup_clk",
 821                         .parent_names = (const char *[]){ "gsbi7_qup_src" },
 822                         .num_parents = 1,
 823                         .ops = &clk_branch_ops,
 824                         .flags = CLK_SET_RATE_PARENT,
 825                 },
 826         },
 827 };
 828
 829 static struct clk_branch gsbi1_h_clk = {
 830         .hwcg_reg = 0x29c0,
 831         .hwcg_bit = 6,
 832         .halt_reg = 0x2fcc,
 833         .halt_bit = 13,
 834         .clkr = {
 835                 .enable_reg = 0x29c0,
 836                 .enable_mask = BIT(4),
 837                 .hw.init = &(struct clk_init_data){
 838                         .name = "gsbi1_h_clk",
 839                         .ops = &clk_branch_ops,
 840                         .flags = CLK_IS_ROOT,
 841                 },
 842         },
 843 };
 844
 845 static struct clk_branch gsbi2_h_clk = {
 846         .hwcg_reg = 0x29e0,
 847         .hwcg_bit = 6,
 848         .halt_reg = 0x2fcc,
 849         .halt_bit = 9,
 850         .clkr = {
 851                 .enable_reg = 0x29e0,
 852                 .enable_mask = BIT(4),
 853                 .hw.init = &(struct clk_init_data){
 854                         .name = "gsbi2_h_clk",
 855                         .ops = &clk_branch_ops,
 856                         .flags = CLK_IS_ROOT,
 857                 },
 858         },
 859 };
 860
 861 static struct clk_branch gsbi4_h_clk = {
 862         .hwcg_reg = 0x2a20,
 863         .hwcg_bit = 6,
 864         .halt_reg = 0x2fd0,
 865         .halt_bit = 27,
 866         .clkr = {
 867                 .enable_reg = 0x2a20,
 868                 .enable_mask = BIT(4),
 869                 .hw.init = &(struct clk_init_data){
 870                         .name = "gsbi4_h_clk",
 871                         .ops = &clk_branch_ops,
 872                         .flags = CLK_IS_ROOT,
 873                 },
 874         },
 875 };
 876
 877 static struct clk_branch gsbi5_h_clk = {
 878         .hwcg_reg = 0x2a40,
 879         .hwcg_bit = 6,
 880         .halt_reg = 0x2fd0,
 881         .halt_bit = 23,
 882         .clkr = {
 883                 .enable_reg = 0x2a40,
 884                 .enable_mask = BIT(4),
 885                 .hw.init = &(struct clk_init_data){
 886                         .name = "gsbi5_h_clk",
 887                         .ops = &clk_branch_ops,
 888                         .flags = CLK_IS_ROOT,
 889                 },
 890         },
 891 };
 892
 893 static struct clk_branch gsbi6_h_clk = {
 894         .hwcg_reg = 0x2a60,
 895         .hwcg_bit = 6,
 896         .halt_reg = 0x2fd0,
 897         .halt_bit = 19,
 898         .clkr = {
 899                 .enable_reg = 0x2a60,
 900                 .enable_mask = BIT(4),
 901                 .hw.init = &(struct clk_init_data){
 902                         .name = "gsbi6_h_clk",
 903                         .ops = &clk_branch_ops,
 904                         .flags = CLK_IS_ROOT,
 905                 },
 906         },
 907 };
 908
 909 static struct clk_branch gsbi7_h_clk = {
 910         .hwcg_reg = 0x2a80,
 911         .hwcg_bit = 6,
 912         .halt_reg = 0x2fd0,
 913         .halt_bit = 15,
 914         .clkr = {
 915                 .enable_reg = 0x2a80,
 916                 .enable_mask = BIT(4),
 917                 .hw.init = &(struct clk_init_data){
 918                         .name = "gsbi7_h_clk",
 919                         .ops = &clk_branch_ops,
 920                         .flags = CLK_IS_ROOT,
 921                 },
 922         },
 923 };
 924
 925 static const struct freq_tbl clk_tbl_gp[] = {
 926         { 12500000, P_PXO,  2, 0, 0 },
 927         { 25000000, P_PXO,  1, 0, 0 },
 928         { 64000000, P_PLL8, 2, 1, 3 },
 929         { 76800000, P_PLL8, 1, 1, 5 },
 930         { 96000000, P_PLL8, 4, 0, 0 },
 931         { 128000000, P_PLL8, 3, 0, 0 },
 932         { 192000000, P_PLL8, 2, 0, 0 },
 933         { }
 934 };
 935
 936 static struct clk_rcg gp0_src = {
 937         .ns_reg = 0x2d24,
 938         .md_reg = 0x2d00,
 939         .mn = {
 940                 .mnctr_en_bit = 8,
 941                 .mnctr_reset_bit = 7,
 942                 .mnctr_mode_shift = 5,
 943                 .n_val_shift = 16,
 944                 .m_val_shift = 16,
 945                 .width = 8,
 946         },
 947         .p = {
 948                 .pre_div_shift = 3,
 949                 .pre_div_width = 2,
 950         },
 951         .s = {
 952                 .src_sel_shift = 0,
 953                 .parent_map = gcc_pxo_pll8_cxo_map,
 954         },
 955         .freq_tbl = clk_tbl_gp,
 956         .clkr = {
 957                 .enable_reg = 0x2d24,
 958                 .enable_mask = BIT(11),
 959                 .hw.init = &(struct clk_init_data){
 960                         .name = "gp0_src",
 961                         .parent_names = gcc_pxo_pll8_cxo,
 962                         .num_parents = 3,
 963                         .ops = &clk_rcg_ops,
 964                         .flags = CLK_SET_PARENT_GATE,
 965                 },
 966         }
 967 };
 968
 969 static struct clk_branch gp0_clk = {
 970         .halt_reg = 0x2fd8,
 971         .halt_bit = 7,
 972         .clkr = {
 973                 .enable_reg = 0x2d24,
 974                 .enable_mask = BIT(9),
 975                 .hw.init = &(struct clk_init_data){
 976                         .name = "gp0_clk",
 977                         .parent_names = (const char *[]){ "gp0_src" },
 978                         .num_parents = 1,
 979                         .ops = &clk_branch_ops,
 980                         .flags = CLK_SET_RATE_PARENT,
 981                 },
 982         },
 983 };
 984
 985 static struct clk_rcg gp1_src = {
 986         .ns_reg = 0x2d44,
 987         .md_reg = 0x2d40,
 988         .mn = {
 989                 .mnctr_en_bit = 8,
 990                 .mnctr_reset_bit = 7,
 991                 .mnctr_mode_shift = 5,
 992                 .n_val_shift = 16,
 993                 .m_val_shift = 16,
 994                 .width = 8,
 995         },
 996         .p = {
 997                 .pre_div_shift = 3,
 998                 .pre_div_width = 2,
 999         },
1000         .s = {
1001                 .src_sel_shift = 0,
1002                 .parent_map = gcc_pxo_pll8_cxo_map,
1003         },
1004         .freq_tbl = clk_tbl_gp,
1005         .clkr = {
1006                 .enable_reg = 0x2d44,
1007                 .enable_mask = BIT(11),
1008                 .hw.init = &(struct clk_init_data){
1009                         .name = "gp1_src",
1010                         .parent_names = gcc_pxo_pll8_cxo,
1011                         .num_parents = 3,
1012                         .ops = &clk_rcg_ops,
1013                         .flags = CLK_SET_RATE_GATE,
1014                 },
1015         }
1016 };
1017
1018 static struct clk_branch gp1_clk = {
1019         .halt_reg = 0x2fd8,
1020         .halt_bit = 6,
1021         .clkr = {
1022                 .enable_reg = 0x2d44,
1023                 .enable_mask = BIT(9),
1024                 .hw.init = &(struct clk_init_data){
1025                         .name = "gp1_clk",
1026                         .parent_names = (const char *[]){ "gp1_src" },
1027                         .num_parents = 1,
1028                         .ops = &clk_branch_ops,
1029                         .flags = CLK_SET_RATE_PARENT,
1030                 },
1031         },
1032 };
1033
1034 static struct clk_rcg gp2_src = {
1035         .ns_reg = 0x2d64,
1036         .md_reg = 0x2d60,
1037         .mn = {
1038                 .mnctr_en_bit = 8,
1039                 .mnctr_reset_bit = 7,
1040                 .mnctr_mode_shift = 5,
1041                 .n_val_shift = 16,
1042                 .m_val_shift = 16,
1043                 .width = 8,
1044         },
1045         .p = {
1046                 .pre_div_shift = 3,
1047                 .pre_div_width = 2,
1048         },
1049         .s = {
1050                 .src_sel_shift = 0,
1051                 .parent_map = gcc_pxo_pll8_cxo_map,
1052         },
1053         .freq_tbl = clk_tbl_gp,
1054         .clkr = {
1055                 .enable_reg = 0x2d64,
1056                 .enable_mask = BIT(11),
1057                 .hw.init = &(struct clk_init_data){
1058                         .name = "gp2_src",
1059                         .parent_names = gcc_pxo_pll8_cxo,
1060                         .num_parents = 3,
1061                         .ops = &clk_rcg_ops,
1062                         .flags = CLK_SET_RATE_GATE,
1063                 },
1064         }
1065 };
1066
1067 static struct clk_branch gp2_clk = {
1068         .halt_reg = 0x2fd8,
1069         .halt_bit = 5,
1070         .clkr = {
1071                 .enable_reg = 0x2d64,
1072                 .enable_mask = BIT(9),
1073                 .hw.init = &(struct clk_init_data){
1074                         .name = "gp2_clk",
1075                         .parent_names = (const char *[]){ "gp2_src" },
1076                         .num_parents = 1,
1077                         .ops = &clk_branch_ops,
1078                         .flags = CLK_SET_RATE_PARENT,
1079                 },
1080         },
1081 };
1082
1083 static struct clk_branch pmem_clk = {
1084         .hwcg_reg = 0x25a0,
1085         .hwcg_bit = 6,
1086         .halt_reg = 0x2fc8,
1087         .halt_bit = 20,
1088         .clkr = {
1089                 .enable_reg = 0x25a0,
1090                 .enable_mask = BIT(4),
1091                 .hw.init = &(struct clk_init_data){
1092                         .name = "pmem_clk",
1093                         .ops = &clk_branch_ops,
1094                         .flags = CLK_IS_ROOT,
1095                 },
1096         },
1097 };
1098
1099 static struct clk_rcg prng_src = {
1100         .ns_reg = 0x2e80,
1101         .p = {
1102                 .pre_div_shift = 3,
1103                 .pre_div_width = 4,
1104         },
1105         .s = {
1106                 .src_sel_shift = 0,
1107                 .parent_map = gcc_pxo_pll8_map,
1108         },
1109         .clkr = {
1110                 .hw.init = &(struct clk_init_data){
1111                         .name = "prng_src",
1112                         .parent_names = gcc_pxo_pll8,
1113                         .num_parents = 2,
1114                         .ops = &clk_rcg_ops,
1115                 },
1116         },
1117 };
1118
1119 static struct clk_branch prng_clk = {
1120         .halt_reg = 0x2fd8,
1121         .halt_check = BRANCH_HALT_VOTED,
1122         .halt_bit = 10,
1123         .clkr = {
1124                 .enable_reg = 0x3080,
1125                 .enable_mask = BIT(10),
1126                 .hw.init = &(struct clk_init_data){
1127                         .name = "prng_clk",
1128                         .parent_names = (const char *[]){ "prng_src" },
1129                         .num_parents = 1,
1130                         .ops = &clk_branch_ops,
1131                 },
1132         },
1133 };
1134
1135 static const struct freq_tbl clk_tbl_sdc[] = {
1136         {    200000, P_PXO,   2, 2, 125 },
1137         {    400000, P_PLL8,  4, 1, 240 },
1138         {  16000000, P_PLL8,  4, 1,   6 },
1139         {  17070000, P_PLL8,  1, 2,  45 },
1140         {  20210000, P_PLL8,  1, 1,  19 },
1141         {  24000000, P_PLL8,  4, 1,   4 },
1142         {  48000000, P_PLL8,  4, 1,   2 },
1143         {  64000000, P_PLL8,  3, 1,   2 },
1144         {  96000000, P_PLL8,  4, 0,   0 },
1145         { 192000000, P_PLL8,  2, 0,   0 },
1146         { }
1147 };
1148
1149 static struct clk_rcg sdc1_src = {
1150         .ns_reg = 0x282c,
1151         .md_reg = 0x2828,
1152         .mn = {
1153                 .mnctr_en_bit = 8,
1154                 .mnctr_reset_bit = 7,
1155                 .mnctr_mode_shift = 5,
1156                 .n_val_shift = 16,
1157                 .m_val_shift = 16,
1158                 .width = 8,
1159         },
1160         .p = {
1161                 .pre_div_shift = 3,
1162                 .pre_div_width = 2,
1163         },
1164         .s = {
1165                 .src_sel_shift = 0,
1166                 .parent_map = gcc_pxo_pll8_map,
1167         },
1168         .freq_tbl = clk_tbl_sdc,
1169         .clkr = {
1170                 .enable_reg = 0x282c,
1171                 .enable_mask = BIT(11),
1172                 .hw.init = &(struct clk_init_data){
1173                         .name = "sdc1_src",
1174                         .parent_names = gcc_pxo_pll8,
1175                         .num_parents = 2,
1176                         .ops = &clk_rcg_ops,
1177                         .flags = CLK_SET_RATE_GATE,
1178                 },
1179         }
1180 };
1181
1182 static struct clk_branch sdc1_clk = {
1183         .halt_reg = 0x2fc8,
1184         .halt_bit = 6,
1185         .clkr = {
1186                 .enable_reg = 0x282c,
1187                 .enable_mask = BIT(9),
1188                 .hw.init = &(struct clk_init_data){
1189                         .name = "sdc1_clk",
1190                         .parent_names = (const char *[]){ "sdc1_src" },
1191                         .num_parents = 1,
1192                         .ops = &clk_branch_ops,
1193                         .flags = CLK_SET_RATE_PARENT,
1194                 },
1195         },
1196 };
1197
1198 static struct clk_rcg sdc3_src = {
1199         .ns_reg = 0x286c,
1200         .md_reg = 0x2868,
1201         .mn = {
1202                 .mnctr_en_bit = 8,
1203                 .mnctr_reset_bit = 7,
1204                 .mnctr_mode_shift = 5,
1205                 .n_val_shift = 16,
1206                 .m_val_shift = 16,
1207                 .width = 8,
1208         },
1209         .p = {
1210                 .pre_div_shift = 3,
1211                 .pre_div_width = 2,
1212         },
1213         .s = {
1214                 .src_sel_shift = 0,
1215                 .parent_map = gcc_pxo_pll8_map,
1216         },
1217         .freq_tbl = clk_tbl_sdc,
1218         .clkr = {
1219                 .enable_reg = 0x286c,
1220                 .enable_mask = BIT(11),
1221                 .hw.init = &(struct clk_init_data){
1222                         .name = "sdc3_src",
1223                         .parent_names = gcc_pxo_pll8,
1224                         .num_parents = 2,
1225                         .ops = &clk_rcg_ops,
1226                         .flags = CLK_SET_RATE_GATE,
1227                 },
1228         }
1229 };
1230
1231 static struct clk_branch sdc3_clk = {
1232         .halt_reg = 0x2fc8,
1233         .halt_bit = 4,
1234         .clkr = {
1235                 .enable_reg = 0x286c,
1236                 .enable_mask = BIT(9),
1237                 .hw.init = &(struct clk_init_data){
1238                         .name = "sdc3_clk",
1239                         .parent_names = (const char *[]){ "sdc3_src" },
1240                         .num_parents = 1,
1241                         .ops = &clk_branch_ops,
1242                         .flags = CLK_SET_RATE_PARENT,
1243                 },
1244         },
1245 };
1246
1247 static struct clk_branch sdc1_h_clk = {
1248         .hwcg_reg = 0x2820,
1249         .hwcg_bit = 6,
1250         .halt_reg = 0x2fc8,
1251         .halt_bit = 11,
1252         .clkr = {
1253                 .enable_reg = 0x2820,
1254                 .enable_mask = BIT(4),
1255                 .hw.init = &(struct clk_init_data){
1256                         .name = "sdc1_h_clk",
1257                         .ops = &clk_branch_ops,
1258                         .flags = CLK_IS_ROOT,
1259                 },
1260         },
1261 };
1262
1263 static struct clk_branch sdc3_h_clk = {
1264         .hwcg_reg = 0x2860,
1265         .hwcg_bit = 6,
1266         .halt_reg = 0x2fc8,
1267         .halt_bit = 9,
1268         .clkr = {
1269                 .enable_reg = 0x2860,
1270                 .enable_mask = BIT(4),
1271                 .hw.init = &(struct clk_init_data){
1272                         .name = "sdc3_h_clk",
1273                         .ops = &clk_branch_ops,
1274                         .flags = CLK_IS_ROOT,
1275                 },
1276         },
1277 };
1278
1279 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1280         { 105000, P_PXO,  1, 1, 256 },
1281         { }
1282 };
1283
1284 static struct clk_rcg tsif_ref_src = {
1285         .ns_reg = 0x2710,
1286         .md_reg = 0x270c,
1287         .mn = {
1288                 .mnctr_en_bit = 8,
1289                 .mnctr_reset_bit = 7,
1290                 .mnctr_mode_shift = 5,
1291                 .n_val_shift = 16,
1292                 .m_val_shift = 16,
1293                 .width = 16,
1294         },
1295         .p = {
1296                 .pre_div_shift = 3,
1297                 .pre_div_width = 2,
1298         },
1299         .s = {
1300                 .src_sel_shift = 0,
1301                 .parent_map = gcc_pxo_pll8_map,
1302         },
1303         .freq_tbl = clk_tbl_tsif_ref,
1304         .clkr = {
1305                 .enable_reg = 0x2710,
1306                 .enable_mask = BIT(11),
1307                 .hw.init = &(struct clk_init_data){
1308                         .name = "tsif_ref_src",
1309                         .parent_names = gcc_pxo_pll8,
1310                         .num_parents = 2,
1311                         .ops = &clk_rcg_ops,
1312                         .flags = CLK_SET_RATE_GATE,
1313                 },
1314         }
1315 };
1316
1317 static struct clk_branch tsif_ref_clk = {
1318         .halt_reg = 0x2fd4,
1319         .halt_bit = 5,
1320         .clkr = {
1321                 .enable_reg = 0x2710,
1322                 .enable_mask = BIT(9),
1323                 .hw.init = &(struct clk_init_data){
1324                         .name = "tsif_ref_clk",
1325                         .parent_names = (const char *[]){ "tsif_ref_src" },
1326                         .num_parents = 1,
1327                         .ops = &clk_branch_ops,
1328                         .flags = CLK_SET_RATE_PARENT,
1329                 },
1330         },
1331 };
1332
1333 static struct clk_branch tsif_h_clk = {
1334         .hwcg_reg = 0x2700,
1335         .hwcg_bit = 6,
1336         .halt_reg = 0x2fd4,
1337         .halt_bit = 7,
1338         .clkr = {
1339                 .enable_reg = 0x2700,
1340                 .enable_mask = BIT(4),
1341                 .hw.init = &(struct clk_init_data){
1342                         .name = "tsif_h_clk",
1343                         .ops = &clk_branch_ops,
1344                         .flags = CLK_IS_ROOT,
1345                 },
1346         },
1347 };
1348
1349 static struct clk_branch dma_bam_h_clk = {
1350         .hwcg_reg = 0x25c0,
1351         .hwcg_bit = 6,
1352         .halt_reg = 0x2fc8,
1353         .halt_bit = 12,
1354         .clkr = {
1355                 .enable_reg = 0x25c0,
1356                 .enable_mask = BIT(4),
1357                 .hw.init = &(struct clk_init_data){
1358                         .name = "dma_bam_h_clk",
1359                         .ops = &clk_branch_ops,
1360                         .flags = CLK_IS_ROOT,
1361                 },
1362         },
1363 };
1364
1365 static struct clk_branch adm0_clk = {
1366         .halt_reg = 0x2fdc,
1367         .halt_check = BRANCH_HALT_VOTED,
1368         .halt_bit = 12,
1369         .clkr = {
1370                 .enable_reg = 0x3080,
1371                 .enable_mask = BIT(2),
1372                 .hw.init = &(struct clk_init_data){
1373                         .name = "adm0_clk",
1374                         .ops = &clk_branch_ops,
1375                         .flags = CLK_IS_ROOT,
1376                 },
1377         },
1378 };
1379
1380 static struct clk_branch adm0_pbus_clk = {
1381         .hwcg_reg = 0x2208,
1382         .hwcg_bit = 6,
1383         .halt_reg = 0x2fdc,
1384         .halt_check = BRANCH_HALT_VOTED,
1385         .halt_bit = 11,
1386         .clkr = {
1387                 .enable_reg = 0x3080,
1388                 .enable_mask = BIT(3),
1389                 .hw.init = &(struct clk_init_data){
1390                         .name = "adm0_pbus_clk",
1391                         .ops = &clk_branch_ops,
1392                         .flags = CLK_IS_ROOT,
1393                 },
1394         },
1395 };
1396
1397 static struct clk_branch pmic_arb0_h_clk = {
1398         .halt_reg = 0x2fd8,
1399         .halt_check = BRANCH_HALT_VOTED,
1400         .halt_bit = 22,
1401         .clkr = {
1402                 .enable_reg = 0x3080,
1403                 .enable_mask = BIT(8),
1404                 .hw.init = &(struct clk_init_data){
1405                         .name = "pmic_arb0_h_clk",
1406                         .ops = &clk_branch_ops,
1407                         .flags = CLK_IS_ROOT,
1408                 },
1409         },
1410 };
1411
1412 static struct clk_branch pmic_arb1_h_clk = {
1413         .halt_reg = 0x2fd8,
1414         .halt_check = BRANCH_HALT_VOTED,
1415         .halt_bit = 21,
1416         .clkr = {
1417                 .enable_reg = 0x3080,
1418                 .enable_mask = BIT(9),
1419                 .hw.init = &(struct clk_init_data){
1420                         .name = "pmic_arb1_h_clk",
1421                         .ops = &clk_branch_ops,
1422                         .flags = CLK_IS_ROOT,
1423                 },
1424         },
1425 };
1426
1427 static struct clk_branch pmic_ssbi2_clk = {
1428         .halt_reg = 0x2fd8,
1429         .halt_check = BRANCH_HALT_VOTED,
1430         .halt_bit = 23,
1431         .clkr = {
1432                 .enable_reg = 0x3080,
1433                 .enable_mask = BIT(7),
1434                 .hw.init = &(struct clk_init_data){
1435                         .name = "pmic_ssbi2_clk",
1436                         .ops = &clk_branch_ops,
1437                         .flags = CLK_IS_ROOT,
1438                 },
1439         },
1440 };
1441
1442 static struct clk_branch rpm_msg_ram_h_clk = {
1443         .hwcg_reg = 0x27e0,
1444         .hwcg_bit = 6,
1445         .halt_reg = 0x2fd8,
1446         .halt_check = BRANCH_HALT_VOTED,
1447         .halt_bit = 12,
1448         .clkr = {
1449                 .enable_reg = 0x3080,
1450                 .enable_mask = BIT(6),
1451                 .hw.init = &(struct clk_init_data){
1452                         .name = "rpm_msg_ram_h_clk",
1453                         .ops = &clk_branch_ops,
1454                         .flags = CLK_IS_ROOT,
1455                 },
1456         },
1457 };
1458
1459 static const struct freq_tbl clk_tbl_pcie_ref[] = {
1460         { 100000000, P_PLL3,  12, 0, 0 },
1461         { }
1462 };
1463
1464 static struct clk_rcg pcie_ref_src = {
1465         .ns_reg = 0x3860,
1466         .p = {
1467                 .pre_div_shift = 3,
1468                 .pre_div_width = 4,
1469         },
1470         .s = {
1471                 .src_sel_shift = 0,
1472                 .parent_map = gcc_pxo_pll3_map,
1473         },
1474         .freq_tbl = clk_tbl_pcie_ref,
1475         .clkr = {
1476                 .enable_reg = 0x3860,
1477                 .enable_mask = BIT(11),
1478                 .hw.init = &(struct clk_init_data){
1479                         .name = "pcie_ref_src",
1480                         .parent_names = gcc_pxo_pll3,
1481                         .num_parents = 2,
1482                         .ops = &clk_rcg_ops,
1483                         .flags = CLK_SET_RATE_GATE,
1484                 },
1485         },
1486 };
1487
1488 static struct clk_branch pcie_ref_src_clk = {
1489         .halt_reg = 0x2fdc,
1490         .halt_bit = 30,
1491         .clkr = {
1492                 .enable_reg = 0x3860,
1493                 .enable_mask = BIT(9),
1494                 .hw.init = &(struct clk_init_data){
1495                         .name = "pcie_ref_src_clk",
1496                         .parent_names = (const char *[]){ "pcie_ref_src" },
1497                         .num_parents = 1,
1498                         .ops = &clk_branch_ops,
1499                         .flags = CLK_SET_RATE_PARENT,
1500                 },
1501         },
1502 };
1503
1504 static struct clk_branch pcie_a_clk = {
1505         .halt_reg = 0x2fc0,
1506         .halt_bit = 13,
1507         .clkr = {
1508                 .enable_reg = 0x22c0,
1509                 .enable_mask = BIT(4),
1510                 .hw.init = &(struct clk_init_data){
1511                         .name = "pcie_a_clk",
1512                         .ops = &clk_branch_ops,
1513                         .flags = CLK_IS_ROOT,
1514                 },
1515         },
1516 };
1517
1518 static struct clk_branch pcie_aux_clk = {
1519         .halt_reg = 0x2fdc,
1520         .halt_bit = 31,
1521         .clkr = {
1522                 .enable_reg = 0x22c8,
1523                 .enable_mask = BIT(4),
1524                 .hw.init = &(struct clk_init_data){
1525                         .name = "pcie_aux_clk",
1526                         .ops = &clk_branch_ops,
1527                         .flags = CLK_IS_ROOT,
1528                 },
1529         },
1530 };
1531
1532 static struct clk_branch pcie_h_clk = {
1533         .halt_reg = 0x2fd4,
1534         .halt_bit = 8,
1535         .clkr = {
1536                 .enable_reg = 0x22cc,
1537                 .enable_mask = BIT(4),
1538                 .hw.init = &(struct clk_init_data){
1539                         .name = "pcie_h_clk",
1540                         .ops = &clk_branch_ops,
1541                         .flags = CLK_IS_ROOT,
1542                 },
1543         },
1544 };
1545
1546 static struct clk_branch pcie_phy_clk = {
1547         .halt_reg = 0x2fdc,
1548         .halt_bit = 29,
1549         .clkr = {
1550                 .enable_reg = 0x22d0,
1551                 .enable_mask = BIT(4),
1552                 .hw.init = &(struct clk_init_data){
1553                         .name = "pcie_phy_clk",
1554                         .ops = &clk_branch_ops,
1555                         .flags = CLK_IS_ROOT,
1556                 },
1557         },
1558 };
1559
1560 static struct clk_rcg pcie1_ref_src = {
1561         .ns_reg = 0x3aa0,
1562         .p = {
1563                 .pre_div_shift = 3,
1564                 .pre_div_width = 4,
1565         },
1566         .s = {
1567                 .src_sel_shift = 0,
1568                 .parent_map = gcc_pxo_pll3_map,
1569         },
1570         .freq_tbl = clk_tbl_pcie_ref,
1571         .clkr = {
1572                 .enable_reg = 0x3aa0,
1573                 .enable_mask = BIT(11),
1574                 .hw.init = &(struct clk_init_data){
1575                         .name = "pcie1_ref_src",
1576                         .parent_names = gcc_pxo_pll3,
1577                         .num_parents = 2,
1578                         .ops = &clk_rcg_ops,
1579                         .flags = CLK_SET_RATE_GATE,
1580                 },
1581         },
1582 };
1583
1584 static struct clk_branch pcie1_ref_src_clk = {
1585         .halt_reg = 0x2fdc,
1586         .halt_bit = 27,
1587         .clkr = {
1588                 .enable_reg = 0x3aa0,
1589                 .enable_mask = BIT(9),
1590                 .hw.init = &(struct clk_init_data){
1591                         .name = "pcie1_ref_src_clk",
1592                         .parent_names = (const char *[]){ "pcie1_ref_src" },
1593                         .num_parents = 1,
1594                         .ops = &clk_branch_ops,
1595                         .flags = CLK_SET_RATE_PARENT,
1596                 },
1597         },
1598 };
1599
1600 static struct clk_branch pcie1_a_clk = {
1601         .halt_reg = 0x2fc0,
1602         .halt_bit = 10,
1603         .clkr = {
1604                 .enable_reg = 0x3a80,
1605                 .enable_mask = BIT(4),
1606                 .hw.init = &(struct clk_init_data){
1607                         .name = "pcie1_a_clk",
1608                         .ops = &clk_branch_ops,
1609                         .flags = CLK_IS_ROOT,
1610                 },
1611         },
1612 };
1613
1614 static struct clk_branch pcie1_aux_clk = {
1615         .halt_reg = 0x2fdc,
1616         .halt_bit = 28,
1617         .clkr = {
1618                 .enable_reg = 0x3a88,
1619                 .enable_mask = BIT(4),
1620                 .hw.init = &(struct clk_init_data){
1621                         .name = "pcie1_aux_clk",
1622                         .ops = &clk_branch_ops,
1623                         .flags = CLK_IS_ROOT,
1624                 },
1625         },
1626 };
1627
1628 static struct clk_branch pcie1_h_clk = {
1629         .halt_reg = 0x2fd4,
1630         .halt_bit = 9,
1631         .clkr = {
1632                 .enable_reg = 0x3a8c,
1633                 .enable_mask = BIT(4),
1634                 .hw.init = &(struct clk_init_data){
1635                         .name = "pcie1_h_clk",
1636                         .ops = &clk_branch_ops,
1637                         .flags = CLK_IS_ROOT,
1638                 },
1639         },
1640 };
1641
1642 static struct clk_branch pcie1_phy_clk = {
1643         .halt_reg = 0x2fdc,
1644         .halt_bit = 26,
1645         .clkr = {
1646                 .enable_reg = 0x3a90,
1647                 .enable_mask = BIT(4),
1648                 .hw.init = &(struct clk_init_data){
1649                         .name = "pcie1_phy_clk",
1650                         .ops = &clk_branch_ops,
1651                         .flags = CLK_IS_ROOT,
1652                 },
1653         },
1654 };
1655
1656 static struct clk_rcg pcie2_ref_src = {
1657         .ns_reg = 0x3ae0,
1658         .p = {
1659                 .pre_div_shift = 3,
1660                 .pre_div_width = 4,
1661         },
1662         .s = {
1663                 .src_sel_shift = 0,
1664                 .parent_map = gcc_pxo_pll3_map,
1665         },
1666         .freq_tbl = clk_tbl_pcie_ref,
1667         .clkr = {
1668                 .enable_reg = 0x3ae0,
1669                 .enable_mask = BIT(11),
1670                 .hw.init = &(struct clk_init_data){
1671                         .name = "pcie2_ref_src",
1672                         .parent_names = gcc_pxo_pll3,
1673                         .num_parents = 2,
1674                         .ops = &clk_rcg_ops,
1675                         .flags = CLK_SET_RATE_GATE,
1676                 },
1677         },
1678 };
1679
1680 static struct clk_branch pcie2_ref_src_clk = {
1681         .halt_reg = 0x2fdc,
1682         .halt_bit = 24,
1683         .clkr = {
1684                 .enable_reg = 0x3ae0,
1685                 .enable_mask = BIT(9),
1686                 .hw.init = &(struct clk_init_data){
1687                         .name = "pcie2_ref_src_clk",
1688                         .parent_names = (const char *[]){ "pcie2_ref_src" },
1689                         .num_parents = 1,
1690                         .ops = &clk_branch_ops,
1691                         .flags = CLK_SET_RATE_PARENT,
1692                 },
1693         },
1694 };
1695
1696 static struct clk_branch pcie2_a_clk = {
1697         .halt_reg = 0x2fc0,
1698         .halt_bit = 9,
1699         .clkr = {
1700                 .enable_reg = 0x3ac0,
1701                 .enable_mask = BIT(4),
1702                 .hw.init = &(struct clk_init_data){
1703                         .name = "pcie2_a_clk",
1704                         .ops = &clk_branch_ops,
1705                         .flags = CLK_IS_ROOT,
1706                 },
1707         },
1708 };
1709
1710 static struct clk_branch pcie2_aux_clk = {
1711         .halt_reg = 0x2fdc,
1712         .halt_bit = 25,
1713         .clkr = {
1714                 .enable_reg = 0x3ac8,
1715                 .enable_mask = BIT(4),
1716                 .hw.init = &(struct clk_init_data){
1717                         .name = "pcie2_aux_clk",
1718                         .ops = &clk_branch_ops,
1719                         .flags = CLK_IS_ROOT,
1720                 },
1721         },
1722 };
1723
1724 static struct clk_branch pcie2_h_clk = {
1725         .halt_reg = 0x2fd4,
1726         .halt_bit = 10,
1727         .clkr = {
1728                 .enable_reg = 0x3acc,
1729                 .enable_mask = BIT(4),
1730                 .hw.init = &(struct clk_init_data){
1731                         .name = "pcie2_h_clk",
1732                         .ops = &clk_branch_ops,
1733                         .flags = CLK_IS_ROOT,
1734                 },
1735         },
1736 };
1737
1738 static struct clk_branch pcie2_phy_clk = {
1739         .halt_reg = 0x2fdc,
1740         .halt_bit = 23,
1741         .clkr = {
1742                 .enable_reg = 0x3ad0,
1743                 .enable_mask = BIT(4),
1744                 .hw.init = &(struct clk_init_data){
1745                         .name = "pcie2_phy_clk",
1746                         .ops = &clk_branch_ops,
1747                         .flags = CLK_IS_ROOT,
1748                 },
1749         },
1750 };
1751
1752 static const struct freq_tbl clk_tbl_sata_ref[] = {
1753         { 100000000, P_PLL3,  12, 0, 0 },
1754         { }
1755 };
1756
1757 static struct clk_rcg sata_ref_src = {
1758         .ns_reg = 0x2c08,
1759         .p = {
1760                 .pre_div_shift = 3,
1761                 .pre_div_width = 4,
1762         },
1763         .s = {
1764                 .src_sel_shift = 0,
1765                 .parent_map = gcc_pxo_pll3_sata_map,
1766         },
1767         .freq_tbl = clk_tbl_sata_ref,
1768         .clkr = {
1769                 .enable_reg = 0x2c08,
1770                 .enable_mask = BIT(7),
1771                 .hw.init = &(struct clk_init_data){
1772                         .name = "sata_ref_src",
1773                         .parent_names = gcc_pxo_pll3,
1774                         .num_parents = 2,
1775                         .ops = &clk_rcg_ops,
1776                         .flags = CLK_SET_RATE_GATE,
1777                 },
1778         },
1779 };
1780
1781 static struct clk_branch sata_rxoob_clk = {
1782         .halt_reg = 0x2fdc,
1783         .halt_bit = 20,
1784         .clkr = {
1785                 .enable_reg = 0x2c0c,
1786                 .enable_mask = BIT(4),
1787                 .hw.init = &(struct clk_init_data){
1788                         .name = "sata_rxoob_clk",
1789                         .parent_names = (const char *[]){ "sata_ref_src" },
1790                         .num_parents = 1,
1791                         .ops = &clk_branch_ops,
1792                         .flags = CLK_SET_RATE_PARENT,
1793                 },
1794         },
1795 };
1796
1797 static struct clk_branch sata_pmalive_clk = {
1798         .halt_reg = 0x2fdc,
1799         .halt_bit = 19,
1800         .clkr = {
1801                 .enable_reg = 0x2c10,
1802                 .enable_mask = BIT(4),
1803                 .hw.init = &(struct clk_init_data){
1804                         .name = "sata_pmalive_clk",
1805                         .parent_names = (const char *[]){ "sata_ref_src" },
1806                         .num_parents = 1,
1807                         .ops = &clk_branch_ops,
1808                         .flags = CLK_SET_RATE_PARENT,
1809                 },
1810         },
1811 };
1812
1813 static struct clk_branch sata_phy_ref_clk = {
1814         .halt_reg = 0x2fdc,
1815         .halt_bit = 18,
1816         .clkr = {
1817                 .enable_reg = 0x2c14,
1818                 .enable_mask = BIT(4),
1819                 .hw.init = &(struct clk_init_data){
1820                         .name = "sata_phy_ref_clk",
1821                         .parent_names = (const char *[]){ "pxo" },
1822                         .num_parents = 1,
1823                         .ops = &clk_branch_ops,
1824                 },
1825         },
1826 };
1827
1828 static struct clk_branch sata_a_clk = {
1829         .halt_reg = 0x2fc0,
1830         .halt_bit = 12,
1831         .clkr = {
1832                 .enable_reg = 0x2c20,
1833                 .enable_mask = BIT(4),
1834                 .hw.init = &(struct clk_init_data){
1835                         .name = "sata_a_clk",
1836                         .ops = &clk_branch_ops,
1837                         .flags = CLK_IS_ROOT,
1838                 },
1839         },
1840 };
1841
1842 static struct clk_branch sata_h_clk = {
1843         .halt_reg = 0x2fdc,
1844         .halt_bit = 21,
1845         .clkr = {
1846                 .enable_reg = 0x2c00,
1847                 .enable_mask = BIT(4),
1848                 .hw.init = &(struct clk_init_data){
1849                         .name = "sata_h_clk",
1850                         .ops = &clk_branch_ops,
1851                         .flags = CLK_IS_ROOT,
1852                 },
1853         },
1854 };
1855
1856 static struct clk_branch sfab_sata_s_h_clk = {
1857         .halt_reg = 0x2fc4,
1858         .halt_bit = 14,
1859         .clkr = {
1860                 .enable_reg = 0x2480,
1861                 .enable_mask = BIT(4),
1862                 .hw.init = &(struct clk_init_data){
1863                         .name = "sfab_sata_s_h_clk",
1864                         .ops = &clk_branch_ops,
1865                         .flags = CLK_IS_ROOT,
1866                 },
1867         },
1868 };
1869
1870 static struct clk_branch sata_phy_cfg_clk = {
1871         .halt_reg = 0x2fcc,
1872         .halt_bit = 14,
1873         .clkr = {
1874                 .enable_reg = 0x2c40,
1875                 .enable_mask = BIT(4),
1876                 .hw.init = &(struct clk_init_data){
1877                         .name = "sata_phy_cfg_clk",
1878                         .ops = &clk_branch_ops,
1879                         .flags = CLK_IS_ROOT,
1880                 },
1881         },
1882 };
1883
1884 static const struct freq_tbl clk_tbl_usb30_master[] = {
1885         { 125000000, P_PLL0,  1, 5, 32 },
1886         { }
1887 };
1888
1889 static struct clk_rcg usb30_master_clk_src = {
1890         .ns_reg = 0x3b2c,
1891         .md_reg = 0x3b28,
1892         .mn = {
1893                 .mnctr_en_bit = 8,
1894                 .mnctr_reset_bit = 7,
1895                 .mnctr_mode_shift = 5,
1896                 .n_val_shift = 16,
1897                 .m_val_shift = 16,
1898                 .width = 8,
1899         },
1900         .p = {
1901                 .pre_div_shift = 3,
1902                 .pre_div_width = 2,
1903         },
1904         .s = {
1905                 .src_sel_shift = 0,
1906                 .parent_map = gcc_pxo_pll8_pll0,
1907         },
1908         .freq_tbl = clk_tbl_usb30_master,
1909         .clkr = {
1910                 .enable_reg = 0x3b2c,
1911                 .enable_mask = BIT(11),
1912                 .hw.init = &(struct clk_init_data){
1913                         .name = "usb30_master_ref_src",
1914                         .parent_names = gcc_pxo_pll8_pll0_map,
1915                         .num_parents = 3,
1916                         .ops = &clk_rcg_ops,
1917                         .flags = CLK_SET_RATE_GATE,
1918                 },
1919         },
1920 };
1921
1922 static struct clk_branch usb30_0_branch_clk = {
1923         .halt_reg = 0x2fc4,
1924         .halt_bit = 22,
1925         .clkr = {
1926                 .enable_reg = 0x3b24,
1927                 .enable_mask = BIT(4),
1928                 .hw.init = &(struct clk_init_data){
1929                         .name = "usb30_0_branch_clk",
1930                         .parent_names = (const char *[]){ "usb30_master_ref_src", },
1931                         .num_parents = 1,
1932                         .ops = &clk_branch_ops,
1933                         .flags = CLK_SET_RATE_PARENT,
1934                 },
1935         },
1936 };
1937
1938 static struct clk_branch usb30_1_branch_clk = {
1939         .halt_reg = 0x2fc4,
1940         .halt_bit = 17,
1941         .clkr = {
1942                 .enable_reg = 0x3b34,
1943                 .enable_mask = BIT(4),
1944                 .hw.init = &(struct clk_init_data){
1945                         .name = "usb30_1_branch_clk",
1946                         .parent_names = (const char *[]){ "usb30_master_ref_src", },
1947                         .num_parents = 1,
1948                         .ops = &clk_branch_ops,
1949                         .flags = CLK_SET_RATE_PARENT,
1950                 },
1951         },
1952 };
1953
1954 static const struct freq_tbl clk_tbl_usb30_utmi[] = {
1955         { 60000000, P_PLL8,  1, 5, 32 },
1956         { }
1957 };
1958
1959 static struct clk_rcg usb30_utmi_clk = {
1960         .ns_reg = 0x3b44,
1961         .md_reg = 0x3b40,
1962         .mn = {
1963                 .mnctr_en_bit = 8,
1964                 .mnctr_reset_bit = 7,
1965                 .mnctr_mode_shift = 5,
1966                 .n_val_shift = 16,
1967                 .m_val_shift = 16,
1968                 .width = 8,
1969         },
1970         .p = {
1971                 .pre_div_shift = 3,
1972                 .pre_div_width = 2,
1973         },
1974         .s = {
1975                 .src_sel_shift = 0,
1976                 .parent_map = gcc_pxo_pll8_pll0,
1977         },
1978         .freq_tbl = clk_tbl_usb30_utmi,
1979         .clkr = {
1980                 .enable_reg = 0x3b44,
1981                 .enable_mask = BIT(11),
1982                 .hw.init = &(struct clk_init_data){
1983                         .name = "usb30_utmi_clk",
1984                         .parent_names = gcc_pxo_pll8_pll0_map,
1985                         .num_parents = 3,
1986                         .ops = &clk_rcg_ops,
1987                         .flags = CLK_SET_RATE_GATE,
1988                 },
1989         },
1990 };
1991
1992 static struct clk_branch usb30_0_utmi_clk_ctl = {
1993         .halt_reg = 0x2fc4,
1994         .halt_bit = 21,
1995         .clkr = {
1996                 .enable_reg = 0x3b48,
1997                 .enable_mask = BIT(4),
1998                 .hw.init = &(struct clk_init_data){
1999                         .name = "usb30_0_utmi_clk_ctl",
2000                         .parent_names = (const char *[]){ "usb30_utmi_clk", },
2001                         .num_parents = 1,
2002                         .ops = &clk_branch_ops,
2003                         .flags = CLK_SET_RATE_PARENT,
2004                 },
2005         },
2006 };
2007
2008 static struct clk_branch usb30_1_utmi_clk_ctl = {
2009         .halt_reg = 0x2fc4,
2010         .halt_bit = 15,
2011         .clkr = {
2012                 .enable_reg = 0x3b4c,
2013                 .enable_mask = BIT(4),
2014                 .hw.init = &(struct clk_init_data){
2015                         .name = "usb30_1_utmi_clk_ctl",
2016                         .parent_names = (const char *[]){ "usb30_utmi_clk", },
2017                         .num_parents = 1,
2018                         .ops = &clk_branch_ops,
2019                         .flags = CLK_SET_RATE_PARENT,
2020                 },
2021         },
2022 };
2023
2024 static const struct freq_tbl clk_tbl_usb[] = {
2025         { 60000000, P_PLL8,  1, 5, 32 },
2026         { }
2027 };
2028
2029 static struct clk_rcg usb_hs1_xcvr_clk_src = {
2030         .ns_reg = 0x290C,
2031         .md_reg = 0x2908,
2032         .mn = {
2033                 .mnctr_en_bit = 8,
2034                 .mnctr_reset_bit = 7,
2035                 .mnctr_mode_shift = 5,
2036                 .n_val_shift = 16,
2037                 .m_val_shift = 16,
2038                 .width = 8,
2039         },
2040         .p = {
2041                 .pre_div_shift = 3,
2042                 .pre_div_width = 2,
2043         },
2044         .s = {
2045                 .src_sel_shift = 0,
2046                 .parent_map = gcc_pxo_pll8_pll0,
2047         },
2048         .freq_tbl = clk_tbl_usb,
2049         .clkr = {
2050                 .enable_reg = 0x2968,
2051                 .enable_mask = BIT(11),
2052                 .hw.init = &(struct clk_init_data){
2053                         .name = "usb_hs1_xcvr_src",
2054                         .parent_names = gcc_pxo_pll8_pll0_map,
2055                         .num_parents = 3,
2056                         .ops = &clk_rcg_ops,
2057                         .flags = CLK_SET_RATE_GATE,
2058                 },
2059         },
2060 };
2061
2062 static struct clk_branch usb_hs1_xcvr_clk = {
2063         .halt_reg = 0x2fcc,
2064         .halt_bit = 17,
2065         .clkr = {
2066                 .enable_reg = 0x290c,
2067                 .enable_mask = BIT(9),
2068                 .hw.init = &(struct clk_init_data){
2069                         .name = "usb_hs1_xcvr_clk",
2070                         .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
2071                         .num_parents = 1,
2072                         .ops = &clk_branch_ops,
2073                         .flags = CLK_SET_RATE_PARENT,
2074                 },
2075         },
2076 };
2077
2078 static struct clk_branch usb_hs1_h_clk = {
2079         .hwcg_reg = 0x2900,
2080         .hwcg_bit = 6,
2081         .halt_reg = 0x2fc8,
2082         .halt_bit = 1,
2083         .clkr = {
2084                 .enable_reg = 0x2900,
2085                 .enable_mask = BIT(4),
2086                 .hw.init = &(struct clk_init_data){
2087                         .name = "usb_hs1_h_clk",
2088                         .ops = &clk_branch_ops,
2089                         .flags = CLK_IS_ROOT,
2090                 },
2091         },
2092 };
2093
2094 static struct clk_rcg usb_fs1_xcvr_clk_src = {
2095         .ns_reg = 0x2968,
2096         .md_reg = 0x2964,
2097         .mn = {
2098                 .mnctr_en_bit = 8,
2099                 .mnctr_reset_bit = 7,
2100                 .mnctr_mode_shift = 5,
2101                 .n_val_shift = 16,
2102                 .m_val_shift = 16,
2103                 .width = 8,
2104         },
2105         .p = {
2106                 .pre_div_shift = 3,
2107                 .pre_div_width = 2,
2108         },
2109         .s = {
2110                 .src_sel_shift = 0,
2111                 .parent_map = gcc_pxo_pll8_pll0,
2112         },
2113         .freq_tbl = clk_tbl_usb,
2114         .clkr = {
2115                 .enable_reg = 0x2968,
2116                 .enable_mask = BIT(11),
2117                 .hw.init = &(struct clk_init_data){
2118                         .name = "usb_fs1_xcvr_src",
2119                         .parent_names = gcc_pxo_pll8_pll0_map,
2120                         .num_parents = 3,
2121                         .ops = &clk_rcg_ops,
2122                         .flags = CLK_SET_RATE_GATE,
2123                 },
2124         },
2125 };
2126
2127 static struct clk_branch usb_fs1_xcvr_clk = {
2128         .halt_reg = 0x2fcc,
2129         .halt_bit = 17,
2130         .clkr = {
2131                 .enable_reg = 0x2968,
2132                 .enable_mask = BIT(9),
2133                 .hw.init = &(struct clk_init_data){
2134                         .name = "usb_fs1_xcvr_clk",
2135                         .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2136                         .num_parents = 1,
2137                         .ops = &clk_branch_ops,
2138                         .flags = CLK_SET_RATE_PARENT,
2139                 },
2140         },
2141 };
2142
2143 static struct clk_branch usb_fs1_sys_clk = {
2144         .halt_reg = 0x2fcc,
2145         .halt_bit = 18,
2146         .clkr = {
2147                 .enable_reg = 0x296c,
2148                 .enable_mask = BIT(4),
2149                 .hw.init = &(struct clk_init_data){
2150                         .name = "usb_fs1_sys_clk",
2151                         .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2152                         .num_parents = 1,
2153                         .ops = &clk_branch_ops,
2154                         .flags = CLK_SET_RATE_PARENT,
2155                 },
2156         },
2157 };
2158
2159 static struct clk_branch usb_fs1_h_clk = {
2160         .halt_reg = 0x2fcc,
2161         .halt_bit = 19,
2162         .clkr = {
2163                 .enable_reg = 0x2960,
2164                 .enable_mask = BIT(4),
2165                 .hw.init = &(struct clk_init_data){
2166                         .name = "usb_fs1_h_clk",
2167                         .ops = &clk_branch_ops,
2168                         .flags = CLK_IS_ROOT,
2169                 },
2170         },
2171 };
2172
2173 static struct clk_regmap *gcc_ipq806x_clks[] = {
2174         [PLL0] = &pll0.clkr,
2175         [PLL0_VOTE] = &pll0_vote,
2176         [PLL3] = &pll3.clkr,
2177         [PLL4_VOTE] = &pll4_vote,
2178         [PLL8] = &pll8.clkr,
2179         [PLL8_VOTE] = &pll8_vote,
2180         [PLL14] = &pll14.clkr,
2181         [PLL14_VOTE] = &pll14_vote,
2182         [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2183         [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2184         [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2185         [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2186         [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2187         [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2188         [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2189         [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2190         [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2191         [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2192         [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2193         [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2194         [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2195         [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2196         [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2197         [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2198         [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2199         [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2200         [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2201         [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2202         [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2203         [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2204         [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2205         [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2206         [GP0_SRC] = &gp0_src.clkr,
2207         [GP0_CLK] = &gp0_clk.clkr,
2208         [GP1_SRC] = &gp1_src.clkr,
2209         [GP1_CLK] = &gp1_clk.clkr,
2210         [GP2_SRC] = &gp2_src.clkr,
2211         [GP2_CLK] = &gp2_clk.clkr,
2212         [PMEM_A_CLK] = &pmem_clk.clkr,
2213         [PRNG_SRC] = &prng_src.clkr,
2214         [PRNG_CLK] = &prng_clk.clkr,
2215         [SDC1_SRC] = &sdc1_src.clkr,
2216         [SDC1_CLK] = &sdc1_clk.clkr,
2217         [SDC3_SRC] = &sdc3_src.clkr,
2218         [SDC3_CLK] = &sdc3_clk.clkr,
2219         [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2220         [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2221         [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
2222         [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2223         [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2224         [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2225         [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2226         [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2227         [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2228         [TSIF_H_CLK] = &tsif_h_clk.clkr,
2229         [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2230         [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2231         [ADM0_CLK] = &adm0_clk.clkr,
2232         [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2233         [PCIE_A_CLK] = &pcie_a_clk.clkr,
2234         [PCIE_AUX_CLK] = &pcie_aux_clk.clkr,
2235         [PCIE_H_CLK] = &pcie_h_clk.clkr,
2236         [PCIE_PHY_CLK] = &pcie_phy_clk.clkr,
2237         [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
2238         [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2239         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2240         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2241         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2242         [SATA_H_CLK] = &sata_h_clk.clkr,
2243         [SATA_CLK_SRC] = &sata_ref_src.clkr,
2244         [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
2245         [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
2246         [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
2247         [SATA_A_CLK] = &sata_a_clk.clkr,
2248         [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
2249         [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr,
2250         [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr,
2251         [PCIE_1_A_CLK] = &pcie1_a_clk.clkr,
2252         [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr,
2253         [PCIE_1_H_CLK] = &pcie1_h_clk.clkr,
2254         [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr,
2255         [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr,
2256         [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr,
2257         [PCIE_2_A_CLK] = &pcie2_a_clk.clkr,
2258         [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr,
2259         [PCIE_2_H_CLK] = &pcie2_h_clk.clkr,
2260         [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr,
2261         [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr,
2262         [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr,
2263         [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr,
2264         [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr,
2265         [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr,
2266         [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr,
2267         [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr,
2268         [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr,
2269         [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2270         [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr,
2271         [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2272         [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2273         [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
2274         [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
2275         [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
2276 };
2277
2278 static const struct qcom_reset_map gcc_ipq806x_resets[] = {
2279         [QDSS_STM_RESET] = { 0x2060, 6 },
2280         [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2281         [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2282         [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
2283         [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
2284         [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
2285         [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2286         [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2287         [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
2288         [ADM0_C2_RESET] = { 0x220c, 4 },
2289         [ADM0_C1_RESET] = { 0x220c, 3 },
2290         [ADM0_C0_RESET] = { 0x220c, 2 },
2291         [ADM0_PBUS_RESET] = { 0x220c, 1 },
2292         [ADM0_RESET] = { 0x220c, 0 },
2293         [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
2294         [QDSS_POR_RESET] = { 0x2260, 4 },
2295         [QDSS_TSCTR_RESET] = { 0x2260, 3 },
2296         [QDSS_HRESET_RESET] = { 0x2260, 2 },
2297         [QDSS_AXI_RESET] = { 0x2260, 1 },
2298         [QDSS_DBG_RESET] = { 0x2260, 0 },
2299         [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
2300         [SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
2301         [PCIE_EXT_RESET] = { 0x22dc, 6 },
2302         [PCIE_PHY_RESET] = { 0x22dc, 5 },
2303         [PCIE_PCI_RESET] = { 0x22dc, 4 },
2304         [PCIE_POR_RESET] = { 0x22dc, 3 },
2305         [PCIE_HCLK_RESET] = { 0x22dc, 2 },
2306         [PCIE_ACLK_RESET] = { 0x22dc, 0 },
2307         [SFAB_LPASS_RESET] = { 0x23a0, 7 },
2308         [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2309         [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2310         [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2311         [SFAB_SATA_S_RESET] = { 0x2480, 7 },
2312         [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2313         [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2314         [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2315         [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2316         [DFAB_ARB0_RESET] = { 0x2560, 7 },
2317         [DFAB_ARB1_RESET] = { 0x2564, 7 },
2318         [PPSS_PROC_RESET] = { 0x2594, 1 },
2319         [PPSS_RESET] = { 0x2594, 0 },
2320         [DMA_BAM_RESET] = { 0x25c0, 7 },
2321         [SPS_TIC_H_RESET] = { 0x2600, 7 },
2322         [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2323         [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2324         [TSIF_H_RESET] = { 0x2700, 7 },
2325         [CE1_H_RESET] = { 0x2720, 7 },
2326         [CE1_CORE_RESET] = { 0x2724, 7 },
2327         [CE1_SLEEP_RESET] = { 0x2728, 7 },
2328         [CE2_H_RESET] = { 0x2740, 7 },
2329         [CE2_CORE_RESET] = { 0x2744, 7 },
2330         [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2331         [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2332         [RPM_PROC_RESET] = { 0x27c0, 7 },
2333         [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2334         [SDC1_RESET] = { 0x2830, 0 },
2335         [SDC2_RESET] = { 0x2850, 0 },
2336         [SDC3_RESET] = { 0x2870, 0 },
2337         [SDC4_RESET] = { 0x2890, 0 },
2338         [USB_HS1_RESET] = { 0x2910, 0 },
2339         [USB_HSIC_RESET] = { 0x2934, 0 },
2340         [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2341         [USB_FS1_RESET] = { 0x2974, 0 },
2342         [GSBI1_RESET] = { 0x29dc, 0 },
2343         [GSBI2_RESET] = { 0x29fc, 0 },
2344         [GSBI3_RESET] = { 0x2a1c, 0 },
2345         [GSBI4_RESET] = { 0x2a3c, 0 },
2346         [GSBI5_RESET] = { 0x2a5c, 0 },
2347         [GSBI6_RESET] = { 0x2a7c, 0 },
2348         [GSBI7_RESET] = { 0x2a9c, 0 },
2349         [SPDM_RESET] = { 0x2b6c, 0 },
2350         [SEC_CTRL_RESET] = { 0x2b80, 7 },
2351         [TLMM_H_RESET] = { 0x2ba0, 7 },
2352         [SFAB_SATA_M_RESET] = { 0x2c18, 0 },
2353         [SATA_RESET] = { 0x2c1c, 0 },
2354         [TSSC_RESET] = { 0x2ca0, 7 },
2355         [PDM_RESET] = { 0x2cc0, 12 },
2356         [MPM_H_RESET] = { 0x2da0, 7 },
2357         [MPM_RESET] = { 0x2da4, 0 },
2358         [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2359         [PRNG_RESET] = { 0x2e80, 12 },
2360         [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
2361         [SFAB_CE3_S_RESET] = { 0x36c8, 0 },
2362         [CE3_SLEEP_RESET] = { 0x36d0, 7 },
2363         [PCIE_1_M_RESET] = { 0x3a98, 1 },
2364         [PCIE_1_S_RESET] = { 0x3a98, 0 },
2365         [PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
2366         [PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
2367         [PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
2368         [PCIE_1_POR_RESET] = { 0x3a9c, 3 },
2369         [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
2370         [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
2371         [PCIE_2_M_RESET] = { 0x3ad8, 1 },
2372         [PCIE_2_S_RESET] = { 0x3ad8, 0 },
2373         [PCIE_2_EXT_RESET] = { 0x3adc, 6 },
2374         [PCIE_2_PHY_RESET] = { 0x3adc, 5 },
2375         [PCIE_2_PCI_RESET] = { 0x3adc, 4 },
2376         [PCIE_2_POR_RESET] = { 0x3adc, 3 },
2377         [PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
2378         [PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
2379         [SFAB_USB30_S_RESET] = { 0x3b54, 1 },
2380         [SFAB_USB30_M_RESET] = { 0x3b54, 0 },
2381         [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
2382         [USB30_0_MASTER_RESET] = { 0x3b50, 4 },
2383         [USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
2384         [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
2385         [USB30_0_POWERON_RESET] = { 0x3b50, 1 },
2386         [USB30_0_PHY_RESET] = { 0x3b50, 0 },
2387         [USB30_1_MASTER_RESET] = { 0x3b58, 4 },
2388         [USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
2389         [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
2390         [USB30_1_POWERON_RESET] = { 0x3b58, 1 },
2391         [USB30_1_PHY_RESET] = { 0x3b58, 0 },
2392         [NSSFB0_RESET] = { 0x3b60, 6 },
2393         [NSSFB1_RESET] = { 0x3b60, 7 },
2394 };
2395
2396 static const struct regmap_config gcc_ipq806x_regmap_config = {
2397         .reg_bits       = 32,
2398         .reg_stride     = 4,
2399         .val_bits       = 32,
2400         .max_register   = 0x3e40,
2401         .fast_io        = true,
2402 };
2403
2404 static const struct qcom_cc_desc gcc_ipq806x_desc = {
2405         .config = &gcc_ipq806x_regmap_config,
2406         .clks = gcc_ipq806x_clks,
2407         .num_clks = ARRAY_SIZE(gcc_ipq806x_clks),
2408         .resets = gcc_ipq806x_resets,
2409         .num_resets = ARRAY_SIZE(gcc_ipq806x_resets),
2410 };
2411
2412 static const struct of_device_id gcc_ipq806x_match_table[] = {
2413         { .compatible = "qcom,gcc-ipq8064" },
2414         { }
2415 };
2416 MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);
2417
2418 static int gcc_ipq806x_probe(struct platform_device *pdev)
2419 {
2420         struct clk *clk;
2421         struct device *dev = &pdev->dev;
2422
2423         /* Temporary until RPM clocks supported */
2424         clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000);
2425         if (IS_ERR(clk))
2426                 return PTR_ERR(clk);
2427
2428         clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 25000000);
2429         if (IS_ERR(clk))
2430                 return PTR_ERR(clk);
2431
2432         return qcom_cc_probe(pdev, &gcc_ipq806x_desc);
2433 }
2434
2435 static int gcc_ipq806x_remove(struct platform_device *pdev)
2436 {
2437         qcom_cc_remove(pdev);
2438         return 0;
2439 }
2440
2441 static struct platform_driver gcc_ipq806x_driver = {
2442         .probe          = gcc_ipq806x_probe,
2443         .remove         = gcc_ipq806x_remove,
2444         .driver         = {
2445                 .name   = "gcc-ipq806x",
2446                 .of_match_table = gcc_ipq806x_match_table,
2447         },
2448 };
2449
2450 static int __init gcc_ipq806x_init(void)
2451 {
2452         return platform_driver_register(&gcc_ipq806x_driver);
2453 }
2454 core_initcall(gcc_ipq806x_init);
2455
2456 static void __exit gcc_ipq806x_exit(void)
2457 {
2458         platform_driver_unregister(&gcc_ipq806x_driver);
2459 }
2460 module_exit(gcc_ipq806x_exit);
2461
2462 MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver");
2463 MODULE_LICENSE("GPL v2");
2464 MODULE_ALIAS("platform:gcc-ipq806x");