2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
26 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
35 static struct clk_pll pll0 = {
43 .clkr.hw.init = &(struct clk_init_data){
45 .parent_names = (const char *[]){ "pxo" },
51 static struct clk_regmap pll0_vote = {
53 .enable_mask = BIT(0),
54 .hw.init = &(struct clk_init_data){
56 .parent_names = (const char *[]){ "pll0" },
58 .ops = &clk_pll_vote_ops,
62 static struct clk_pll pll3 = {
70 .clkr.hw.init = &(struct clk_init_data){
72 .parent_names = (const char *[]){ "pxo" },
78 static struct clk_regmap pll4_vote = {
80 .enable_mask = BIT(4),
81 .hw.init = &(struct clk_init_data){
83 .parent_names = (const char *[]){ "pll4" },
85 .ops = &clk_pll_vote_ops,
89 static struct clk_pll pll8 = {
97 .clkr.hw.init = &(struct clk_init_data){
99 .parent_names = (const char *[]){ "pxo" },
105 static struct clk_regmap pll8_vote = {
106 .enable_reg = 0x34c0,
107 .enable_mask = BIT(8),
108 .hw.init = &(struct clk_init_data){
110 .parent_names = (const char *[]){ "pll8" },
112 .ops = &clk_pll_vote_ops,
116 static struct clk_pll pll14 = {
120 .config_reg = 0x31d4,
122 .status_reg = 0x31d8,
124 .clkr.hw.init = &(struct clk_init_data){
126 .parent_names = (const char *[]){ "pxo" },
132 static struct clk_regmap pll14_vote = {
133 .enable_reg = 0x34c0,
134 .enable_mask = BIT(14),
135 .hw.init = &(struct clk_init_data){
136 .name = "pll14_vote",
137 .parent_names = (const char *[]){ "pll14" },
139 .ops = &clk_pll_vote_ops,
149 static const u8 gcc_pxo_pll8_map[] = {
154 static const char *gcc_pxo_pll8[] = {
159 static const u8 gcc_pxo_pll8_cxo_map[] = {
165 static const char *gcc_pxo_pll8_cxo[] = {
171 static const u8 gcc_pxo_pll3_map[] = {
176 static const u8 gcc_pxo_pll3_sata_map[] = {
181 static const char *gcc_pxo_pll3[] = {
186 static const u8 gcc_pxo_pll8_pll0[] = {
192 static const char *gcc_pxo_pll8_pll0_map[] = {
198 static struct freq_tbl clk_tbl_gsbi_uart[] = {
199 { 1843200, P_PLL8, 2, 6, 625 },
200 { 3686400, P_PLL8, 2, 12, 625 },
201 { 7372800, P_PLL8, 2, 24, 625 },
202 { 14745600, P_PLL8, 2, 48, 625 },
203 { 16000000, P_PLL8, 4, 1, 6 },
204 { 24000000, P_PLL8, 4, 1, 4 },
205 { 32000000, P_PLL8, 4, 1, 3 },
206 { 40000000, P_PLL8, 1, 5, 48 },
207 { 46400000, P_PLL8, 1, 29, 240 },
208 { 48000000, P_PLL8, 4, 1, 2 },
209 { 51200000, P_PLL8, 1, 2, 15 },
210 { 56000000, P_PLL8, 1, 7, 48 },
211 { 58982400, P_PLL8, 1, 96, 625 },
212 { 64000000, P_PLL8, 2, 1, 3 },
216 static struct clk_rcg gsbi1_uart_src = {
221 .mnctr_reset_bit = 7,
222 .mnctr_mode_shift = 5,
233 .parent_map = gcc_pxo_pll8_map,
235 .freq_tbl = clk_tbl_gsbi_uart,
237 .enable_reg = 0x29d4,
238 .enable_mask = BIT(11),
239 .hw.init = &(struct clk_init_data){
240 .name = "gsbi1_uart_src",
241 .parent_names = gcc_pxo_pll8,
244 .flags = CLK_SET_PARENT_GATE,
249 static struct clk_branch gsbi1_uart_clk = {
253 .enable_reg = 0x29d4,
254 .enable_mask = BIT(9),
255 .hw.init = &(struct clk_init_data){
256 .name = "gsbi1_uart_clk",
257 .parent_names = (const char *[]){
261 .ops = &clk_branch_ops,
262 .flags = CLK_SET_RATE_PARENT,
267 static struct clk_rcg gsbi2_uart_src = {
272 .mnctr_reset_bit = 7,
273 .mnctr_mode_shift = 5,
284 .parent_map = gcc_pxo_pll8_map,
286 .freq_tbl = clk_tbl_gsbi_uart,
288 .enable_reg = 0x29f4,
289 .enable_mask = BIT(11),
290 .hw.init = &(struct clk_init_data){
291 .name = "gsbi2_uart_src",
292 .parent_names = gcc_pxo_pll8,
295 .flags = CLK_SET_PARENT_GATE,
300 static struct clk_branch gsbi2_uart_clk = {
304 .enable_reg = 0x29f4,
305 .enable_mask = BIT(9),
306 .hw.init = &(struct clk_init_data){
307 .name = "gsbi2_uart_clk",
308 .parent_names = (const char *[]){
312 .ops = &clk_branch_ops,
313 .flags = CLK_SET_RATE_PARENT,
318 static struct clk_rcg gsbi4_uart_src = {
323 .mnctr_reset_bit = 7,
324 .mnctr_mode_shift = 5,
335 .parent_map = gcc_pxo_pll8_map,
337 .freq_tbl = clk_tbl_gsbi_uart,
339 .enable_reg = 0x2a34,
340 .enable_mask = BIT(11),
341 .hw.init = &(struct clk_init_data){
342 .name = "gsbi4_uart_src",
343 .parent_names = gcc_pxo_pll8,
346 .flags = CLK_SET_PARENT_GATE,
351 static struct clk_branch gsbi4_uart_clk = {
355 .enable_reg = 0x2a34,
356 .enable_mask = BIT(9),
357 .hw.init = &(struct clk_init_data){
358 .name = "gsbi4_uart_clk",
359 .parent_names = (const char *[]){
363 .ops = &clk_branch_ops,
364 .flags = CLK_SET_RATE_PARENT,
369 static struct clk_rcg gsbi5_uart_src = {
374 .mnctr_reset_bit = 7,
375 .mnctr_mode_shift = 5,
386 .parent_map = gcc_pxo_pll8_map,
388 .freq_tbl = clk_tbl_gsbi_uart,
390 .enable_reg = 0x2a54,
391 .enable_mask = BIT(11),
392 .hw.init = &(struct clk_init_data){
393 .name = "gsbi5_uart_src",
394 .parent_names = gcc_pxo_pll8,
397 .flags = CLK_SET_PARENT_GATE,
402 static struct clk_branch gsbi5_uart_clk = {
406 .enable_reg = 0x2a54,
407 .enable_mask = BIT(9),
408 .hw.init = &(struct clk_init_data){
409 .name = "gsbi5_uart_clk",
410 .parent_names = (const char *[]){
414 .ops = &clk_branch_ops,
415 .flags = CLK_SET_RATE_PARENT,
420 static struct clk_rcg gsbi6_uart_src = {
425 .mnctr_reset_bit = 7,
426 .mnctr_mode_shift = 5,
437 .parent_map = gcc_pxo_pll8_map,
439 .freq_tbl = clk_tbl_gsbi_uart,
441 .enable_reg = 0x2a74,
442 .enable_mask = BIT(11),
443 .hw.init = &(struct clk_init_data){
444 .name = "gsbi6_uart_src",
445 .parent_names = gcc_pxo_pll8,
448 .flags = CLK_SET_PARENT_GATE,
453 static struct clk_branch gsbi6_uart_clk = {
457 .enable_reg = 0x2a74,
458 .enable_mask = BIT(9),
459 .hw.init = &(struct clk_init_data){
460 .name = "gsbi6_uart_clk",
461 .parent_names = (const char *[]){
465 .ops = &clk_branch_ops,
466 .flags = CLK_SET_RATE_PARENT,
471 static struct clk_rcg gsbi7_uart_src = {
476 .mnctr_reset_bit = 7,
477 .mnctr_mode_shift = 5,
488 .parent_map = gcc_pxo_pll8_map,
490 .freq_tbl = clk_tbl_gsbi_uart,
492 .enable_reg = 0x2a94,
493 .enable_mask = BIT(11),
494 .hw.init = &(struct clk_init_data){
495 .name = "gsbi7_uart_src",
496 .parent_names = gcc_pxo_pll8,
499 .flags = CLK_SET_PARENT_GATE,
504 static struct clk_branch gsbi7_uart_clk = {
508 .enable_reg = 0x2a94,
509 .enable_mask = BIT(9),
510 .hw.init = &(struct clk_init_data){
511 .name = "gsbi7_uart_clk",
512 .parent_names = (const char *[]){
516 .ops = &clk_branch_ops,
517 .flags = CLK_SET_RATE_PARENT,
522 static struct freq_tbl clk_tbl_gsbi_qup[] = {
523 { 1100000, P_PXO, 1, 2, 49 },
524 { 5400000, P_PXO, 1, 1, 5 },
525 { 10800000, P_PXO, 1, 2, 5 },
526 { 15060000, P_PLL8, 1, 2, 51 },
527 { 24000000, P_PLL8, 4, 1, 4 },
528 { 25600000, P_PLL8, 1, 1, 15 },
529 { 27000000, P_PXO, 1, 0, 0 },
530 { 48000000, P_PLL8, 4, 1, 2 },
531 { 51200000, P_PLL8, 1, 2, 15 },
535 static struct clk_rcg gsbi1_qup_src = {
540 .mnctr_reset_bit = 7,
541 .mnctr_mode_shift = 5,
552 .parent_map = gcc_pxo_pll8_map,
554 .freq_tbl = clk_tbl_gsbi_qup,
556 .enable_reg = 0x29cc,
557 .enable_mask = BIT(11),
558 .hw.init = &(struct clk_init_data){
559 .name = "gsbi1_qup_src",
560 .parent_names = gcc_pxo_pll8,
563 .flags = CLK_SET_PARENT_GATE,
568 static struct clk_branch gsbi1_qup_clk = {
572 .enable_reg = 0x29cc,
573 .enable_mask = BIT(9),
574 .hw.init = &(struct clk_init_data){
575 .name = "gsbi1_qup_clk",
576 .parent_names = (const char *[]){ "gsbi1_qup_src" },
578 .ops = &clk_branch_ops,
579 .flags = CLK_SET_RATE_PARENT,
584 static struct clk_rcg gsbi2_qup_src = {
589 .mnctr_reset_bit = 7,
590 .mnctr_mode_shift = 5,
601 .parent_map = gcc_pxo_pll8_map,
603 .freq_tbl = clk_tbl_gsbi_qup,
605 .enable_reg = 0x29ec,
606 .enable_mask = BIT(11),
607 .hw.init = &(struct clk_init_data){
608 .name = "gsbi2_qup_src",
609 .parent_names = gcc_pxo_pll8,
612 .flags = CLK_SET_PARENT_GATE,
617 static struct clk_branch gsbi2_qup_clk = {
621 .enable_reg = 0x29ec,
622 .enable_mask = BIT(9),
623 .hw.init = &(struct clk_init_data){
624 .name = "gsbi2_qup_clk",
625 .parent_names = (const char *[]){ "gsbi2_qup_src" },
627 .ops = &clk_branch_ops,
628 .flags = CLK_SET_RATE_PARENT,
633 static struct clk_rcg gsbi4_qup_src = {
638 .mnctr_reset_bit = 7,
639 .mnctr_mode_shift = 5,
650 .parent_map = gcc_pxo_pll8_map,
652 .freq_tbl = clk_tbl_gsbi_qup,
654 .enable_reg = 0x2a2c,
655 .enable_mask = BIT(11),
656 .hw.init = &(struct clk_init_data){
657 .name = "gsbi4_qup_src",
658 .parent_names = gcc_pxo_pll8,
661 .flags = CLK_SET_PARENT_GATE,
666 static struct clk_branch gsbi4_qup_clk = {
670 .enable_reg = 0x2a2c,
671 .enable_mask = BIT(9),
672 .hw.init = &(struct clk_init_data){
673 .name = "gsbi4_qup_clk",
674 .parent_names = (const char *[]){ "gsbi4_qup_src" },
676 .ops = &clk_branch_ops,
677 .flags = CLK_SET_RATE_PARENT,
682 static struct clk_rcg gsbi5_qup_src = {
687 .mnctr_reset_bit = 7,
688 .mnctr_mode_shift = 5,
699 .parent_map = gcc_pxo_pll8_map,
701 .freq_tbl = clk_tbl_gsbi_qup,
703 .enable_reg = 0x2a4c,
704 .enable_mask = BIT(11),
705 .hw.init = &(struct clk_init_data){
706 .name = "gsbi5_qup_src",
707 .parent_names = gcc_pxo_pll8,
710 .flags = CLK_SET_PARENT_GATE,
715 static struct clk_branch gsbi5_qup_clk = {
719 .enable_reg = 0x2a4c,
720 .enable_mask = BIT(9),
721 .hw.init = &(struct clk_init_data){
722 .name = "gsbi5_qup_clk",
723 .parent_names = (const char *[]){ "gsbi5_qup_src" },
725 .ops = &clk_branch_ops,
726 .flags = CLK_SET_RATE_PARENT,
731 static struct clk_rcg gsbi6_qup_src = {
736 .mnctr_reset_bit = 7,
737 .mnctr_mode_shift = 5,
748 .parent_map = gcc_pxo_pll8_map,
750 .freq_tbl = clk_tbl_gsbi_qup,
752 .enable_reg = 0x2a6c,
753 .enable_mask = BIT(11),
754 .hw.init = &(struct clk_init_data){
755 .name = "gsbi6_qup_src",
756 .parent_names = gcc_pxo_pll8,
759 .flags = CLK_SET_PARENT_GATE,
764 static struct clk_branch gsbi6_qup_clk = {
768 .enable_reg = 0x2a6c,
769 .enable_mask = BIT(9),
770 .hw.init = &(struct clk_init_data){
771 .name = "gsbi6_qup_clk",
772 .parent_names = (const char *[]){ "gsbi6_qup_src" },
774 .ops = &clk_branch_ops,
775 .flags = CLK_SET_RATE_PARENT,
780 static struct clk_rcg gsbi7_qup_src = {
785 .mnctr_reset_bit = 7,
786 .mnctr_mode_shift = 5,
797 .parent_map = gcc_pxo_pll8_map,
799 .freq_tbl = clk_tbl_gsbi_qup,
801 .enable_reg = 0x2a8c,
802 .enable_mask = BIT(11),
803 .hw.init = &(struct clk_init_data){
804 .name = "gsbi7_qup_src",
805 .parent_names = gcc_pxo_pll8,
808 .flags = CLK_SET_PARENT_GATE,
813 static struct clk_branch gsbi7_qup_clk = {
817 .enable_reg = 0x2a8c,
818 .enable_mask = BIT(9),
819 .hw.init = &(struct clk_init_data){
820 .name = "gsbi7_qup_clk",
821 .parent_names = (const char *[]){ "gsbi7_qup_src" },
823 .ops = &clk_branch_ops,
824 .flags = CLK_SET_RATE_PARENT,
829 static struct clk_branch gsbi1_h_clk = {
835 .enable_reg = 0x29c0,
836 .enable_mask = BIT(4),
837 .hw.init = &(struct clk_init_data){
838 .name = "gsbi1_h_clk",
839 .ops = &clk_branch_ops,
840 .flags = CLK_IS_ROOT,
845 static struct clk_branch gsbi2_h_clk = {
851 .enable_reg = 0x29e0,
852 .enable_mask = BIT(4),
853 .hw.init = &(struct clk_init_data){
854 .name = "gsbi2_h_clk",
855 .ops = &clk_branch_ops,
856 .flags = CLK_IS_ROOT,
861 static struct clk_branch gsbi4_h_clk = {
867 .enable_reg = 0x2a20,
868 .enable_mask = BIT(4),
869 .hw.init = &(struct clk_init_data){
870 .name = "gsbi4_h_clk",
871 .ops = &clk_branch_ops,
872 .flags = CLK_IS_ROOT,
877 static struct clk_branch gsbi5_h_clk = {
883 .enable_reg = 0x2a40,
884 .enable_mask = BIT(4),
885 .hw.init = &(struct clk_init_data){
886 .name = "gsbi5_h_clk",
887 .ops = &clk_branch_ops,
888 .flags = CLK_IS_ROOT,
893 static struct clk_branch gsbi6_h_clk = {
899 .enable_reg = 0x2a60,
900 .enable_mask = BIT(4),
901 .hw.init = &(struct clk_init_data){
902 .name = "gsbi6_h_clk",
903 .ops = &clk_branch_ops,
904 .flags = CLK_IS_ROOT,
909 static struct clk_branch gsbi7_h_clk = {
915 .enable_reg = 0x2a80,
916 .enable_mask = BIT(4),
917 .hw.init = &(struct clk_init_data){
918 .name = "gsbi7_h_clk",
919 .ops = &clk_branch_ops,
920 .flags = CLK_IS_ROOT,
925 static const struct freq_tbl clk_tbl_gp[] = {
926 { 12500000, P_PXO, 2, 0, 0 },
927 { 25000000, P_PXO, 1, 0, 0 },
928 { 64000000, P_PLL8, 2, 1, 3 },
929 { 76800000, P_PLL8, 1, 1, 5 },
930 { 96000000, P_PLL8, 4, 0, 0 },
931 { 128000000, P_PLL8, 3, 0, 0 },
932 { 192000000, P_PLL8, 2, 0, 0 },
936 static struct clk_rcg gp0_src = {
941 .mnctr_reset_bit = 7,
942 .mnctr_mode_shift = 5,
953 .parent_map = gcc_pxo_pll8_cxo_map,
955 .freq_tbl = clk_tbl_gp,
957 .enable_reg = 0x2d24,
958 .enable_mask = BIT(11),
959 .hw.init = &(struct clk_init_data){
961 .parent_names = gcc_pxo_pll8_cxo,
964 .flags = CLK_SET_PARENT_GATE,
969 static struct clk_branch gp0_clk = {
973 .enable_reg = 0x2d24,
974 .enable_mask = BIT(9),
975 .hw.init = &(struct clk_init_data){
977 .parent_names = (const char *[]){ "gp0_src" },
979 .ops = &clk_branch_ops,
980 .flags = CLK_SET_RATE_PARENT,
985 static struct clk_rcg gp1_src = {
990 .mnctr_reset_bit = 7,
991 .mnctr_mode_shift = 5,
1002 .parent_map = gcc_pxo_pll8_cxo_map,
1004 .freq_tbl = clk_tbl_gp,
1006 .enable_reg = 0x2d44,
1007 .enable_mask = BIT(11),
1008 .hw.init = &(struct clk_init_data){
1010 .parent_names = gcc_pxo_pll8_cxo,
1012 .ops = &clk_rcg_ops,
1013 .flags = CLK_SET_RATE_GATE,
1018 static struct clk_branch gp1_clk = {
1022 .enable_reg = 0x2d44,
1023 .enable_mask = BIT(9),
1024 .hw.init = &(struct clk_init_data){
1026 .parent_names = (const char *[]){ "gp1_src" },
1028 .ops = &clk_branch_ops,
1029 .flags = CLK_SET_RATE_PARENT,
1034 static struct clk_rcg gp2_src = {
1039 .mnctr_reset_bit = 7,
1040 .mnctr_mode_shift = 5,
1051 .parent_map = gcc_pxo_pll8_cxo_map,
1053 .freq_tbl = clk_tbl_gp,
1055 .enable_reg = 0x2d64,
1056 .enable_mask = BIT(11),
1057 .hw.init = &(struct clk_init_data){
1059 .parent_names = gcc_pxo_pll8_cxo,
1061 .ops = &clk_rcg_ops,
1062 .flags = CLK_SET_RATE_GATE,
1067 static struct clk_branch gp2_clk = {
1071 .enable_reg = 0x2d64,
1072 .enable_mask = BIT(9),
1073 .hw.init = &(struct clk_init_data){
1075 .parent_names = (const char *[]){ "gp2_src" },
1077 .ops = &clk_branch_ops,
1078 .flags = CLK_SET_RATE_PARENT,
1083 static struct clk_branch pmem_clk = {
1089 .enable_reg = 0x25a0,
1090 .enable_mask = BIT(4),
1091 .hw.init = &(struct clk_init_data){
1093 .ops = &clk_branch_ops,
1094 .flags = CLK_IS_ROOT,
1099 static struct clk_rcg prng_src = {
1107 .parent_map = gcc_pxo_pll8_map,
1110 .hw.init = &(struct clk_init_data){
1112 .parent_names = gcc_pxo_pll8,
1114 .ops = &clk_rcg_ops,
1119 static struct clk_branch prng_clk = {
1121 .halt_check = BRANCH_HALT_VOTED,
1124 .enable_reg = 0x3080,
1125 .enable_mask = BIT(10),
1126 .hw.init = &(struct clk_init_data){
1128 .parent_names = (const char *[]){ "prng_src" },
1130 .ops = &clk_branch_ops,
1135 static const struct freq_tbl clk_tbl_sdc[] = {
1136 { 200000, P_PXO, 2, 2, 125 },
1137 { 400000, P_PLL8, 4, 1, 240 },
1138 { 16000000, P_PLL8, 4, 1, 6 },
1139 { 17070000, P_PLL8, 1, 2, 45 },
1140 { 20210000, P_PLL8, 1, 1, 19 },
1141 { 24000000, P_PLL8, 4, 1, 4 },
1142 { 48000000, P_PLL8, 4, 1, 2 },
1143 { 64000000, P_PLL8, 3, 1, 2 },
1144 { 96000000, P_PLL8, 4, 0, 0 },
1145 { 192000000, P_PLL8, 2, 0, 0 },
1149 static struct clk_rcg sdc1_src = {
1154 .mnctr_reset_bit = 7,
1155 .mnctr_mode_shift = 5,
1166 .parent_map = gcc_pxo_pll8_map,
1168 .freq_tbl = clk_tbl_sdc,
1170 .enable_reg = 0x282c,
1171 .enable_mask = BIT(11),
1172 .hw.init = &(struct clk_init_data){
1174 .parent_names = gcc_pxo_pll8,
1176 .ops = &clk_rcg_ops,
1177 .flags = CLK_SET_RATE_GATE,
1182 static struct clk_branch sdc1_clk = {
1186 .enable_reg = 0x282c,
1187 .enable_mask = BIT(9),
1188 .hw.init = &(struct clk_init_data){
1190 .parent_names = (const char *[]){ "sdc1_src" },
1192 .ops = &clk_branch_ops,
1193 .flags = CLK_SET_RATE_PARENT,
1198 static struct clk_rcg sdc3_src = {
1203 .mnctr_reset_bit = 7,
1204 .mnctr_mode_shift = 5,
1215 .parent_map = gcc_pxo_pll8_map,
1217 .freq_tbl = clk_tbl_sdc,
1219 .enable_reg = 0x286c,
1220 .enable_mask = BIT(11),
1221 .hw.init = &(struct clk_init_data){
1223 .parent_names = gcc_pxo_pll8,
1225 .ops = &clk_rcg_ops,
1226 .flags = CLK_SET_RATE_GATE,
1231 static struct clk_branch sdc3_clk = {
1235 .enable_reg = 0x286c,
1236 .enable_mask = BIT(9),
1237 .hw.init = &(struct clk_init_data){
1239 .parent_names = (const char *[]){ "sdc3_src" },
1241 .ops = &clk_branch_ops,
1242 .flags = CLK_SET_RATE_PARENT,
1247 static struct clk_branch sdc1_h_clk = {
1253 .enable_reg = 0x2820,
1254 .enable_mask = BIT(4),
1255 .hw.init = &(struct clk_init_data){
1256 .name = "sdc1_h_clk",
1257 .ops = &clk_branch_ops,
1258 .flags = CLK_IS_ROOT,
1263 static struct clk_branch sdc3_h_clk = {
1269 .enable_reg = 0x2860,
1270 .enable_mask = BIT(4),
1271 .hw.init = &(struct clk_init_data){
1272 .name = "sdc3_h_clk",
1273 .ops = &clk_branch_ops,
1274 .flags = CLK_IS_ROOT,
1279 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1280 { 105000, P_PXO, 1, 1, 256 },
1284 static struct clk_rcg tsif_ref_src = {
1289 .mnctr_reset_bit = 7,
1290 .mnctr_mode_shift = 5,
1301 .parent_map = gcc_pxo_pll8_map,
1303 .freq_tbl = clk_tbl_tsif_ref,
1305 .enable_reg = 0x2710,
1306 .enable_mask = BIT(11),
1307 .hw.init = &(struct clk_init_data){
1308 .name = "tsif_ref_src",
1309 .parent_names = gcc_pxo_pll8,
1311 .ops = &clk_rcg_ops,
1312 .flags = CLK_SET_RATE_GATE,
1317 static struct clk_branch tsif_ref_clk = {
1321 .enable_reg = 0x2710,
1322 .enable_mask = BIT(9),
1323 .hw.init = &(struct clk_init_data){
1324 .name = "tsif_ref_clk",
1325 .parent_names = (const char *[]){ "tsif_ref_src" },
1327 .ops = &clk_branch_ops,
1328 .flags = CLK_SET_RATE_PARENT,
1333 static struct clk_branch tsif_h_clk = {
1339 .enable_reg = 0x2700,
1340 .enable_mask = BIT(4),
1341 .hw.init = &(struct clk_init_data){
1342 .name = "tsif_h_clk",
1343 .ops = &clk_branch_ops,
1344 .flags = CLK_IS_ROOT,
1349 static struct clk_branch dma_bam_h_clk = {
1355 .enable_reg = 0x25c0,
1356 .enable_mask = BIT(4),
1357 .hw.init = &(struct clk_init_data){
1358 .name = "dma_bam_h_clk",
1359 .ops = &clk_branch_ops,
1360 .flags = CLK_IS_ROOT,
1365 static struct clk_branch adm0_clk = {
1367 .halt_check = BRANCH_HALT_VOTED,
1370 .enable_reg = 0x3080,
1371 .enable_mask = BIT(2),
1372 .hw.init = &(struct clk_init_data){
1374 .ops = &clk_branch_ops,
1375 .flags = CLK_IS_ROOT,
1380 static struct clk_branch adm0_pbus_clk = {
1384 .halt_check = BRANCH_HALT_VOTED,
1387 .enable_reg = 0x3080,
1388 .enable_mask = BIT(3),
1389 .hw.init = &(struct clk_init_data){
1390 .name = "adm0_pbus_clk",
1391 .ops = &clk_branch_ops,
1392 .flags = CLK_IS_ROOT,
1397 static struct clk_branch pmic_arb0_h_clk = {
1399 .halt_check = BRANCH_HALT_VOTED,
1402 .enable_reg = 0x3080,
1403 .enable_mask = BIT(8),
1404 .hw.init = &(struct clk_init_data){
1405 .name = "pmic_arb0_h_clk",
1406 .ops = &clk_branch_ops,
1407 .flags = CLK_IS_ROOT,
1412 static struct clk_branch pmic_arb1_h_clk = {
1414 .halt_check = BRANCH_HALT_VOTED,
1417 .enable_reg = 0x3080,
1418 .enable_mask = BIT(9),
1419 .hw.init = &(struct clk_init_data){
1420 .name = "pmic_arb1_h_clk",
1421 .ops = &clk_branch_ops,
1422 .flags = CLK_IS_ROOT,
1427 static struct clk_branch pmic_ssbi2_clk = {
1429 .halt_check = BRANCH_HALT_VOTED,
1432 .enable_reg = 0x3080,
1433 .enable_mask = BIT(7),
1434 .hw.init = &(struct clk_init_data){
1435 .name = "pmic_ssbi2_clk",
1436 .ops = &clk_branch_ops,
1437 .flags = CLK_IS_ROOT,
1442 static struct clk_branch rpm_msg_ram_h_clk = {
1446 .halt_check = BRANCH_HALT_VOTED,
1449 .enable_reg = 0x3080,
1450 .enable_mask = BIT(6),
1451 .hw.init = &(struct clk_init_data){
1452 .name = "rpm_msg_ram_h_clk",
1453 .ops = &clk_branch_ops,
1454 .flags = CLK_IS_ROOT,
1459 static const struct freq_tbl clk_tbl_pcie_ref[] = {
1460 { 100000000, P_PLL3, 12, 0, 0 },
1464 static struct clk_rcg pcie_ref_src = {
1472 .parent_map = gcc_pxo_pll3_map,
1474 .freq_tbl = clk_tbl_pcie_ref,
1476 .enable_reg = 0x3860,
1477 .enable_mask = BIT(11),
1478 .hw.init = &(struct clk_init_data){
1479 .name = "pcie_ref_src",
1480 .parent_names = gcc_pxo_pll3,
1482 .ops = &clk_rcg_ops,
1483 .flags = CLK_SET_RATE_GATE,
1488 static struct clk_branch pcie_ref_src_clk = {
1492 .enable_reg = 0x3860,
1493 .enable_mask = BIT(9),
1494 .hw.init = &(struct clk_init_data){
1495 .name = "pcie_ref_src_clk",
1496 .parent_names = (const char *[]){ "pcie_ref_src" },
1498 .ops = &clk_branch_ops,
1499 .flags = CLK_SET_RATE_PARENT,
1504 static struct clk_branch pcie_a_clk = {
1508 .enable_reg = 0x22c0,
1509 .enable_mask = BIT(4),
1510 .hw.init = &(struct clk_init_data){
1511 .name = "pcie_a_clk",
1512 .ops = &clk_branch_ops,
1513 .flags = CLK_IS_ROOT,
1518 static struct clk_branch pcie_aux_clk = {
1522 .enable_reg = 0x22c8,
1523 .enable_mask = BIT(4),
1524 .hw.init = &(struct clk_init_data){
1525 .name = "pcie_aux_clk",
1526 .ops = &clk_branch_ops,
1527 .flags = CLK_IS_ROOT,
1532 static struct clk_branch pcie_h_clk = {
1536 .enable_reg = 0x22cc,
1537 .enable_mask = BIT(4),
1538 .hw.init = &(struct clk_init_data){
1539 .name = "pcie_h_clk",
1540 .ops = &clk_branch_ops,
1541 .flags = CLK_IS_ROOT,
1546 static struct clk_branch pcie_phy_clk = {
1550 .enable_reg = 0x22d0,
1551 .enable_mask = BIT(4),
1552 .hw.init = &(struct clk_init_data){
1553 .name = "pcie_phy_clk",
1554 .ops = &clk_branch_ops,
1555 .flags = CLK_IS_ROOT,
1560 static struct clk_rcg pcie1_ref_src = {
1568 .parent_map = gcc_pxo_pll3_map,
1570 .freq_tbl = clk_tbl_pcie_ref,
1572 .enable_reg = 0x3aa0,
1573 .enable_mask = BIT(11),
1574 .hw.init = &(struct clk_init_data){
1575 .name = "pcie1_ref_src",
1576 .parent_names = gcc_pxo_pll3,
1578 .ops = &clk_rcg_ops,
1579 .flags = CLK_SET_RATE_GATE,
1584 static struct clk_branch pcie1_ref_src_clk = {
1588 .enable_reg = 0x3aa0,
1589 .enable_mask = BIT(9),
1590 .hw.init = &(struct clk_init_data){
1591 .name = "pcie1_ref_src_clk",
1592 .parent_names = (const char *[]){ "pcie1_ref_src" },
1594 .ops = &clk_branch_ops,
1595 .flags = CLK_SET_RATE_PARENT,
1600 static struct clk_branch pcie1_a_clk = {
1604 .enable_reg = 0x3a80,
1605 .enable_mask = BIT(4),
1606 .hw.init = &(struct clk_init_data){
1607 .name = "pcie1_a_clk",
1608 .ops = &clk_branch_ops,
1609 .flags = CLK_IS_ROOT,
1614 static struct clk_branch pcie1_aux_clk = {
1618 .enable_reg = 0x3a88,
1619 .enable_mask = BIT(4),
1620 .hw.init = &(struct clk_init_data){
1621 .name = "pcie1_aux_clk",
1622 .ops = &clk_branch_ops,
1623 .flags = CLK_IS_ROOT,
1628 static struct clk_branch pcie1_h_clk = {
1632 .enable_reg = 0x3a8c,
1633 .enable_mask = BIT(4),
1634 .hw.init = &(struct clk_init_data){
1635 .name = "pcie1_h_clk",
1636 .ops = &clk_branch_ops,
1637 .flags = CLK_IS_ROOT,
1642 static struct clk_branch pcie1_phy_clk = {
1646 .enable_reg = 0x3a90,
1647 .enable_mask = BIT(4),
1648 .hw.init = &(struct clk_init_data){
1649 .name = "pcie1_phy_clk",
1650 .ops = &clk_branch_ops,
1651 .flags = CLK_IS_ROOT,
1656 static struct clk_rcg pcie2_ref_src = {
1664 .parent_map = gcc_pxo_pll3_map,
1666 .freq_tbl = clk_tbl_pcie_ref,
1668 .enable_reg = 0x3ae0,
1669 .enable_mask = BIT(11),
1670 .hw.init = &(struct clk_init_data){
1671 .name = "pcie2_ref_src",
1672 .parent_names = gcc_pxo_pll3,
1674 .ops = &clk_rcg_ops,
1675 .flags = CLK_SET_RATE_GATE,
1680 static struct clk_branch pcie2_ref_src_clk = {
1684 .enable_reg = 0x3ae0,
1685 .enable_mask = BIT(9),
1686 .hw.init = &(struct clk_init_data){
1687 .name = "pcie2_ref_src_clk",
1688 .parent_names = (const char *[]){ "pcie2_ref_src" },
1690 .ops = &clk_branch_ops,
1691 .flags = CLK_SET_RATE_PARENT,
1696 static struct clk_branch pcie2_a_clk = {
1700 .enable_reg = 0x3ac0,
1701 .enable_mask = BIT(4),
1702 .hw.init = &(struct clk_init_data){
1703 .name = "pcie2_a_clk",
1704 .ops = &clk_branch_ops,
1705 .flags = CLK_IS_ROOT,
1710 static struct clk_branch pcie2_aux_clk = {
1714 .enable_reg = 0x3ac8,
1715 .enable_mask = BIT(4),
1716 .hw.init = &(struct clk_init_data){
1717 .name = "pcie2_aux_clk",
1718 .ops = &clk_branch_ops,
1719 .flags = CLK_IS_ROOT,
1724 static struct clk_branch pcie2_h_clk = {
1728 .enable_reg = 0x3acc,
1729 .enable_mask = BIT(4),
1730 .hw.init = &(struct clk_init_data){
1731 .name = "pcie2_h_clk",
1732 .ops = &clk_branch_ops,
1733 .flags = CLK_IS_ROOT,
1738 static struct clk_branch pcie2_phy_clk = {
1742 .enable_reg = 0x3ad0,
1743 .enable_mask = BIT(4),
1744 .hw.init = &(struct clk_init_data){
1745 .name = "pcie2_phy_clk",
1746 .ops = &clk_branch_ops,
1747 .flags = CLK_IS_ROOT,
1752 static const struct freq_tbl clk_tbl_sata_ref[] = {
1753 { 100000000, P_PLL3, 12, 0, 0 },
1757 static struct clk_rcg sata_ref_src = {
1765 .parent_map = gcc_pxo_pll3_sata_map,
1767 .freq_tbl = clk_tbl_sata_ref,
1769 .enable_reg = 0x2c08,
1770 .enable_mask = BIT(7),
1771 .hw.init = &(struct clk_init_data){
1772 .name = "sata_ref_src",
1773 .parent_names = gcc_pxo_pll3,
1775 .ops = &clk_rcg_ops,
1776 .flags = CLK_SET_RATE_GATE,
1781 static struct clk_branch sata_rxoob_clk = {
1785 .enable_reg = 0x2c0c,
1786 .enable_mask = BIT(4),
1787 .hw.init = &(struct clk_init_data){
1788 .name = "sata_rxoob_clk",
1789 .parent_names = (const char *[]){ "sata_ref_src" },
1791 .ops = &clk_branch_ops,
1792 .flags = CLK_SET_RATE_PARENT,
1797 static struct clk_branch sata_pmalive_clk = {
1801 .enable_reg = 0x2c10,
1802 .enable_mask = BIT(4),
1803 .hw.init = &(struct clk_init_data){
1804 .name = "sata_pmalive_clk",
1805 .parent_names = (const char *[]){ "sata_ref_src" },
1807 .ops = &clk_branch_ops,
1808 .flags = CLK_SET_RATE_PARENT,
1813 static struct clk_branch sata_phy_ref_clk = {
1817 .enable_reg = 0x2c14,
1818 .enable_mask = BIT(4),
1819 .hw.init = &(struct clk_init_data){
1820 .name = "sata_phy_ref_clk",
1821 .parent_names = (const char *[]){ "pxo" },
1823 .ops = &clk_branch_ops,
1828 static struct clk_branch sata_a_clk = {
1832 .enable_reg = 0x2c20,
1833 .enable_mask = BIT(4),
1834 .hw.init = &(struct clk_init_data){
1835 .name = "sata_a_clk",
1836 .ops = &clk_branch_ops,
1837 .flags = CLK_IS_ROOT,
1842 static struct clk_branch sata_h_clk = {
1846 .enable_reg = 0x2c00,
1847 .enable_mask = BIT(4),
1848 .hw.init = &(struct clk_init_data){
1849 .name = "sata_h_clk",
1850 .ops = &clk_branch_ops,
1851 .flags = CLK_IS_ROOT,
1856 static struct clk_branch sfab_sata_s_h_clk = {
1860 .enable_reg = 0x2480,
1861 .enable_mask = BIT(4),
1862 .hw.init = &(struct clk_init_data){
1863 .name = "sfab_sata_s_h_clk",
1864 .ops = &clk_branch_ops,
1865 .flags = CLK_IS_ROOT,
1870 static struct clk_branch sata_phy_cfg_clk = {
1874 .enable_reg = 0x2c40,
1875 .enable_mask = BIT(4),
1876 .hw.init = &(struct clk_init_data){
1877 .name = "sata_phy_cfg_clk",
1878 .ops = &clk_branch_ops,
1879 .flags = CLK_IS_ROOT,
1884 static const struct freq_tbl clk_tbl_usb30_master[] = {
1885 { 125000000, P_PLL0, 1, 5, 32 },
1889 static struct clk_rcg usb30_master_clk_src = {
1894 .mnctr_reset_bit = 7,
1895 .mnctr_mode_shift = 5,
1906 .parent_map = gcc_pxo_pll8_pll0,
1908 .freq_tbl = clk_tbl_usb30_master,
1910 .enable_reg = 0x3b2c,
1911 .enable_mask = BIT(11),
1912 .hw.init = &(struct clk_init_data){
1913 .name = "usb30_master_ref_src",
1914 .parent_names = gcc_pxo_pll8_pll0_map,
1916 .ops = &clk_rcg_ops,
1917 .flags = CLK_SET_RATE_GATE,
1922 static struct clk_branch usb30_0_branch_clk = {
1926 .enable_reg = 0x3b24,
1927 .enable_mask = BIT(4),
1928 .hw.init = &(struct clk_init_data){
1929 .name = "usb30_0_branch_clk",
1930 .parent_names = (const char *[]){ "usb30_master_ref_src", },
1932 .ops = &clk_branch_ops,
1933 .flags = CLK_SET_RATE_PARENT,
1938 static struct clk_branch usb30_1_branch_clk = {
1942 .enable_reg = 0x3b34,
1943 .enable_mask = BIT(4),
1944 .hw.init = &(struct clk_init_data){
1945 .name = "usb30_1_branch_clk",
1946 .parent_names = (const char *[]){ "usb30_master_ref_src", },
1948 .ops = &clk_branch_ops,
1949 .flags = CLK_SET_RATE_PARENT,
1954 static const struct freq_tbl clk_tbl_usb30_utmi[] = {
1955 { 60000000, P_PLL8, 1, 5, 32 },
1959 static struct clk_rcg usb30_utmi_clk = {
1964 .mnctr_reset_bit = 7,
1965 .mnctr_mode_shift = 5,
1976 .parent_map = gcc_pxo_pll8_pll0,
1978 .freq_tbl = clk_tbl_usb30_utmi,
1980 .enable_reg = 0x3b44,
1981 .enable_mask = BIT(11),
1982 .hw.init = &(struct clk_init_data){
1983 .name = "usb30_utmi_clk",
1984 .parent_names = gcc_pxo_pll8_pll0_map,
1986 .ops = &clk_rcg_ops,
1987 .flags = CLK_SET_RATE_GATE,
1992 static struct clk_branch usb30_0_utmi_clk_ctl = {
1996 .enable_reg = 0x3b48,
1997 .enable_mask = BIT(4),
1998 .hw.init = &(struct clk_init_data){
1999 .name = "usb30_0_utmi_clk_ctl",
2000 .parent_names = (const char *[]){ "usb30_utmi_clk", },
2002 .ops = &clk_branch_ops,
2003 .flags = CLK_SET_RATE_PARENT,
2008 static struct clk_branch usb30_1_utmi_clk_ctl = {
2012 .enable_reg = 0x3b4c,
2013 .enable_mask = BIT(4),
2014 .hw.init = &(struct clk_init_data){
2015 .name = "usb30_1_utmi_clk_ctl",
2016 .parent_names = (const char *[]){ "usb30_utmi_clk", },
2018 .ops = &clk_branch_ops,
2019 .flags = CLK_SET_RATE_PARENT,
2024 static const struct freq_tbl clk_tbl_usb[] = {
2025 { 60000000, P_PLL8, 1, 5, 32 },
2029 static struct clk_rcg usb_hs1_xcvr_clk_src = {
2034 .mnctr_reset_bit = 7,
2035 .mnctr_mode_shift = 5,
2046 .parent_map = gcc_pxo_pll8_pll0,
2048 .freq_tbl = clk_tbl_usb,
2050 .enable_reg = 0x2968,
2051 .enable_mask = BIT(11),
2052 .hw.init = &(struct clk_init_data){
2053 .name = "usb_hs1_xcvr_src",
2054 .parent_names = gcc_pxo_pll8_pll0_map,
2056 .ops = &clk_rcg_ops,
2057 .flags = CLK_SET_RATE_GATE,
2062 static struct clk_branch usb_hs1_xcvr_clk = {
2066 .enable_reg = 0x290c,
2067 .enable_mask = BIT(9),
2068 .hw.init = &(struct clk_init_data){
2069 .name = "usb_hs1_xcvr_clk",
2070 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
2072 .ops = &clk_branch_ops,
2073 .flags = CLK_SET_RATE_PARENT,
2078 static struct clk_branch usb_hs1_h_clk = {
2084 .enable_reg = 0x2900,
2085 .enable_mask = BIT(4),
2086 .hw.init = &(struct clk_init_data){
2087 .name = "usb_hs1_h_clk",
2088 .ops = &clk_branch_ops,
2089 .flags = CLK_IS_ROOT,
2094 static struct clk_rcg usb_fs1_xcvr_clk_src = {
2099 .mnctr_reset_bit = 7,
2100 .mnctr_mode_shift = 5,
2111 .parent_map = gcc_pxo_pll8_pll0,
2113 .freq_tbl = clk_tbl_usb,
2115 .enable_reg = 0x2968,
2116 .enable_mask = BIT(11),
2117 .hw.init = &(struct clk_init_data){
2118 .name = "usb_fs1_xcvr_src",
2119 .parent_names = gcc_pxo_pll8_pll0_map,
2121 .ops = &clk_rcg_ops,
2122 .flags = CLK_SET_RATE_GATE,
2127 static struct clk_branch usb_fs1_xcvr_clk = {
2131 .enable_reg = 0x2968,
2132 .enable_mask = BIT(9),
2133 .hw.init = &(struct clk_init_data){
2134 .name = "usb_fs1_xcvr_clk",
2135 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2137 .ops = &clk_branch_ops,
2138 .flags = CLK_SET_RATE_PARENT,
2143 static struct clk_branch usb_fs1_sys_clk = {
2147 .enable_reg = 0x296c,
2148 .enable_mask = BIT(4),
2149 .hw.init = &(struct clk_init_data){
2150 .name = "usb_fs1_sys_clk",
2151 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2153 .ops = &clk_branch_ops,
2154 .flags = CLK_SET_RATE_PARENT,
2159 static struct clk_branch usb_fs1_h_clk = {
2163 .enable_reg = 0x2960,
2164 .enable_mask = BIT(4),
2165 .hw.init = &(struct clk_init_data){
2166 .name = "usb_fs1_h_clk",
2167 .ops = &clk_branch_ops,
2168 .flags = CLK_IS_ROOT,
2173 static struct clk_regmap *gcc_ipq806x_clks[] = {
2174 [PLL0] = &pll0.clkr,
2175 [PLL0_VOTE] = &pll0_vote,
2176 [PLL3] = &pll3.clkr,
2177 [PLL4_VOTE] = &pll4_vote,
2178 [PLL8] = &pll8.clkr,
2179 [PLL8_VOTE] = &pll8_vote,
2180 [PLL14] = &pll14.clkr,
2181 [PLL14_VOTE] = &pll14_vote,
2182 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2183 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2184 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2185 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2186 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2187 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2188 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2189 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2190 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2191 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2192 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2193 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2194 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2195 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2196 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2197 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2198 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2199 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2200 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2201 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2202 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2203 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2204 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2205 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2206 [GP0_SRC] = &gp0_src.clkr,
2207 [GP0_CLK] = &gp0_clk.clkr,
2208 [GP1_SRC] = &gp1_src.clkr,
2209 [GP1_CLK] = &gp1_clk.clkr,
2210 [GP2_SRC] = &gp2_src.clkr,
2211 [GP2_CLK] = &gp2_clk.clkr,
2212 [PMEM_A_CLK] = &pmem_clk.clkr,
2213 [PRNG_SRC] = &prng_src.clkr,
2214 [PRNG_CLK] = &prng_clk.clkr,
2215 [SDC1_SRC] = &sdc1_src.clkr,
2216 [SDC1_CLK] = &sdc1_clk.clkr,
2217 [SDC3_SRC] = &sdc3_src.clkr,
2218 [SDC3_CLK] = &sdc3_clk.clkr,
2219 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2220 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2221 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
2222 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2223 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2224 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2225 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2226 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2227 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2228 [TSIF_H_CLK] = &tsif_h_clk.clkr,
2229 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2230 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2231 [ADM0_CLK] = &adm0_clk.clkr,
2232 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2233 [PCIE_A_CLK] = &pcie_a_clk.clkr,
2234 [PCIE_AUX_CLK] = &pcie_aux_clk.clkr,
2235 [PCIE_H_CLK] = &pcie_h_clk.clkr,
2236 [PCIE_PHY_CLK] = &pcie_phy_clk.clkr,
2237 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
2238 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2239 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2240 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2241 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2242 [SATA_H_CLK] = &sata_h_clk.clkr,
2243 [SATA_CLK_SRC] = &sata_ref_src.clkr,
2244 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
2245 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
2246 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
2247 [SATA_A_CLK] = &sata_a_clk.clkr,
2248 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
2249 [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr,
2250 [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr,
2251 [PCIE_1_A_CLK] = &pcie1_a_clk.clkr,
2252 [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr,
2253 [PCIE_1_H_CLK] = &pcie1_h_clk.clkr,
2254 [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr,
2255 [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr,
2256 [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr,
2257 [PCIE_2_A_CLK] = &pcie2_a_clk.clkr,
2258 [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr,
2259 [PCIE_2_H_CLK] = &pcie2_h_clk.clkr,
2260 [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr,
2261 [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr,
2262 [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr,
2263 [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr,
2264 [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr,
2265 [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr,
2266 [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr,
2267 [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr,
2268 [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr,
2269 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2270 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr,
2271 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2272 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2273 [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
2274 [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
2275 [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
2278 static const struct qcom_reset_map gcc_ipq806x_resets[] = {
2279 [QDSS_STM_RESET] = { 0x2060, 6 },
2280 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2281 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2282 [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
2283 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
2284 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
2285 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2286 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2287 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
2288 [ADM0_C2_RESET] = { 0x220c, 4 },
2289 [ADM0_C1_RESET] = { 0x220c, 3 },
2290 [ADM0_C0_RESET] = { 0x220c, 2 },
2291 [ADM0_PBUS_RESET] = { 0x220c, 1 },
2292 [ADM0_RESET] = { 0x220c, 0 },
2293 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
2294 [QDSS_POR_RESET] = { 0x2260, 4 },
2295 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
2296 [QDSS_HRESET_RESET] = { 0x2260, 2 },
2297 [QDSS_AXI_RESET] = { 0x2260, 1 },
2298 [QDSS_DBG_RESET] = { 0x2260, 0 },
2299 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
2300 [SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
2301 [PCIE_EXT_RESET] = { 0x22dc, 6 },
2302 [PCIE_PHY_RESET] = { 0x22dc, 5 },
2303 [PCIE_PCI_RESET] = { 0x22dc, 4 },
2304 [PCIE_POR_RESET] = { 0x22dc, 3 },
2305 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
2306 [PCIE_ACLK_RESET] = { 0x22dc, 0 },
2307 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
2308 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2309 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2310 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2311 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
2312 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2313 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2314 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2315 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2316 [DFAB_ARB0_RESET] = { 0x2560, 7 },
2317 [DFAB_ARB1_RESET] = { 0x2564, 7 },
2318 [PPSS_PROC_RESET] = { 0x2594, 1 },
2319 [PPSS_RESET] = { 0x2594, 0 },
2320 [DMA_BAM_RESET] = { 0x25c0, 7 },
2321 [SPS_TIC_H_RESET] = { 0x2600, 7 },
2322 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2323 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2324 [TSIF_H_RESET] = { 0x2700, 7 },
2325 [CE1_H_RESET] = { 0x2720, 7 },
2326 [CE1_CORE_RESET] = { 0x2724, 7 },
2327 [CE1_SLEEP_RESET] = { 0x2728, 7 },
2328 [CE2_H_RESET] = { 0x2740, 7 },
2329 [CE2_CORE_RESET] = { 0x2744, 7 },
2330 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2331 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2332 [RPM_PROC_RESET] = { 0x27c0, 7 },
2333 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2334 [SDC1_RESET] = { 0x2830, 0 },
2335 [SDC2_RESET] = { 0x2850, 0 },
2336 [SDC3_RESET] = { 0x2870, 0 },
2337 [SDC4_RESET] = { 0x2890, 0 },
2338 [USB_HS1_RESET] = { 0x2910, 0 },
2339 [USB_HSIC_RESET] = { 0x2934, 0 },
2340 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2341 [USB_FS1_RESET] = { 0x2974, 0 },
2342 [GSBI1_RESET] = { 0x29dc, 0 },
2343 [GSBI2_RESET] = { 0x29fc, 0 },
2344 [GSBI3_RESET] = { 0x2a1c, 0 },
2345 [GSBI4_RESET] = { 0x2a3c, 0 },
2346 [GSBI5_RESET] = { 0x2a5c, 0 },
2347 [GSBI6_RESET] = { 0x2a7c, 0 },
2348 [GSBI7_RESET] = { 0x2a9c, 0 },
2349 [SPDM_RESET] = { 0x2b6c, 0 },
2350 [SEC_CTRL_RESET] = { 0x2b80, 7 },
2351 [TLMM_H_RESET] = { 0x2ba0, 7 },
2352 [SFAB_SATA_M_RESET] = { 0x2c18, 0 },
2353 [SATA_RESET] = { 0x2c1c, 0 },
2354 [TSSC_RESET] = { 0x2ca0, 7 },
2355 [PDM_RESET] = { 0x2cc0, 12 },
2356 [MPM_H_RESET] = { 0x2da0, 7 },
2357 [MPM_RESET] = { 0x2da4, 0 },
2358 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2359 [PRNG_RESET] = { 0x2e80, 12 },
2360 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
2361 [SFAB_CE3_S_RESET] = { 0x36c8, 0 },
2362 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
2363 [PCIE_1_M_RESET] = { 0x3a98, 1 },
2364 [PCIE_1_S_RESET] = { 0x3a98, 0 },
2365 [PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
2366 [PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
2367 [PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
2368 [PCIE_1_POR_RESET] = { 0x3a9c, 3 },
2369 [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
2370 [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
2371 [PCIE_2_M_RESET] = { 0x3ad8, 1 },
2372 [PCIE_2_S_RESET] = { 0x3ad8, 0 },
2373 [PCIE_2_EXT_RESET] = { 0x3adc, 6 },
2374 [PCIE_2_PHY_RESET] = { 0x3adc, 5 },
2375 [PCIE_2_PCI_RESET] = { 0x3adc, 4 },
2376 [PCIE_2_POR_RESET] = { 0x3adc, 3 },
2377 [PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
2378 [PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
2379 [SFAB_USB30_S_RESET] = { 0x3b54, 1 },
2380 [SFAB_USB30_M_RESET] = { 0x3b54, 0 },
2381 [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
2382 [USB30_0_MASTER_RESET] = { 0x3b50, 4 },
2383 [USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
2384 [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
2385 [USB30_0_POWERON_RESET] = { 0x3b50, 1 },
2386 [USB30_0_PHY_RESET] = { 0x3b50, 0 },
2387 [USB30_1_MASTER_RESET] = { 0x3b58, 4 },
2388 [USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
2389 [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
2390 [USB30_1_POWERON_RESET] = { 0x3b58, 1 },
2391 [USB30_1_PHY_RESET] = { 0x3b58, 0 },
2392 [NSSFB0_RESET] = { 0x3b60, 6 },
2393 [NSSFB1_RESET] = { 0x3b60, 7 },
2396 static const struct regmap_config gcc_ipq806x_regmap_config = {
2400 .max_register = 0x3e40,
2404 static const struct qcom_cc_desc gcc_ipq806x_desc = {
2405 .config = &gcc_ipq806x_regmap_config,
2406 .clks = gcc_ipq806x_clks,
2407 .num_clks = ARRAY_SIZE(gcc_ipq806x_clks),
2408 .resets = gcc_ipq806x_resets,
2409 .num_resets = ARRAY_SIZE(gcc_ipq806x_resets),
2412 static const struct of_device_id gcc_ipq806x_match_table[] = {
2413 { .compatible = "qcom,gcc-ipq8064" },
2416 MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);
2418 static int gcc_ipq806x_probe(struct platform_device *pdev)
2421 struct device *dev = &pdev->dev;
2423 /* Temporary until RPM clocks supported */
2424 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000);
2426 return PTR_ERR(clk);
2428 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 25000000);
2430 return PTR_ERR(clk);
2432 return qcom_cc_probe(pdev, &gcc_ipq806x_desc);
2435 static int gcc_ipq806x_remove(struct platform_device *pdev)
2437 qcom_cc_remove(pdev);
2441 static struct platform_driver gcc_ipq806x_driver = {
2442 .probe = gcc_ipq806x_probe,
2443 .remove = gcc_ipq806x_remove,
2445 .name = "gcc-ipq806x",
2446 .of_match_table = gcc_ipq806x_match_table,
2450 static int __init gcc_ipq806x_init(void)
2452 return platform_driver_register(&gcc_ipq806x_driver);
2454 core_initcall(gcc_ipq806x_init);
2456 static void __exit gcc_ipq806x_exit(void)
2458 platform_driver_unregister(&gcc_ipq806x_driver);
2460 module_exit(gcc_ipq806x_exit);
2462 MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver");
2463 MODULE_LICENSE("GPL v2");
2464 MODULE_ALIAS("platform:gcc-ipq806x");