2 * Copyright 2015 Linaro Limited
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
26 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
50 static const struct parent_map gcc_xo_gpll0_map[] = {
55 static const char * const gcc_xo_gpll0[] = {
60 static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
66 static const char * const gcc_xo_gpll0_bimc[] = {
72 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {
79 static const char * const gcc_xo_gpll0a_gpll1_gpll2a[] = {
86 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
92 static const char * const gcc_xo_gpll0_gpll2[] = {
98 static const struct parent_map gcc_xo_gpll0a_map[] = {
103 static const char * const gcc_xo_gpll0a[] = {
108 static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
115 static const char * const gcc_xo_gpll0_gpll1a_sleep[] = {
122 static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
128 static const char * const gcc_xo_gpll0_gpll1a[] = {
134 static const struct parent_map gcc_xo_dsibyte_map[] = {
136 { P_DSI0_PHYPLL_BYTE, 2 },
139 static const char * const gcc_xo_dsibyte[] = {
144 static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
147 { P_DSI0_PHYPLL_BYTE, 1 },
150 static const char * const gcc_xo_gpll0a_dsibyte[] = {
156 static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = {
159 { P_DSI0_PHYPLL_DSI, 2 },
162 static const char * const gcc_xo_gpll0_dsiphy[] = {
168 static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
171 { P_DSI0_PHYPLL_DSI, 1 },
174 static const char * const gcc_xo_gpll0a_dsiphy[] = {
180 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = {
187 static const char * const gcc_xo_gpll0a_gpll1_gpll2[] = {
194 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
196 static struct clk_pll gpll0 = {
200 .config_reg = 0x21014,
202 .status_reg = 0x2101c,
204 .clkr.hw.init = &(struct clk_init_data){
206 .parent_names = (const char *[]){ "xo" },
212 static struct clk_regmap gpll0_vote = {
213 .enable_reg = 0x45000,
214 .enable_mask = BIT(0),
215 .hw.init = &(struct clk_init_data){
216 .name = "gpll0_vote",
217 .parent_names = (const char *[]){ "gpll0" },
219 .ops = &clk_pll_vote_ops,
223 static struct clk_pll gpll1 = {
227 .config_reg = 0x20014,
229 .status_reg = 0x2001c,
231 .clkr.hw.init = &(struct clk_init_data){
233 .parent_names = (const char *[]){ "xo" },
239 static struct clk_regmap gpll1_vote = {
240 .enable_reg = 0x45000,
241 .enable_mask = BIT(1),
242 .hw.init = &(struct clk_init_data){
243 .name = "gpll1_vote",
244 .parent_names = (const char *[]){ "gpll1" },
246 .ops = &clk_pll_vote_ops,
250 static struct clk_pll gpll2 = {
254 .config_reg = 0x4a014,
256 .status_reg = 0x4a01c,
258 .clkr.hw.init = &(struct clk_init_data){
260 .parent_names = (const char *[]){ "xo" },
266 static struct clk_regmap gpll2_vote = {
267 .enable_reg = 0x45000,
268 .enable_mask = BIT(2),
269 .hw.init = &(struct clk_init_data){
270 .name = "gpll2_vote",
271 .parent_names = (const char *[]){ "gpll2" },
273 .ops = &clk_pll_vote_ops,
277 static struct clk_pll bimc_pll = {
281 .config_reg = 0x23014,
283 .status_reg = 0x2301c,
285 .clkr.hw.init = &(struct clk_init_data){
287 .parent_names = (const char *[]){ "xo" },
293 static struct clk_regmap bimc_pll_vote = {
294 .enable_reg = 0x45000,
295 .enable_mask = BIT(3),
296 .hw.init = &(struct clk_init_data){
297 .name = "bimc_pll_vote",
298 .parent_names = (const char *[]){ "bimc_pll" },
300 .ops = &clk_pll_vote_ops,
304 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
307 .parent_map = gcc_xo_gpll0_bimc_map,
308 .clkr.hw.init = &(struct clk_init_data){
309 .name = "pcnoc_bfdcd_clk_src",
310 .parent_names = gcc_xo_gpll0_bimc,
312 .ops = &clk_rcg2_ops,
316 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
319 .parent_map = gcc_xo_gpll0_bimc_map,
320 .clkr.hw.init = &(struct clk_init_data){
321 .name = "system_noc_bfdcd_clk_src",
322 .parent_names = gcc_xo_gpll0_bimc,
324 .ops = &clk_rcg2_ops,
328 static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
329 F(40000000, P_GPLL0, 10, 1, 2),
330 F(80000000, P_GPLL0, 10, 0, 0),
334 static struct clk_rcg2 camss_ahb_clk_src = {
338 .parent_map = gcc_xo_gpll0_map,
339 .freq_tbl = ftbl_gcc_camss_ahb_clk,
340 .clkr.hw.init = &(struct clk_init_data){
341 .name = "camss_ahb_clk_src",
342 .parent_names = gcc_xo_gpll0,
344 .ops = &clk_rcg2_ops,
348 static const struct freq_tbl ftbl_apss_ahb_clk[] = {
349 F(19200000, P_XO, 1, 0, 0),
350 F(50000000, P_GPLL0, 16, 0, 0),
351 F(100000000, P_GPLL0, 8, 0, 0),
352 F(133330000, P_GPLL0, 6, 0, 0),
356 static struct clk_rcg2 apss_ahb_clk_src = {
359 .parent_map = gcc_xo_gpll0_map,
360 .freq_tbl = ftbl_apss_ahb_clk,
361 .clkr.hw.init = &(struct clk_init_data){
362 .name = "apss_ahb_clk_src",
363 .parent_names = gcc_xo_gpll0,
365 .ops = &clk_rcg2_ops,
369 static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
370 F(100000000, P_GPLL0, 8, 0, 0),
371 F(200000000, P_GPLL0, 4, 0, 0),
375 static struct clk_rcg2 csi0_clk_src = {
378 .parent_map = gcc_xo_gpll0_map,
379 .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
380 .clkr.hw.init = &(struct clk_init_data){
381 .name = "csi0_clk_src",
382 .parent_names = gcc_xo_gpll0,
384 .ops = &clk_rcg2_ops,
388 static struct clk_rcg2 csi1_clk_src = {
391 .parent_map = gcc_xo_gpll0_map,
392 .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
393 .clkr.hw.init = &(struct clk_init_data){
394 .name = "csi1_clk_src",
395 .parent_names = gcc_xo_gpll0,
397 .ops = &clk_rcg2_ops,
401 static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
402 F(19200000, P_XO, 1, 0, 0),
403 F(50000000, P_GPLL0_AUX, 16, 0, 0),
404 F(80000000, P_GPLL0_AUX, 10, 0, 0),
405 F(100000000, P_GPLL0_AUX, 8, 0, 0),
406 F(160000000, P_GPLL0_AUX, 5, 0, 0),
407 F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
408 F(200000000, P_GPLL0_AUX, 4, 0, 0),
409 F(266670000, P_GPLL0_AUX, 3, 0, 0),
410 F(294912000, P_GPLL1, 3, 0, 0),
411 F(310000000, P_GPLL2, 3, 0, 0),
412 F(400000000, P_GPLL0_AUX, 2, 0, 0),
416 static struct clk_rcg2 gfx3d_clk_src = {
419 .parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map,
420 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
421 .clkr.hw.init = &(struct clk_init_data){
422 .name = "gfx3d_clk_src",
423 .parent_names = gcc_xo_gpll0a_gpll1_gpll2a,
425 .ops = &clk_rcg2_ops,
429 static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
430 F(50000000, P_GPLL0, 16, 0, 0),
431 F(80000000, P_GPLL0, 10, 0, 0),
432 F(100000000, P_GPLL0, 8, 0, 0),
433 F(160000000, P_GPLL0, 5, 0, 0),
434 F(177780000, P_GPLL0, 4.5, 0, 0),
435 F(200000000, P_GPLL0, 4, 0, 0),
436 F(266670000, P_GPLL0, 3, 0, 0),
437 F(320000000, P_GPLL0, 2.5, 0, 0),
438 F(400000000, P_GPLL0, 2, 0, 0),
439 F(465000000, P_GPLL2, 2, 0, 0),
443 static struct clk_rcg2 vfe0_clk_src = {
446 .parent_map = gcc_xo_gpll0_gpll2_map,
447 .freq_tbl = ftbl_gcc_camss_vfe0_clk,
448 .clkr.hw.init = &(struct clk_init_data){
449 .name = "vfe0_clk_src",
450 .parent_names = gcc_xo_gpll0_gpll2,
452 .ops = &clk_rcg2_ops,
456 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
457 F(19200000, P_XO, 1, 0, 0),
458 F(50000000, P_GPLL0, 16, 0, 0),
462 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
465 .parent_map = gcc_xo_gpll0_map,
466 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
467 .clkr.hw.init = &(struct clk_init_data){
468 .name = "blsp1_qup1_i2c_apps_clk_src",
469 .parent_names = gcc_xo_gpll0,
471 .ops = &clk_rcg2_ops,
475 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
476 F(960000, P_XO, 10, 1, 2),
477 F(4800000, P_XO, 4, 0, 0),
478 F(9600000, P_XO, 2, 0, 0),
479 F(16000000, P_GPLL0, 10, 1, 5),
480 F(19200000, P_XO, 1, 0, 0),
481 F(25000000, P_GPLL0, 16, 1, 2),
482 F(50000000, P_GPLL0, 16, 0, 0),
486 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
490 .parent_map = gcc_xo_gpll0_map,
491 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
492 .clkr.hw.init = &(struct clk_init_data){
493 .name = "blsp1_qup1_spi_apps_clk_src",
494 .parent_names = gcc_xo_gpll0,
496 .ops = &clk_rcg2_ops,
500 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
503 .parent_map = gcc_xo_gpll0_map,
504 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
505 .clkr.hw.init = &(struct clk_init_data){
506 .name = "blsp1_qup2_i2c_apps_clk_src",
507 .parent_names = gcc_xo_gpll0,
509 .ops = &clk_rcg2_ops,
513 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
517 .parent_map = gcc_xo_gpll0_map,
518 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
519 .clkr.hw.init = &(struct clk_init_data){
520 .name = "blsp1_qup2_spi_apps_clk_src",
521 .parent_names = gcc_xo_gpll0,
523 .ops = &clk_rcg2_ops,
527 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
530 .parent_map = gcc_xo_gpll0_map,
531 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
532 .clkr.hw.init = &(struct clk_init_data){
533 .name = "blsp1_qup3_i2c_apps_clk_src",
534 .parent_names = gcc_xo_gpll0,
536 .ops = &clk_rcg2_ops,
540 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
544 .parent_map = gcc_xo_gpll0_map,
545 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
546 .clkr.hw.init = &(struct clk_init_data){
547 .name = "blsp1_qup3_spi_apps_clk_src",
548 .parent_names = gcc_xo_gpll0,
550 .ops = &clk_rcg2_ops,
554 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
557 .parent_map = gcc_xo_gpll0_map,
558 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
559 .clkr.hw.init = &(struct clk_init_data){
560 .name = "blsp1_qup4_i2c_apps_clk_src",
561 .parent_names = gcc_xo_gpll0,
563 .ops = &clk_rcg2_ops,
567 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
571 .parent_map = gcc_xo_gpll0_map,
572 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
573 .clkr.hw.init = &(struct clk_init_data){
574 .name = "blsp1_qup4_spi_apps_clk_src",
575 .parent_names = gcc_xo_gpll0,
577 .ops = &clk_rcg2_ops,
581 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
584 .parent_map = gcc_xo_gpll0_map,
585 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
586 .clkr.hw.init = &(struct clk_init_data){
587 .name = "blsp1_qup5_i2c_apps_clk_src",
588 .parent_names = gcc_xo_gpll0,
590 .ops = &clk_rcg2_ops,
594 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
598 .parent_map = gcc_xo_gpll0_map,
599 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
600 .clkr.hw.init = &(struct clk_init_data){
601 .name = "blsp1_qup5_spi_apps_clk_src",
602 .parent_names = gcc_xo_gpll0,
604 .ops = &clk_rcg2_ops,
608 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
611 .parent_map = gcc_xo_gpll0_map,
612 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
613 .clkr.hw.init = &(struct clk_init_data){
614 .name = "blsp1_qup6_i2c_apps_clk_src",
615 .parent_names = gcc_xo_gpll0,
617 .ops = &clk_rcg2_ops,
621 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
625 .parent_map = gcc_xo_gpll0_map,
626 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
627 .clkr.hw.init = &(struct clk_init_data){
628 .name = "blsp1_qup6_spi_apps_clk_src",
629 .parent_names = gcc_xo_gpll0,
631 .ops = &clk_rcg2_ops,
635 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
636 F(3686400, P_GPLL0, 1, 72, 15625),
637 F(7372800, P_GPLL0, 1, 144, 15625),
638 F(14745600, P_GPLL0, 1, 288, 15625),
639 F(16000000, P_GPLL0, 10, 1, 5),
640 F(19200000, P_XO, 1, 0, 0),
641 F(24000000, P_GPLL0, 1, 3, 100),
642 F(25000000, P_GPLL0, 16, 1, 2),
643 F(32000000, P_GPLL0, 1, 1, 25),
644 F(40000000, P_GPLL0, 1, 1, 20),
645 F(46400000, P_GPLL0, 1, 29, 500),
646 F(48000000, P_GPLL0, 1, 3, 50),
647 F(51200000, P_GPLL0, 1, 8, 125),
648 F(56000000, P_GPLL0, 1, 7, 100),
649 F(58982400, P_GPLL0, 1, 1152, 15625),
650 F(60000000, P_GPLL0, 1, 3, 40),
654 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
658 .parent_map = gcc_xo_gpll0_map,
659 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
660 .clkr.hw.init = &(struct clk_init_data){
661 .name = "blsp1_uart1_apps_clk_src",
662 .parent_names = gcc_xo_gpll0,
664 .ops = &clk_rcg2_ops,
668 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
672 .parent_map = gcc_xo_gpll0_map,
673 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
674 .clkr.hw.init = &(struct clk_init_data){
675 .name = "blsp1_uart2_apps_clk_src",
676 .parent_names = gcc_xo_gpll0,
678 .ops = &clk_rcg2_ops,
682 static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
683 F(19200000, P_XO, 1, 0, 0),
687 static struct clk_rcg2 cci_clk_src = {
691 .parent_map = gcc_xo_gpll0a_map,
692 .freq_tbl = ftbl_gcc_camss_cci_clk,
693 .clkr.hw.init = &(struct clk_init_data){
694 .name = "cci_clk_src",
695 .parent_names = gcc_xo_gpll0a,
697 .ops = &clk_rcg2_ops,
701 static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
702 F(100000000, P_GPLL0, 8, 0, 0),
703 F(200000000, P_GPLL0, 4, 0, 0),
707 static struct clk_rcg2 camss_gp0_clk_src = {
711 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
712 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
713 .clkr.hw.init = &(struct clk_init_data){
714 .name = "camss_gp0_clk_src",
715 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
717 .ops = &clk_rcg2_ops,
721 static struct clk_rcg2 camss_gp1_clk_src = {
725 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
726 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
727 .clkr.hw.init = &(struct clk_init_data){
728 .name = "camss_gp1_clk_src",
729 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
731 .ops = &clk_rcg2_ops,
735 static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
736 F(133330000, P_GPLL0, 6, 0, 0),
737 F(266670000, P_GPLL0, 3, 0, 0),
738 F(320000000, P_GPLL0, 2.5, 0, 0),
742 static struct clk_rcg2 jpeg0_clk_src = {
745 .parent_map = gcc_xo_gpll0_map,
746 .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
747 .clkr.hw.init = &(struct clk_init_data){
748 .name = "jpeg0_clk_src",
749 .parent_names = gcc_xo_gpll0,
751 .ops = &clk_rcg2_ops,
755 static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
756 F(9600000, P_XO, 2, 0, 0),
757 F(23880000, P_GPLL0, 1, 2, 67),
758 F(66670000, P_GPLL0, 12, 0, 0),
762 static struct clk_rcg2 mclk0_clk_src = {
766 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
767 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
768 .clkr.hw.init = &(struct clk_init_data){
769 .name = "mclk0_clk_src",
770 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
772 .ops = &clk_rcg2_ops,
776 static struct clk_rcg2 mclk1_clk_src = {
780 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
781 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
782 .clkr.hw.init = &(struct clk_init_data){
783 .name = "mclk1_clk_src",
784 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
786 .ops = &clk_rcg2_ops,
790 static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
791 F(100000000, P_GPLL0, 8, 0, 0),
792 F(200000000, P_GPLL0, 4, 0, 0),
796 static struct clk_rcg2 csi0phytimer_clk_src = {
799 .parent_map = gcc_xo_gpll0_gpll1a_map,
800 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "csi0phytimer_clk_src",
803 .parent_names = gcc_xo_gpll0_gpll1a,
805 .ops = &clk_rcg2_ops,
809 static struct clk_rcg2 csi1phytimer_clk_src = {
812 .parent_map = gcc_xo_gpll0_gpll1a_map,
813 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
814 .clkr.hw.init = &(struct clk_init_data){
815 .name = "csi1phytimer_clk_src",
816 .parent_names = gcc_xo_gpll0_gpll1a,
818 .ops = &clk_rcg2_ops,
822 static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
823 F(160000000, P_GPLL0, 5, 0, 0),
824 F(320000000, P_GPLL0, 2.5, 0, 0),
825 F(465000000, P_GPLL2, 2, 0, 0),
829 static struct clk_rcg2 cpp_clk_src = {
832 .parent_map = gcc_xo_gpll0_gpll2_map,
833 .freq_tbl = ftbl_gcc_camss_cpp_clk,
834 .clkr.hw.init = &(struct clk_init_data){
835 .name = "cpp_clk_src",
836 .parent_names = gcc_xo_gpll0_gpll2,
838 .ops = &clk_rcg2_ops,
842 static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
843 F(50000000, P_GPLL0, 16, 0, 0),
844 F(80000000, P_GPLL0, 10, 0, 0),
845 F(100000000, P_GPLL0, 8, 0, 0),
846 F(160000000, P_GPLL0, 5, 0, 0),
850 static struct clk_rcg2 crypto_clk_src = {
853 .parent_map = gcc_xo_gpll0_map,
854 .freq_tbl = ftbl_gcc_crypto_clk,
855 .clkr.hw.init = &(struct clk_init_data){
856 .name = "crypto_clk_src",
857 .parent_names = gcc_xo_gpll0,
859 .ops = &clk_rcg2_ops,
863 static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
864 F(19200000, P_XO, 1, 0, 0),
868 static struct clk_rcg2 gp1_clk_src = {
872 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
873 .freq_tbl = ftbl_gcc_gp1_3_clk,
874 .clkr.hw.init = &(struct clk_init_data){
875 .name = "gp1_clk_src",
876 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
878 .ops = &clk_rcg2_ops,
882 static struct clk_rcg2 gp2_clk_src = {
886 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
887 .freq_tbl = ftbl_gcc_gp1_3_clk,
888 .clkr.hw.init = &(struct clk_init_data){
889 .name = "gp2_clk_src",
890 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
892 .ops = &clk_rcg2_ops,
896 static struct clk_rcg2 gp3_clk_src = {
900 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
901 .freq_tbl = ftbl_gcc_gp1_3_clk,
902 .clkr.hw.init = &(struct clk_init_data){
903 .name = "gp3_clk_src",
904 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
906 .ops = &clk_rcg2_ops,
910 static struct clk_rcg2 byte0_clk_src = {
913 .parent_map = gcc_xo_gpll0a_dsibyte_map,
914 .clkr.hw.init = &(struct clk_init_data){
915 .name = "byte0_clk_src",
916 .parent_names = gcc_xo_gpll0a_dsibyte,
918 .ops = &clk_byte2_ops,
919 .flags = CLK_SET_RATE_PARENT,
923 static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
924 F(19200000, P_XO, 1, 0, 0),
928 static struct clk_rcg2 esc0_clk_src = {
931 .parent_map = gcc_xo_dsibyte_map,
932 .freq_tbl = ftbl_gcc_mdss_esc0_clk,
933 .clkr.hw.init = &(struct clk_init_data){
934 .name = "esc0_clk_src",
935 .parent_names = gcc_xo_dsibyte,
937 .ops = &clk_rcg2_ops,
941 static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
942 F(50000000, P_GPLL0, 16, 0, 0),
943 F(80000000, P_GPLL0, 10, 0, 0),
944 F(100000000, P_GPLL0, 8, 0, 0),
945 F(160000000, P_GPLL0, 5, 0, 0),
946 F(177780000, P_GPLL0, 4.5, 0, 0),
947 F(200000000, P_GPLL0, 4, 0, 0),
948 F(266670000, P_GPLL0, 3, 0, 0),
949 F(320000000, P_GPLL0, 2.5, 0, 0),
953 static struct clk_rcg2 mdp_clk_src = {
956 .parent_map = gcc_xo_gpll0_dsiphy_map,
957 .freq_tbl = ftbl_gcc_mdss_mdp_clk,
958 .clkr.hw.init = &(struct clk_init_data){
959 .name = "mdp_clk_src",
960 .parent_names = gcc_xo_gpll0_dsiphy,
962 .ops = &clk_rcg2_ops,
966 static struct clk_rcg2 pclk0_clk_src = {
970 .parent_map = gcc_xo_gpll0a_dsiphy_map,
971 .clkr.hw.init = &(struct clk_init_data){
972 .name = "pclk0_clk_src",
973 .parent_names = gcc_xo_gpll0a_dsiphy,
975 .ops = &clk_pixel_ops,
976 .flags = CLK_SET_RATE_PARENT,
980 static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
981 F(19200000, P_XO, 1, 0, 0),
985 static struct clk_rcg2 vsync_clk_src = {
988 .parent_map = gcc_xo_gpll0a_map,
989 .freq_tbl = ftbl_gcc_mdss_vsync_clk,
990 .clkr.hw.init = &(struct clk_init_data){
991 .name = "vsync_clk_src",
992 .parent_names = gcc_xo_gpll0a,
994 .ops = &clk_rcg2_ops,
998 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
999 F(64000000, P_GPLL0, 12.5, 0, 0),
1003 static struct clk_rcg2 pdm2_clk_src = {
1004 .cmd_rcgr = 0x44010,
1006 .parent_map = gcc_xo_gpll0_map,
1007 .freq_tbl = ftbl_gcc_pdm2_clk,
1008 .clkr.hw.init = &(struct clk_init_data){
1009 .name = "pdm2_clk_src",
1010 .parent_names = gcc_xo_gpll0,
1012 .ops = &clk_rcg2_ops,
1016 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
1017 F(144000, P_XO, 16, 3, 25),
1018 F(400000, P_XO, 12, 1, 4),
1019 F(20000000, P_GPLL0, 10, 1, 4),
1020 F(25000000, P_GPLL0, 16, 1, 2),
1021 F(50000000, P_GPLL0, 16, 0, 0),
1022 F(100000000, P_GPLL0, 8, 0, 0),
1023 F(177770000, P_GPLL0, 4.5, 0, 0),
1027 static struct clk_rcg2 sdcc1_apps_clk_src = {
1028 .cmd_rcgr = 0x42004,
1031 .parent_map = gcc_xo_gpll0_map,
1032 .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
1033 .clkr.hw.init = &(struct clk_init_data){
1034 .name = "sdcc1_apps_clk_src",
1035 .parent_names = gcc_xo_gpll0,
1037 .ops = &clk_rcg2_ops,
1041 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
1042 F(144000, P_XO, 16, 3, 25),
1043 F(400000, P_XO, 12, 1, 4),
1044 F(20000000, P_GPLL0, 10, 1, 4),
1045 F(25000000, P_GPLL0, 16, 1, 2),
1046 F(50000000, P_GPLL0, 16, 0, 0),
1047 F(100000000, P_GPLL0, 8, 0, 0),
1048 F(200000000, P_GPLL0, 4, 0, 0),
1052 static struct clk_rcg2 sdcc2_apps_clk_src = {
1053 .cmd_rcgr = 0x43004,
1056 .parent_map = gcc_xo_gpll0_map,
1057 .freq_tbl = ftbl_gcc_sdcc2_apps_clk,
1058 .clkr.hw.init = &(struct clk_init_data){
1059 .name = "sdcc2_apps_clk_src",
1060 .parent_names = gcc_xo_gpll0,
1062 .ops = &clk_rcg2_ops,
1066 static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
1067 F(155000000, P_GPLL2, 6, 0, 0),
1068 F(310000000, P_GPLL2, 3, 0, 0),
1069 F(400000000, P_GPLL0, 2, 0, 0),
1073 static struct clk_rcg2 apss_tcu_clk_src = {
1074 .cmd_rcgr = 0x1207c,
1076 .parent_map = gcc_xo_gpll0a_gpll1_gpll2_map,
1077 .freq_tbl = ftbl_gcc_apss_tcu_clk,
1078 .clkr.hw.init = &(struct clk_init_data){
1079 .name = "apss_tcu_clk_src",
1080 .parent_names = gcc_xo_gpll0a_gpll1_gpll2,
1082 .ops = &clk_rcg2_ops,
1086 static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
1087 F(19200000, P_XO, 1, 0, 0),
1088 F(100000000, P_GPLL0, 8, 0, 0),
1089 F(200000000, P_GPLL0, 4, 0, 0),
1090 F(266500000, P_BIMC, 4, 0, 0),
1091 F(400000000, P_GPLL0, 2, 0, 0),
1092 F(533000000, P_BIMC, 2, 0, 0),
1096 static struct clk_rcg2 bimc_gpu_clk_src = {
1097 .cmd_rcgr = 0x31028,
1099 .parent_map = gcc_xo_gpll0_bimc_map,
1100 .freq_tbl = ftbl_gcc_bimc_gpu_clk,
1101 .clkr.hw.init = &(struct clk_init_data){
1102 .name = "bimc_gpu_clk_src",
1103 .parent_names = gcc_xo_gpll0_bimc,
1105 .flags = CLK_GET_RATE_NOCACHE,
1106 .ops = &clk_rcg2_shared_ops,
1110 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1111 F(80000000, P_GPLL0, 10, 0, 0),
1115 static struct clk_rcg2 usb_hs_system_clk_src = {
1116 .cmd_rcgr = 0x41010,
1118 .parent_map = gcc_xo_gpll0_map,
1119 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1120 .clkr.hw.init = &(struct clk_init_data){
1121 .name = "usb_hs_system_clk_src",
1122 .parent_names = gcc_xo_gpll0,
1124 .ops = &clk_rcg2_ops,
1128 static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
1129 F(100000000, P_GPLL0, 8, 0, 0),
1130 F(160000000, P_GPLL0, 5, 0, 0),
1131 F(228570000, P_GPLL0, 3.5, 0, 0),
1135 static struct clk_rcg2 vcodec0_clk_src = {
1136 .cmd_rcgr = 0x4C000,
1139 .parent_map = gcc_xo_gpll0_map,
1140 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
1141 .clkr.hw.init = &(struct clk_init_data){
1142 .name = "vcodec0_clk_src",
1143 .parent_names = gcc_xo_gpll0,
1145 .ops = &clk_rcg2_ops,
1149 static struct clk_branch gcc_blsp1_ahb_clk = {
1150 .halt_reg = 0x01008,
1151 .halt_check = BRANCH_HALT_VOTED,
1153 .enable_reg = 0x45004,
1154 .enable_mask = BIT(10),
1155 .hw.init = &(struct clk_init_data){
1156 .name = "gcc_blsp1_ahb_clk",
1157 .parent_names = (const char *[]){
1158 "pcnoc_bfdcd_clk_src",
1161 .ops = &clk_branch2_ops,
1166 static struct clk_branch gcc_blsp1_sleep_clk = {
1167 .halt_reg = 0x01004,
1169 .enable_reg = 0x01004,
1170 .enable_mask = BIT(0),
1171 .hw.init = &(struct clk_init_data){
1172 .name = "gcc_blsp1_sleep_clk",
1173 .parent_names = (const char *[]){
1177 .flags = CLK_SET_RATE_PARENT,
1178 .ops = &clk_branch2_ops,
1183 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1184 .halt_reg = 0x02008,
1186 .enable_reg = 0x02008,
1187 .enable_mask = BIT(0),
1188 .hw.init = &(struct clk_init_data){
1189 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1190 .parent_names = (const char *[]){
1191 "blsp1_qup1_i2c_apps_clk_src",
1194 .flags = CLK_SET_RATE_PARENT,
1195 .ops = &clk_branch2_ops,
1200 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1201 .halt_reg = 0x02004,
1203 .enable_reg = 0x02004,
1204 .enable_mask = BIT(0),
1205 .hw.init = &(struct clk_init_data){
1206 .name = "gcc_blsp1_qup1_spi_apps_clk",
1207 .parent_names = (const char *[]){
1208 "blsp1_qup1_spi_apps_clk_src",
1211 .flags = CLK_SET_RATE_PARENT,
1212 .ops = &clk_branch2_ops,
1217 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1218 .halt_reg = 0x03010,
1220 .enable_reg = 0x03010,
1221 .enable_mask = BIT(0),
1222 .hw.init = &(struct clk_init_data){
1223 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1224 .parent_names = (const char *[]){
1225 "blsp1_qup2_i2c_apps_clk_src",
1228 .flags = CLK_SET_RATE_PARENT,
1229 .ops = &clk_branch2_ops,
1234 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1235 .halt_reg = 0x0300c,
1237 .enable_reg = 0x0300c,
1238 .enable_mask = BIT(0),
1239 .hw.init = &(struct clk_init_data){
1240 .name = "gcc_blsp1_qup2_spi_apps_clk",
1241 .parent_names = (const char *[]){
1242 "blsp1_qup2_spi_apps_clk_src",
1245 .flags = CLK_SET_RATE_PARENT,
1246 .ops = &clk_branch2_ops,
1251 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1252 .halt_reg = 0x04020,
1254 .enable_reg = 0x04020,
1255 .enable_mask = BIT(0),
1256 .hw.init = &(struct clk_init_data){
1257 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1258 .parent_names = (const char *[]){
1259 "blsp1_qup3_i2c_apps_clk_src",
1262 .flags = CLK_SET_RATE_PARENT,
1263 .ops = &clk_branch2_ops,
1268 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1269 .halt_reg = 0x0401c,
1271 .enable_reg = 0x0401c,
1272 .enable_mask = BIT(0),
1273 .hw.init = &(struct clk_init_data){
1274 .name = "gcc_blsp1_qup3_spi_apps_clk",
1275 .parent_names = (const char *[]){
1276 "blsp1_qup3_spi_apps_clk_src",
1279 .flags = CLK_SET_RATE_PARENT,
1280 .ops = &clk_branch2_ops,
1285 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1286 .halt_reg = 0x05020,
1288 .enable_reg = 0x05020,
1289 .enable_mask = BIT(0),
1290 .hw.init = &(struct clk_init_data){
1291 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1292 .parent_names = (const char *[]){
1293 "blsp1_qup4_i2c_apps_clk_src",
1296 .flags = CLK_SET_RATE_PARENT,
1297 .ops = &clk_branch2_ops,
1302 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1303 .halt_reg = 0x0501c,
1305 .enable_reg = 0x0501c,
1306 .enable_mask = BIT(0),
1307 .hw.init = &(struct clk_init_data){
1308 .name = "gcc_blsp1_qup4_spi_apps_clk",
1309 .parent_names = (const char *[]){
1310 "blsp1_qup4_spi_apps_clk_src",
1313 .flags = CLK_SET_RATE_PARENT,
1314 .ops = &clk_branch2_ops,
1319 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1320 .halt_reg = 0x06020,
1322 .enable_reg = 0x06020,
1323 .enable_mask = BIT(0),
1324 .hw.init = &(struct clk_init_data){
1325 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1326 .parent_names = (const char *[]){
1327 "blsp1_qup5_i2c_apps_clk_src",
1330 .flags = CLK_SET_RATE_PARENT,
1331 .ops = &clk_branch2_ops,
1336 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1337 .halt_reg = 0x0601c,
1339 .enable_reg = 0x0601c,
1340 .enable_mask = BIT(0),
1341 .hw.init = &(struct clk_init_data){
1342 .name = "gcc_blsp1_qup5_spi_apps_clk",
1343 .parent_names = (const char *[]){
1344 "blsp1_qup5_spi_apps_clk_src",
1347 .flags = CLK_SET_RATE_PARENT,
1348 .ops = &clk_branch2_ops,
1353 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1354 .halt_reg = 0x07020,
1356 .enable_reg = 0x07020,
1357 .enable_mask = BIT(0),
1358 .hw.init = &(struct clk_init_data){
1359 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1360 .parent_names = (const char *[]){
1361 "blsp1_qup6_i2c_apps_clk_src",
1364 .flags = CLK_SET_RATE_PARENT,
1365 .ops = &clk_branch2_ops,
1370 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1371 .halt_reg = 0x0701c,
1373 .enable_reg = 0x0701c,
1374 .enable_mask = BIT(0),
1375 .hw.init = &(struct clk_init_data){
1376 .name = "gcc_blsp1_qup6_spi_apps_clk",
1377 .parent_names = (const char *[]){
1378 "blsp1_qup6_spi_apps_clk_src",
1381 .flags = CLK_SET_RATE_PARENT,
1382 .ops = &clk_branch2_ops,
1387 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1388 .halt_reg = 0x0203c,
1390 .enable_reg = 0x0203c,
1391 .enable_mask = BIT(0),
1392 .hw.init = &(struct clk_init_data){
1393 .name = "gcc_blsp1_uart1_apps_clk",
1394 .parent_names = (const char *[]){
1395 "blsp1_uart1_apps_clk_src",
1398 .flags = CLK_SET_RATE_PARENT,
1399 .ops = &clk_branch2_ops,
1404 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1405 .halt_reg = 0x0302c,
1407 .enable_reg = 0x0302c,
1408 .enable_mask = BIT(0),
1409 .hw.init = &(struct clk_init_data){
1410 .name = "gcc_blsp1_uart2_apps_clk",
1411 .parent_names = (const char *[]){
1412 "blsp1_uart2_apps_clk_src",
1415 .flags = CLK_SET_RATE_PARENT,
1416 .ops = &clk_branch2_ops,
1421 static struct clk_branch gcc_boot_rom_ahb_clk = {
1422 .halt_reg = 0x1300c,
1423 .halt_check = BRANCH_HALT_VOTED,
1425 .enable_reg = 0x45004,
1426 .enable_mask = BIT(7),
1427 .hw.init = &(struct clk_init_data){
1428 .name = "gcc_boot_rom_ahb_clk",
1429 .parent_names = (const char *[]){
1430 "pcnoc_bfdcd_clk_src",
1433 .ops = &clk_branch2_ops,
1438 static struct clk_branch gcc_camss_cci_ahb_clk = {
1439 .halt_reg = 0x5101c,
1441 .enable_reg = 0x5101c,
1442 .enable_mask = BIT(0),
1443 .hw.init = &(struct clk_init_data){
1444 .name = "gcc_camss_cci_ahb_clk",
1445 .parent_names = (const char *[]){
1446 "camss_ahb_clk_src",
1449 .flags = CLK_SET_RATE_PARENT,
1450 .ops = &clk_branch2_ops,
1455 static struct clk_branch gcc_camss_cci_clk = {
1456 .halt_reg = 0x51018,
1458 .enable_reg = 0x51018,
1459 .enable_mask = BIT(0),
1460 .hw.init = &(struct clk_init_data){
1461 .name = "gcc_camss_cci_clk",
1462 .parent_names = (const char *[]){
1466 .flags = CLK_SET_RATE_PARENT,
1467 .ops = &clk_branch2_ops,
1472 static struct clk_branch gcc_camss_csi0_ahb_clk = {
1473 .halt_reg = 0x4e040,
1475 .enable_reg = 0x4e040,
1476 .enable_mask = BIT(0),
1477 .hw.init = &(struct clk_init_data){
1478 .name = "gcc_camss_csi0_ahb_clk",
1479 .parent_names = (const char *[]){
1480 "camss_ahb_clk_src",
1483 .flags = CLK_SET_RATE_PARENT,
1484 .ops = &clk_branch2_ops,
1489 static struct clk_branch gcc_camss_csi0_clk = {
1490 .halt_reg = 0x4e03c,
1492 .enable_reg = 0x4e03c,
1493 .enable_mask = BIT(0),
1494 .hw.init = &(struct clk_init_data){
1495 .name = "gcc_camss_csi0_clk",
1496 .parent_names = (const char *[]){
1500 .flags = CLK_SET_RATE_PARENT,
1501 .ops = &clk_branch2_ops,
1506 static struct clk_branch gcc_camss_csi0phy_clk = {
1507 .halt_reg = 0x4e048,
1509 .enable_reg = 0x4e048,
1510 .enable_mask = BIT(0),
1511 .hw.init = &(struct clk_init_data){
1512 .name = "gcc_camss_csi0phy_clk",
1513 .parent_names = (const char *[]){
1517 .flags = CLK_SET_RATE_PARENT,
1518 .ops = &clk_branch2_ops,
1523 static struct clk_branch gcc_camss_csi0pix_clk = {
1524 .halt_reg = 0x4e058,
1526 .enable_reg = 0x4e058,
1527 .enable_mask = BIT(0),
1528 .hw.init = &(struct clk_init_data){
1529 .name = "gcc_camss_csi0pix_clk",
1530 .parent_names = (const char *[]){
1534 .flags = CLK_SET_RATE_PARENT,
1535 .ops = &clk_branch2_ops,
1540 static struct clk_branch gcc_camss_csi0rdi_clk = {
1541 .halt_reg = 0x4e050,
1543 .enable_reg = 0x4e050,
1544 .enable_mask = BIT(0),
1545 .hw.init = &(struct clk_init_data){
1546 .name = "gcc_camss_csi0rdi_clk",
1547 .parent_names = (const char *[]){
1551 .flags = CLK_SET_RATE_PARENT,
1552 .ops = &clk_branch2_ops,
1557 static struct clk_branch gcc_camss_csi1_ahb_clk = {
1558 .halt_reg = 0x4f040,
1560 .enable_reg = 0x4f040,
1561 .enable_mask = BIT(0),
1562 .hw.init = &(struct clk_init_data){
1563 .name = "gcc_camss_csi1_ahb_clk",
1564 .parent_names = (const char *[]){
1565 "camss_ahb_clk_src",
1568 .flags = CLK_SET_RATE_PARENT,
1569 .ops = &clk_branch2_ops,
1574 static struct clk_branch gcc_camss_csi1_clk = {
1575 .halt_reg = 0x4f03c,
1577 .enable_reg = 0x4f03c,
1578 .enable_mask = BIT(0),
1579 .hw.init = &(struct clk_init_data){
1580 .name = "gcc_camss_csi1_clk",
1581 .parent_names = (const char *[]){
1585 .flags = CLK_SET_RATE_PARENT,
1586 .ops = &clk_branch2_ops,
1591 static struct clk_branch gcc_camss_csi1phy_clk = {
1592 .halt_reg = 0x4f048,
1594 .enable_reg = 0x4f048,
1595 .enable_mask = BIT(0),
1596 .hw.init = &(struct clk_init_data){
1597 .name = "gcc_camss_csi1phy_clk",
1598 .parent_names = (const char *[]){
1602 .flags = CLK_SET_RATE_PARENT,
1603 .ops = &clk_branch2_ops,
1608 static struct clk_branch gcc_camss_csi1pix_clk = {
1609 .halt_reg = 0x4f058,
1611 .enable_reg = 0x4f058,
1612 .enable_mask = BIT(0),
1613 .hw.init = &(struct clk_init_data){
1614 .name = "gcc_camss_csi1pix_clk",
1615 .parent_names = (const char *[]){
1619 .flags = CLK_SET_RATE_PARENT,
1620 .ops = &clk_branch2_ops,
1625 static struct clk_branch gcc_camss_csi1rdi_clk = {
1626 .halt_reg = 0x4f050,
1628 .enable_reg = 0x4f050,
1629 .enable_mask = BIT(0),
1630 .hw.init = &(struct clk_init_data){
1631 .name = "gcc_camss_csi1rdi_clk",
1632 .parent_names = (const char *[]){
1636 .flags = CLK_SET_RATE_PARENT,
1637 .ops = &clk_branch2_ops,
1642 static struct clk_branch gcc_camss_csi_vfe0_clk = {
1643 .halt_reg = 0x58050,
1645 .enable_reg = 0x58050,
1646 .enable_mask = BIT(0),
1647 .hw.init = &(struct clk_init_data){
1648 .name = "gcc_camss_csi_vfe0_clk",
1649 .parent_names = (const char *[]){
1653 .flags = CLK_SET_RATE_PARENT,
1654 .ops = &clk_branch2_ops,
1659 static struct clk_branch gcc_camss_gp0_clk = {
1660 .halt_reg = 0x54018,
1662 .enable_reg = 0x54018,
1663 .enable_mask = BIT(0),
1664 .hw.init = &(struct clk_init_data){
1665 .name = "gcc_camss_gp0_clk",
1666 .parent_names = (const char *[]){
1667 "camss_gp0_clk_src",
1670 .flags = CLK_SET_RATE_PARENT,
1671 .ops = &clk_branch2_ops,
1676 static struct clk_branch gcc_camss_gp1_clk = {
1677 .halt_reg = 0x55018,
1679 .enable_reg = 0x55018,
1680 .enable_mask = BIT(0),
1681 .hw.init = &(struct clk_init_data){
1682 .name = "gcc_camss_gp1_clk",
1683 .parent_names = (const char *[]){
1684 "camss_gp1_clk_src",
1687 .flags = CLK_SET_RATE_PARENT,
1688 .ops = &clk_branch2_ops,
1693 static struct clk_branch gcc_camss_ispif_ahb_clk = {
1694 .halt_reg = 0x50004,
1696 .enable_reg = 0x50004,
1697 .enable_mask = BIT(0),
1698 .hw.init = &(struct clk_init_data){
1699 .name = "gcc_camss_ispif_ahb_clk",
1700 .parent_names = (const char *[]){
1701 "camss_ahb_clk_src",
1704 .flags = CLK_SET_RATE_PARENT,
1705 .ops = &clk_branch2_ops,
1710 static struct clk_branch gcc_camss_jpeg0_clk = {
1711 .halt_reg = 0x57020,
1713 .enable_reg = 0x57020,
1714 .enable_mask = BIT(0),
1715 .hw.init = &(struct clk_init_data){
1716 .name = "gcc_camss_jpeg0_clk",
1717 .parent_names = (const char *[]){
1721 .flags = CLK_SET_RATE_PARENT,
1722 .ops = &clk_branch2_ops,
1727 static struct clk_branch gcc_camss_jpeg_ahb_clk = {
1728 .halt_reg = 0x57024,
1730 .enable_reg = 0x57024,
1731 .enable_mask = BIT(0),
1732 .hw.init = &(struct clk_init_data){
1733 .name = "gcc_camss_jpeg_ahb_clk",
1734 .parent_names = (const char *[]){
1735 "camss_ahb_clk_src",
1738 .flags = CLK_SET_RATE_PARENT,
1739 .ops = &clk_branch2_ops,
1744 static struct clk_branch gcc_camss_jpeg_axi_clk = {
1745 .halt_reg = 0x57028,
1747 .enable_reg = 0x57028,
1748 .enable_mask = BIT(0),
1749 .hw.init = &(struct clk_init_data){
1750 .name = "gcc_camss_jpeg_axi_clk",
1751 .parent_names = (const char *[]){
1752 "system_noc_bfdcd_clk_src",
1755 .flags = CLK_SET_RATE_PARENT,
1756 .ops = &clk_branch2_ops,
1761 static struct clk_branch gcc_camss_mclk0_clk = {
1762 .halt_reg = 0x52018,
1764 .enable_reg = 0x52018,
1765 .enable_mask = BIT(0),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "gcc_camss_mclk0_clk",
1768 .parent_names = (const char *[]){
1772 .flags = CLK_SET_RATE_PARENT,
1773 .ops = &clk_branch2_ops,
1778 static struct clk_branch gcc_camss_mclk1_clk = {
1779 .halt_reg = 0x53018,
1781 .enable_reg = 0x53018,
1782 .enable_mask = BIT(0),
1783 .hw.init = &(struct clk_init_data){
1784 .name = "gcc_camss_mclk1_clk",
1785 .parent_names = (const char *[]){
1789 .flags = CLK_SET_RATE_PARENT,
1790 .ops = &clk_branch2_ops,
1795 static struct clk_branch gcc_camss_micro_ahb_clk = {
1796 .halt_reg = 0x5600c,
1798 .enable_reg = 0x5600c,
1799 .enable_mask = BIT(0),
1800 .hw.init = &(struct clk_init_data){
1801 .name = "gcc_camss_micro_ahb_clk",
1802 .parent_names = (const char *[]){
1803 "camss_ahb_clk_src",
1806 .flags = CLK_SET_RATE_PARENT,
1807 .ops = &clk_branch2_ops,
1812 static struct clk_branch gcc_camss_csi0phytimer_clk = {
1813 .halt_reg = 0x4e01c,
1815 .enable_reg = 0x4e01c,
1816 .enable_mask = BIT(0),
1817 .hw.init = &(struct clk_init_data){
1818 .name = "gcc_camss_csi0phytimer_clk",
1819 .parent_names = (const char *[]){
1820 "csi0phytimer_clk_src",
1823 .flags = CLK_SET_RATE_PARENT,
1824 .ops = &clk_branch2_ops,
1829 static struct clk_branch gcc_camss_csi1phytimer_clk = {
1830 .halt_reg = 0x4f01c,
1832 .enable_reg = 0x4f01c,
1833 .enable_mask = BIT(0),
1834 .hw.init = &(struct clk_init_data){
1835 .name = "gcc_camss_csi1phytimer_clk",
1836 .parent_names = (const char *[]){
1837 "csi1phytimer_clk_src",
1840 .flags = CLK_SET_RATE_PARENT,
1841 .ops = &clk_branch2_ops,
1846 static struct clk_branch gcc_camss_ahb_clk = {
1847 .halt_reg = 0x5a014,
1849 .enable_reg = 0x5a014,
1850 .enable_mask = BIT(0),
1851 .hw.init = &(struct clk_init_data){
1852 .name = "gcc_camss_ahb_clk",
1853 .parent_names = (const char *[]){
1854 "camss_ahb_clk_src",
1857 .flags = CLK_SET_RATE_PARENT,
1858 .ops = &clk_branch2_ops,
1863 static struct clk_branch gcc_camss_top_ahb_clk = {
1864 .halt_reg = 0x56004,
1866 .enable_reg = 0x56004,
1867 .enable_mask = BIT(0),
1868 .hw.init = &(struct clk_init_data){
1869 .name = "gcc_camss_top_ahb_clk",
1870 .parent_names = (const char *[]){
1871 "pcnoc_bfdcd_clk_src",
1874 .flags = CLK_SET_RATE_PARENT,
1875 .ops = &clk_branch2_ops,
1880 static struct clk_branch gcc_camss_cpp_ahb_clk = {
1881 .halt_reg = 0x58040,
1883 .enable_reg = 0x58040,
1884 .enable_mask = BIT(0),
1885 .hw.init = &(struct clk_init_data){
1886 .name = "gcc_camss_cpp_ahb_clk",
1887 .parent_names = (const char *[]){
1888 "camss_ahb_clk_src",
1891 .flags = CLK_SET_RATE_PARENT,
1892 .ops = &clk_branch2_ops,
1897 static struct clk_branch gcc_camss_cpp_clk = {
1898 .halt_reg = 0x5803c,
1900 .enable_reg = 0x5803c,
1901 .enable_mask = BIT(0),
1902 .hw.init = &(struct clk_init_data){
1903 .name = "gcc_camss_cpp_clk",
1904 .parent_names = (const char *[]){
1908 .flags = CLK_SET_RATE_PARENT,
1909 .ops = &clk_branch2_ops,
1914 static struct clk_branch gcc_camss_vfe0_clk = {
1915 .halt_reg = 0x58038,
1917 .enable_reg = 0x58038,
1918 .enable_mask = BIT(0),
1919 .hw.init = &(struct clk_init_data){
1920 .name = "gcc_camss_vfe0_clk",
1921 .parent_names = (const char *[]){
1925 .flags = CLK_SET_RATE_PARENT,
1926 .ops = &clk_branch2_ops,
1931 static struct clk_branch gcc_camss_vfe_ahb_clk = {
1932 .halt_reg = 0x58044,
1934 .enable_reg = 0x58044,
1935 .enable_mask = BIT(0),
1936 .hw.init = &(struct clk_init_data){
1937 .name = "gcc_camss_vfe_ahb_clk",
1938 .parent_names = (const char *[]){
1939 "camss_ahb_clk_src",
1942 .flags = CLK_SET_RATE_PARENT,
1943 .ops = &clk_branch2_ops,
1948 static struct clk_branch gcc_camss_vfe_axi_clk = {
1949 .halt_reg = 0x58048,
1951 .enable_reg = 0x58048,
1952 .enable_mask = BIT(0),
1953 .hw.init = &(struct clk_init_data){
1954 .name = "gcc_camss_vfe_axi_clk",
1955 .parent_names = (const char *[]){
1956 "system_noc_bfdcd_clk_src",
1959 .flags = CLK_SET_RATE_PARENT,
1960 .ops = &clk_branch2_ops,
1965 static struct clk_branch gcc_crypto_ahb_clk = {
1966 .halt_reg = 0x16024,
1967 .halt_check = BRANCH_HALT_VOTED,
1969 .enable_reg = 0x45004,
1970 .enable_mask = BIT(0),
1971 .hw.init = &(struct clk_init_data){
1972 .name = "gcc_crypto_ahb_clk",
1973 .parent_names = (const char *[]){
1974 "pcnoc_bfdcd_clk_src",
1977 .ops = &clk_branch2_ops,
1982 static struct clk_branch gcc_crypto_axi_clk = {
1983 .halt_reg = 0x16020,
1984 .halt_check = BRANCH_HALT_VOTED,
1986 .enable_reg = 0x45004,
1987 .enable_mask = BIT(1),
1988 .hw.init = &(struct clk_init_data){
1989 .name = "gcc_crypto_axi_clk",
1990 .parent_names = (const char *[]){
1991 "pcnoc_bfdcd_clk_src",
1994 .flags = CLK_SET_RATE_PARENT,
1995 .ops = &clk_branch2_ops,
2000 static struct clk_branch gcc_crypto_clk = {
2001 .halt_reg = 0x1601c,
2002 .halt_check = BRANCH_HALT_VOTED,
2004 .enable_reg = 0x45004,
2005 .enable_mask = BIT(2),
2006 .hw.init = &(struct clk_init_data){
2007 .name = "gcc_crypto_clk",
2008 .parent_names = (const char *[]){
2012 .ops = &clk_branch2_ops,
2017 static struct clk_branch gcc_oxili_gmem_clk = {
2018 .halt_reg = 0x59024,
2020 .enable_reg = 0x59024,
2021 .enable_mask = BIT(0),
2022 .hw.init = &(struct clk_init_data){
2023 .name = "gcc_oxili_gmem_clk",
2024 .parent_names = (const char *[]){
2028 .flags = CLK_SET_RATE_PARENT,
2029 .ops = &clk_branch2_ops,
2034 static struct clk_branch gcc_gp1_clk = {
2035 .halt_reg = 0x08000,
2037 .enable_reg = 0x08000,
2038 .enable_mask = BIT(0),
2039 .hw.init = &(struct clk_init_data){
2040 .name = "gcc_gp1_clk",
2041 .parent_names = (const char *[]){
2045 .flags = CLK_SET_RATE_PARENT,
2046 .ops = &clk_branch2_ops,
2051 static struct clk_branch gcc_gp2_clk = {
2052 .halt_reg = 0x09000,
2054 .enable_reg = 0x09000,
2055 .enable_mask = BIT(0),
2056 .hw.init = &(struct clk_init_data){
2057 .name = "gcc_gp2_clk",
2058 .parent_names = (const char *[]){
2062 .flags = CLK_SET_RATE_PARENT,
2063 .ops = &clk_branch2_ops,
2068 static struct clk_branch gcc_gp3_clk = {
2069 .halt_reg = 0x0a000,
2071 .enable_reg = 0x0a000,
2072 .enable_mask = BIT(0),
2073 .hw.init = &(struct clk_init_data){
2074 .name = "gcc_gp3_clk",
2075 .parent_names = (const char *[]){
2079 .flags = CLK_SET_RATE_PARENT,
2080 .ops = &clk_branch2_ops,
2085 static struct clk_branch gcc_mdss_ahb_clk = {
2086 .halt_reg = 0x4d07c,
2088 .enable_reg = 0x4d07c,
2089 .enable_mask = BIT(0),
2090 .hw.init = &(struct clk_init_data){
2091 .name = "gcc_mdss_ahb_clk",
2092 .parent_names = (const char *[]){
2093 "pcnoc_bfdcd_clk_src",
2096 .flags = CLK_SET_RATE_PARENT,
2097 .ops = &clk_branch2_ops,
2102 static struct clk_branch gcc_mdss_axi_clk = {
2103 .halt_reg = 0x4d080,
2105 .enable_reg = 0x4d080,
2106 .enable_mask = BIT(0),
2107 .hw.init = &(struct clk_init_data){
2108 .name = "gcc_mdss_axi_clk",
2109 .parent_names = (const char *[]){
2110 "system_noc_bfdcd_clk_src",
2113 .flags = CLK_SET_RATE_PARENT,
2114 .ops = &clk_branch2_ops,
2119 static struct clk_branch gcc_mdss_byte0_clk = {
2120 .halt_reg = 0x4d094,
2122 .enable_reg = 0x4d094,
2123 .enable_mask = BIT(0),
2124 .hw.init = &(struct clk_init_data){
2125 .name = "gcc_mdss_byte0_clk",
2126 .parent_names = (const char *[]){
2130 .flags = CLK_SET_RATE_PARENT,
2131 .ops = &clk_branch2_ops,
2136 static struct clk_branch gcc_mdss_esc0_clk = {
2137 .halt_reg = 0x4d098,
2139 .enable_reg = 0x4d098,
2140 .enable_mask = BIT(0),
2141 .hw.init = &(struct clk_init_data){
2142 .name = "gcc_mdss_esc0_clk",
2143 .parent_names = (const char *[]){
2147 .flags = CLK_SET_RATE_PARENT,
2148 .ops = &clk_branch2_ops,
2153 static struct clk_branch gcc_mdss_mdp_clk = {
2154 .halt_reg = 0x4D088,
2156 .enable_reg = 0x4D088,
2157 .enable_mask = BIT(0),
2158 .hw.init = &(struct clk_init_data){
2159 .name = "gcc_mdss_mdp_clk",
2160 .parent_names = (const char *[]){
2164 .flags = CLK_SET_RATE_PARENT,
2165 .ops = &clk_branch2_ops,
2170 static struct clk_branch gcc_mdss_pclk0_clk = {
2171 .halt_reg = 0x4d084,
2173 .enable_reg = 0x4d084,
2174 .enable_mask = BIT(0),
2175 .hw.init = &(struct clk_init_data){
2176 .name = "gcc_mdss_pclk0_clk",
2177 .parent_names = (const char *[]){
2181 .flags = CLK_SET_RATE_PARENT,
2182 .ops = &clk_branch2_ops,
2187 static struct clk_branch gcc_mdss_vsync_clk = {
2188 .halt_reg = 0x4d090,
2190 .enable_reg = 0x4d090,
2191 .enable_mask = BIT(0),
2192 .hw.init = &(struct clk_init_data){
2193 .name = "gcc_mdss_vsync_clk",
2194 .parent_names = (const char *[]){
2198 .flags = CLK_SET_RATE_PARENT,
2199 .ops = &clk_branch2_ops,
2204 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2205 .halt_reg = 0x49000,
2207 .enable_reg = 0x49000,
2208 .enable_mask = BIT(0),
2209 .hw.init = &(struct clk_init_data){
2210 .name = "gcc_mss_cfg_ahb_clk",
2211 .parent_names = (const char *[]){
2212 "pcnoc_bfdcd_clk_src",
2215 .flags = CLK_SET_RATE_PARENT,
2216 .ops = &clk_branch2_ops,
2221 static struct clk_branch gcc_oxili_ahb_clk = {
2222 .halt_reg = 0x59028,
2224 .enable_reg = 0x59028,
2225 .enable_mask = BIT(0),
2226 .hw.init = &(struct clk_init_data){
2227 .name = "gcc_oxili_ahb_clk",
2228 .parent_names = (const char *[]){
2229 "pcnoc_bfdcd_clk_src",
2232 .flags = CLK_SET_RATE_PARENT,
2233 .ops = &clk_branch2_ops,
2238 static struct clk_branch gcc_oxili_gfx3d_clk = {
2239 .halt_reg = 0x59020,
2241 .enable_reg = 0x59020,
2242 .enable_mask = BIT(0),
2243 .hw.init = &(struct clk_init_data){
2244 .name = "gcc_oxili_gfx3d_clk",
2245 .parent_names = (const char *[]){
2249 .flags = CLK_SET_RATE_PARENT,
2250 .ops = &clk_branch2_ops,
2255 static struct clk_branch gcc_pdm2_clk = {
2256 .halt_reg = 0x4400c,
2258 .enable_reg = 0x4400c,
2259 .enable_mask = BIT(0),
2260 .hw.init = &(struct clk_init_data){
2261 .name = "gcc_pdm2_clk",
2262 .parent_names = (const char *[]){
2266 .flags = CLK_SET_RATE_PARENT,
2267 .ops = &clk_branch2_ops,
2272 static struct clk_branch gcc_pdm_ahb_clk = {
2273 .halt_reg = 0x44004,
2275 .enable_reg = 0x44004,
2276 .enable_mask = BIT(0),
2277 .hw.init = &(struct clk_init_data){
2278 .name = "gcc_pdm_ahb_clk",
2279 .parent_names = (const char *[]){
2280 "pcnoc_bfdcd_clk_src",
2283 .flags = CLK_SET_RATE_PARENT,
2284 .ops = &clk_branch2_ops,
2289 static struct clk_branch gcc_prng_ahb_clk = {
2290 .halt_reg = 0x13004,
2291 .halt_check = BRANCH_HALT_VOTED,
2293 .enable_reg = 0x45004,
2294 .enable_mask = BIT(8),
2295 .hw.init = &(struct clk_init_data){
2296 .name = "gcc_prng_ahb_clk",
2297 .parent_names = (const char *[]){
2298 "pcnoc_bfdcd_clk_src",
2301 .ops = &clk_branch2_ops,
2306 static struct clk_branch gcc_sdcc1_ahb_clk = {
2307 .halt_reg = 0x4201c,
2309 .enable_reg = 0x4201c,
2310 .enable_mask = BIT(0),
2311 .hw.init = &(struct clk_init_data){
2312 .name = "gcc_sdcc1_ahb_clk",
2313 .parent_names = (const char *[]){
2314 "pcnoc_bfdcd_clk_src",
2317 .flags = CLK_SET_RATE_PARENT,
2318 .ops = &clk_branch2_ops,
2323 static struct clk_branch gcc_sdcc1_apps_clk = {
2324 .halt_reg = 0x42018,
2326 .enable_reg = 0x42018,
2327 .enable_mask = BIT(0),
2328 .hw.init = &(struct clk_init_data){
2329 .name = "gcc_sdcc1_apps_clk",
2330 .parent_names = (const char *[]){
2331 "sdcc1_apps_clk_src",
2334 .flags = CLK_SET_RATE_PARENT,
2335 .ops = &clk_branch2_ops,
2340 static struct clk_branch gcc_sdcc2_ahb_clk = {
2341 .halt_reg = 0x4301c,
2343 .enable_reg = 0x4301c,
2344 .enable_mask = BIT(0),
2345 .hw.init = &(struct clk_init_data){
2346 .name = "gcc_sdcc2_ahb_clk",
2347 .parent_names = (const char *[]){
2348 "pcnoc_bfdcd_clk_src",
2351 .flags = CLK_SET_RATE_PARENT,
2352 .ops = &clk_branch2_ops,
2357 static struct clk_branch gcc_sdcc2_apps_clk = {
2358 .halt_reg = 0x43018,
2360 .enable_reg = 0x43018,
2361 .enable_mask = BIT(0),
2362 .hw.init = &(struct clk_init_data){
2363 .name = "gcc_sdcc2_apps_clk",
2364 .parent_names = (const char *[]){
2365 "sdcc2_apps_clk_src",
2368 .flags = CLK_SET_RATE_PARENT,
2369 .ops = &clk_branch2_ops,
2374 static struct clk_rcg2 bimc_ddr_clk_src = {
2375 .cmd_rcgr = 0x32004,
2377 .parent_map = gcc_xo_gpll0_bimc_map,
2378 .clkr.hw.init = &(struct clk_init_data){
2379 .name = "bimc_ddr_clk_src",
2380 .parent_names = gcc_xo_gpll0_bimc,
2382 .ops = &clk_rcg2_ops,
2383 .flags = CLK_GET_RATE_NOCACHE,
2387 static struct clk_branch gcc_apss_tcu_clk = {
2388 .halt_reg = 0x12018,
2390 .enable_reg = 0x4500c,
2391 .enable_mask = BIT(1),
2392 .hw.init = &(struct clk_init_data){
2393 .name = "gcc_apss_tcu_clk",
2394 .parent_names = (const char *[]){
2398 .ops = &clk_branch2_ops,
2403 static struct clk_branch gcc_gfx_tcu_clk = {
2404 .halt_reg = 0x12020,
2406 .enable_reg = 0x4500c,
2407 .enable_mask = BIT(2),
2408 .hw.init = &(struct clk_init_data){
2409 .name = "gcc_gfx_tcu_clk",
2410 .parent_names = (const char *[]){
2414 .ops = &clk_branch2_ops,
2419 static struct clk_branch gcc_gtcu_ahb_clk = {
2420 .halt_reg = 0x12044,
2422 .enable_reg = 0x4500c,
2423 .enable_mask = BIT(13),
2424 .hw.init = &(struct clk_init_data){
2425 .name = "gcc_gtcu_ahb_clk",
2426 .parent_names = (const char *[]){
2427 "pcnoc_bfdcd_clk_src",
2430 .flags = CLK_SET_RATE_PARENT,
2431 .ops = &clk_branch2_ops,
2436 static struct clk_branch gcc_bimc_gfx_clk = {
2437 .halt_reg = 0x31024,
2439 .enable_reg = 0x31024,
2440 .enable_mask = BIT(0),
2441 .hw.init = &(struct clk_init_data){
2442 .name = "gcc_bimc_gfx_clk",
2443 .parent_names = (const char *[]){
2447 .flags = CLK_SET_RATE_PARENT,
2448 .ops = &clk_branch2_ops,
2453 static struct clk_branch gcc_bimc_gpu_clk = {
2454 .halt_reg = 0x31040,
2456 .enable_reg = 0x31040,
2457 .enable_mask = BIT(0),
2458 .hw.init = &(struct clk_init_data){
2459 .name = "gcc_bimc_gpu_clk",
2460 .parent_names = (const char *[]){
2464 .flags = CLK_SET_RATE_PARENT,
2465 .ops = &clk_branch2_ops,
2470 static struct clk_branch gcc_jpeg_tbu_clk = {
2471 .halt_reg = 0x12034,
2473 .enable_reg = 0x4500c,
2474 .enable_mask = BIT(10),
2475 .hw.init = &(struct clk_init_data){
2476 .name = "gcc_jpeg_tbu_clk",
2477 .parent_names = (const char *[]){
2478 "system_noc_bfdcd_clk_src",
2481 .flags = CLK_SET_RATE_PARENT,
2482 .ops = &clk_branch2_ops,
2487 static struct clk_branch gcc_mdp_tbu_clk = {
2488 .halt_reg = 0x1201c,
2490 .enable_reg = 0x4500c,
2491 .enable_mask = BIT(4),
2492 .hw.init = &(struct clk_init_data){
2493 .name = "gcc_mdp_tbu_clk",
2494 .parent_names = (const char *[]){
2495 "system_noc_bfdcd_clk_src",
2498 .flags = CLK_SET_RATE_PARENT,
2499 .ops = &clk_branch2_ops,
2504 static struct clk_branch gcc_smmu_cfg_clk = {
2505 .halt_reg = 0x12038,
2507 .enable_reg = 0x4500c,
2508 .enable_mask = BIT(12),
2509 .hw.init = &(struct clk_init_data){
2510 .name = "gcc_smmu_cfg_clk",
2511 .parent_names = (const char *[]){
2512 "pcnoc_bfdcd_clk_src",
2515 .flags = CLK_SET_RATE_PARENT,
2516 .ops = &clk_branch2_ops,
2521 static struct clk_branch gcc_venus_tbu_clk = {
2522 .halt_reg = 0x12014,
2524 .enable_reg = 0x4500c,
2525 .enable_mask = BIT(5),
2526 .hw.init = &(struct clk_init_data){
2527 .name = "gcc_venus_tbu_clk",
2528 .parent_names = (const char *[]){
2529 "system_noc_bfdcd_clk_src",
2532 .flags = CLK_SET_RATE_PARENT,
2533 .ops = &clk_branch2_ops,
2538 static struct clk_branch gcc_vfe_tbu_clk = {
2539 .halt_reg = 0x1203c,
2541 .enable_reg = 0x4500c,
2542 .enable_mask = BIT(9),
2543 .hw.init = &(struct clk_init_data){
2544 .name = "gcc_vfe_tbu_clk",
2545 .parent_names = (const char *[]){
2546 "system_noc_bfdcd_clk_src",
2549 .flags = CLK_SET_RATE_PARENT,
2550 .ops = &clk_branch2_ops,
2555 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2556 .halt_reg = 0x4102c,
2558 .enable_reg = 0x4102c,
2559 .enable_mask = BIT(0),
2560 .hw.init = &(struct clk_init_data){
2561 .name = "gcc_usb2a_phy_sleep_clk",
2562 .parent_names = (const char *[]){
2566 .flags = CLK_SET_RATE_PARENT,
2567 .ops = &clk_branch2_ops,
2572 static struct clk_branch gcc_usb_hs_ahb_clk = {
2573 .halt_reg = 0x41008,
2575 .enable_reg = 0x41008,
2576 .enable_mask = BIT(0),
2577 .hw.init = &(struct clk_init_data){
2578 .name = "gcc_usb_hs_ahb_clk",
2579 .parent_names = (const char *[]){
2580 "pcnoc_bfdcd_clk_src",
2583 .flags = CLK_SET_RATE_PARENT,
2584 .ops = &clk_branch2_ops,
2589 static struct clk_branch gcc_usb_hs_system_clk = {
2590 .halt_reg = 0x41004,
2592 .enable_reg = 0x41004,
2593 .enable_mask = BIT(0),
2594 .hw.init = &(struct clk_init_data){
2595 .name = "gcc_usb_hs_system_clk",
2596 .parent_names = (const char *[]){
2597 "usb_hs_system_clk_src",
2600 .flags = CLK_SET_RATE_PARENT,
2601 .ops = &clk_branch2_ops,
2606 static struct clk_branch gcc_venus0_ahb_clk = {
2607 .halt_reg = 0x4c020,
2609 .enable_reg = 0x4c020,
2610 .enable_mask = BIT(0),
2611 .hw.init = &(struct clk_init_data){
2612 .name = "gcc_venus0_ahb_clk",
2613 .parent_names = (const char *[]){
2614 "pcnoc_bfdcd_clk_src",
2617 .flags = CLK_SET_RATE_PARENT,
2618 .ops = &clk_branch2_ops,
2623 static struct clk_branch gcc_venus0_axi_clk = {
2624 .halt_reg = 0x4c024,
2626 .enable_reg = 0x4c024,
2627 .enable_mask = BIT(0),
2628 .hw.init = &(struct clk_init_data){
2629 .name = "gcc_venus0_axi_clk",
2630 .parent_names = (const char *[]){
2631 "system_noc_bfdcd_clk_src",
2634 .flags = CLK_SET_RATE_PARENT,
2635 .ops = &clk_branch2_ops,
2640 static struct clk_branch gcc_venus0_vcodec0_clk = {
2641 .halt_reg = 0x4c01c,
2643 .enable_reg = 0x4c01c,
2644 .enable_mask = BIT(0),
2645 .hw.init = &(struct clk_init_data){
2646 .name = "gcc_venus0_vcodec0_clk",
2647 .parent_names = (const char *[]){
2651 .flags = CLK_SET_RATE_PARENT,
2652 .ops = &clk_branch2_ops,
2657 static struct gdsc venus_gdsc = {
2662 .pwrsts = PWRSTS_OFF_ON,
2665 static struct gdsc mdss_gdsc = {
2670 .pwrsts = PWRSTS_OFF_ON,
2673 static struct gdsc jpeg_gdsc = {
2678 .pwrsts = PWRSTS_OFF_ON,
2681 static struct gdsc vfe_gdsc = {
2686 .pwrsts = PWRSTS_OFF_ON,
2689 static struct gdsc oxili_gdsc = {
2694 .pwrsts = PWRSTS_OFF_ON,
2697 static struct clk_regmap *gcc_msm8916_clocks[] = {
2698 [GPLL0] = &gpll0.clkr,
2699 [GPLL0_VOTE] = &gpll0_vote,
2700 [BIMC_PLL] = &bimc_pll.clkr,
2701 [BIMC_PLL_VOTE] = &bimc_pll_vote,
2702 [GPLL1] = &gpll1.clkr,
2703 [GPLL1_VOTE] = &gpll1_vote,
2704 [GPLL2] = &gpll2.clkr,
2705 [GPLL2_VOTE] = &gpll2_vote,
2706 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
2707 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
2708 [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
2709 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
2710 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2711 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2712 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2713 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2714 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2715 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2716 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2717 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2718 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2719 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2720 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2721 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2722 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2723 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2724 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2725 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2726 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2727 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2728 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2729 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2730 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2731 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2732 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2733 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2734 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2735 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2736 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2737 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
2738 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2739 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2740 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2741 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2742 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2743 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2744 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2745 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2746 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2747 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2748 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2749 [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
2750 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2751 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2752 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2753 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
2754 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2755 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2756 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2757 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2758 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2759 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2760 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2761 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2762 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2763 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2764 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2765 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2766 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2767 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2768 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2769 [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
2770 [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
2771 [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
2772 [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
2773 [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
2774 [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
2775 [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
2776 [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
2777 [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
2778 [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
2779 [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
2780 [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
2781 [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
2782 [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
2783 [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
2784 [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
2785 [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
2786 [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
2787 [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
2788 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
2789 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
2790 [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
2791 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
2792 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
2793 [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
2794 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
2795 [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
2796 [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
2797 [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
2798 [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
2799 [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
2800 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
2801 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
2802 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
2803 [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
2804 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2805 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2806 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2807 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
2808 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
2809 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
2810 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
2811 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
2812 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
2813 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
2814 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2815 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
2816 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
2817 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2818 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2819 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2820 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2821 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2822 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2823 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2824 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
2825 [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
2826 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
2827 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
2828 [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
2829 [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
2830 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2831 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2832 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2833 [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
2834 [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
2835 [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
2836 [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
2837 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
2838 [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
2839 [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
2840 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
2841 [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
2844 static struct gdsc *gcc_msm8916_gdscs[] = {
2845 [VENUS_GDSC] = &venus_gdsc,
2846 [MDSS_GDSC] = &mdss_gdsc,
2847 [JPEG_GDSC] = &jpeg_gdsc,
2848 [VFE_GDSC] = &vfe_gdsc,
2849 [OXILI_GDSC] = &oxili_gdsc,
2852 static const struct qcom_reset_map gcc_msm8916_resets[] = {
2853 [GCC_BLSP1_BCR] = { 0x01000 },
2854 [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
2855 [GCC_BLSP1_UART1_BCR] = { 0x02038 },
2856 [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
2857 [GCC_BLSP1_UART2_BCR] = { 0x03028 },
2858 [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
2859 [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
2860 [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
2861 [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
2862 [GCC_IMEM_BCR] = { 0x0e000 },
2863 [GCC_SMMU_BCR] = { 0x12000 },
2864 [GCC_APSS_TCU_BCR] = { 0x12050 },
2865 [GCC_SMMU_XPU_BCR] = { 0x12054 },
2866 [GCC_PCNOC_TBU_BCR] = { 0x12058 },
2867 [GCC_PRNG_BCR] = { 0x13000 },
2868 [GCC_BOOT_ROM_BCR] = { 0x13008 },
2869 [GCC_CRYPTO_BCR] = { 0x16000 },
2870 [GCC_SEC_CTRL_BCR] = { 0x1a000 },
2871 [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
2872 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
2873 [GCC_DEHR_BCR] = { 0x1f000 },
2874 [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
2875 [GCC_PCNOC_BCR] = { 0x27018 },
2876 [GCC_TCSR_BCR] = { 0x28000 },
2877 [GCC_QDSS_BCR] = { 0x29000 },
2878 [GCC_DCD_BCR] = { 0x2a000 },
2879 [GCC_MSG_RAM_BCR] = { 0x2b000 },
2880 [GCC_MPM_BCR] = { 0x2c000 },
2881 [GCC_SPMI_BCR] = { 0x2e000 },
2882 [GCC_SPDM_BCR] = { 0x2f000 },
2883 [GCC_MM_SPDM_BCR] = { 0x2f024 },
2884 [GCC_BIMC_BCR] = { 0x31000 },
2885 [GCC_RBCPR_BCR] = { 0x33000 },
2886 [GCC_TLMM_BCR] = { 0x34000 },
2887 [GCC_USB_HS_BCR] = { 0x41000 },
2888 [GCC_USB2A_PHY_BCR] = { 0x41028 },
2889 [GCC_SDCC1_BCR] = { 0x42000 },
2890 [GCC_SDCC2_BCR] = { 0x43000 },
2891 [GCC_PDM_BCR] = { 0x44000 },
2892 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
2893 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
2894 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
2895 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
2896 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
2897 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
2898 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
2899 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
2900 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
2901 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
2902 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
2903 [GCC_MMSS_BCR] = { 0x4b000 },
2904 [GCC_VENUS0_BCR] = { 0x4c014 },
2905 [GCC_MDSS_BCR] = { 0x4d074 },
2906 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
2907 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
2908 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
2909 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
2910 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
2911 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
2912 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
2913 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
2914 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
2915 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
2916 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
2917 [GCC_CAMSS_CCI_BCR] = { 0x51014 },
2918 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
2919 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
2920 [GCC_CAMSS_GP0_BCR] = { 0x54014 },
2921 [GCC_CAMSS_GP1_BCR] = { 0x55014 },
2922 [GCC_CAMSS_TOP_BCR] = { 0x56000 },
2923 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
2924 [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
2925 [GCC_CAMSS_VFE_BCR] = { 0x58030 },
2926 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
2927 [GCC_OXILI_BCR] = { 0x59018 },
2928 [GCC_GMEM_BCR] = { 0x5902c },
2929 [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
2930 [GCC_MDP_TBU_BCR] = { 0x62000 },
2931 [GCC_GFX_TBU_BCR] = { 0x63000 },
2932 [GCC_GFX_TCU_BCR] = { 0x64000 },
2933 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
2934 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
2935 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
2936 [GCC_GTCU_AHB_BCR] = { 0x68000 },
2937 [GCC_SMMU_CFG_BCR] = { 0x69000 },
2938 [GCC_VFE_TBU_BCR] = { 0x6a000 },
2939 [GCC_VENUS_TBU_BCR] = { 0x6b000 },
2940 [GCC_JPEG_TBU_BCR] = { 0x6c000 },
2941 [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
2942 [GCC_SMMU_CATS_BCR] = { 0x7c000 },
2945 static const struct regmap_config gcc_msm8916_regmap_config = {
2949 .max_register = 0x80000,
2953 static const struct qcom_cc_desc gcc_msm8916_desc = {
2954 .config = &gcc_msm8916_regmap_config,
2955 .clks = gcc_msm8916_clocks,
2956 .num_clks = ARRAY_SIZE(gcc_msm8916_clocks),
2957 .resets = gcc_msm8916_resets,
2958 .num_resets = ARRAY_SIZE(gcc_msm8916_resets),
2959 .gdscs = gcc_msm8916_gdscs,
2960 .num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs),
2963 static const struct of_device_id gcc_msm8916_match_table[] = {
2964 { .compatible = "qcom,gcc-msm8916" },
2967 MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table);
2969 static int gcc_msm8916_probe(struct platform_device *pdev)
2972 struct device *dev = &pdev->dev;
2974 /* Temporary until RPM clocks supported */
2975 clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
2977 return PTR_ERR(clk);
2979 clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
2980 CLK_IS_ROOT, 32768);
2982 return PTR_ERR(clk);
2984 return qcom_cc_probe(pdev, &gcc_msm8916_desc);
2987 static int gcc_msm8916_remove(struct platform_device *pdev)
2989 qcom_cc_remove(pdev);
2993 static struct platform_driver gcc_msm8916_driver = {
2994 .probe = gcc_msm8916_probe,
2995 .remove = gcc_msm8916_remove,
2997 .name = "gcc-msm8916",
2998 .of_match_table = gcc_msm8916_match_table,
3002 static int __init gcc_msm8916_init(void)
3004 return platform_driver_register(&gcc_msm8916_driver);
3006 core_initcall(gcc_msm8916_init);
3008 static void __exit gcc_msm8916_exit(void)
3010 platform_driver_unregister(&gcc_msm8916_driver);
3012 module_exit(gcc_msm8916_exit);
3014 MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver");
3015 MODULE_LICENSE("GPL v2");
3016 MODULE_ALIAS("platform:gcc-msm8916");