2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
24 #include <linux/clk.h>
26 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
29 #include "clk-regmap.h"
30 #include "clk-regmap-divider.h"
31 #include "clk-alpha-pll.h"
33 #include "clk-branch.h"
37 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
58 static const struct parent_map mmss_xo_hdmi_map[] = {
63 static const char * const mmss_xo_hdmi[] = {
68 static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
74 static const char * const mmss_xo_dsi0pll_dsi1pll[] = {
80 static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
86 static const char * const mmss_xo_gpll0_gpll0_div[] = {
92 static const struct parent_map mmss_xo_dsibyte_map[] = {
94 { P_DSI0PLL_BYTE, 1 },
98 static const char * const mmss_xo_dsibyte[] = {
104 static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
111 static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = {
118 static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
126 static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
134 static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = {
142 static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = {
150 static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
158 static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
166 static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = {
174 static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = {
182 static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = {
191 static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = {
200 static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = {
210 static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = {
220 static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = {
230 static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = {
240 static struct clk_fixed_factor gpll0_div = {
243 .hw.init = &(struct clk_init_data){
245 .parent_names = (const char *[]){ "gpll0" },
247 .ops = &clk_fixed_factor_ops,
251 static struct pll_vco mmpll_p_vco[] = {
252 { 250000000, 500000000, 3 },
253 { 500000000, 1000000000, 2 },
254 { 1000000000, 1500000000, 1 },
255 { 1500000000, 2000000000, 0 },
258 static struct pll_vco mmpll_gfx_vco[] = {
259 { 400000000, 1000000000, 2 },
260 { 1000000000, 1500000000, 1 },
261 { 1500000000, 2000000000, 0 },
264 static struct pll_vco mmpll_t_vco[] = {
265 { 500000000, 1500000000, 0 },
268 static struct clk_alpha_pll mmpll0_early = {
270 .vco_table = mmpll_p_vco,
271 .num_vco = ARRAY_SIZE(mmpll_p_vco),
274 .enable_mask = BIT(0),
275 .hw.init = &(struct clk_init_data){
276 .name = "mmpll0_early",
277 .parent_names = (const char *[]){ "xo" },
279 .ops = &clk_alpha_pll_ops,
284 static struct clk_alpha_pll_postdiv mmpll0 = {
287 .clkr.hw.init = &(struct clk_init_data){
289 .parent_names = (const char *[]){ "mmpll0_early" },
291 .ops = &clk_alpha_pll_postdiv_ops,
292 .flags = CLK_SET_RATE_PARENT,
296 static struct clk_alpha_pll mmpll1_early = {
298 .vco_table = mmpll_p_vco,
299 .num_vco = ARRAY_SIZE(mmpll_p_vco),
302 .enable_mask = BIT(1),
303 .hw.init = &(struct clk_init_data){
304 .name = "mmpll1_early",
305 .parent_names = (const char *[]){ "xo" },
307 .ops = &clk_alpha_pll_ops,
312 static struct clk_alpha_pll_postdiv mmpll1 = {
315 .clkr.hw.init = &(struct clk_init_data){
317 .parent_names = (const char *[]){ "mmpll1_early" },
319 .ops = &clk_alpha_pll_postdiv_ops,
320 .flags = CLK_SET_RATE_PARENT,
324 static struct clk_alpha_pll mmpll2_early = {
326 .vco_table = mmpll_gfx_vco,
327 .num_vco = ARRAY_SIZE(mmpll_gfx_vco),
328 .clkr.hw.init = &(struct clk_init_data){
329 .name = "mmpll2_early",
330 .parent_names = (const char *[]){ "xo" },
332 .ops = &clk_alpha_pll_ops,
336 static struct clk_alpha_pll_postdiv mmpll2 = {
339 .clkr.hw.init = &(struct clk_init_data){
341 .parent_names = (const char *[]){ "mmpll2_early" },
343 .ops = &clk_alpha_pll_postdiv_ops,
344 .flags = CLK_SET_RATE_PARENT,
348 static struct clk_alpha_pll mmpll3_early = {
350 .vco_table = mmpll_p_vco,
351 .num_vco = ARRAY_SIZE(mmpll_p_vco),
352 .clkr.hw.init = &(struct clk_init_data){
353 .name = "mmpll3_early",
354 .parent_names = (const char *[]){ "xo" },
356 .ops = &clk_alpha_pll_ops,
360 static struct clk_alpha_pll_postdiv mmpll3 = {
363 .clkr.hw.init = &(struct clk_init_data){
365 .parent_names = (const char *[]){ "mmpll3_early" },
367 .ops = &clk_alpha_pll_postdiv_ops,
368 .flags = CLK_SET_RATE_PARENT,
372 static struct clk_alpha_pll mmpll4_early = {
374 .vco_table = mmpll_t_vco,
375 .num_vco = ARRAY_SIZE(mmpll_t_vco),
376 .clkr.hw.init = &(struct clk_init_data){
377 .name = "mmpll4_early",
378 .parent_names = (const char *[]){ "xo" },
380 .ops = &clk_alpha_pll_ops,
384 static struct clk_alpha_pll_postdiv mmpll4 = {
387 .clkr.hw.init = &(struct clk_init_data){
389 .parent_names = (const char *[]){ "mmpll4_early" },
391 .ops = &clk_alpha_pll_postdiv_ops,
392 .flags = CLK_SET_RATE_PARENT,
396 static struct clk_alpha_pll mmpll5_early = {
398 .vco_table = mmpll_p_vco,
399 .num_vco = ARRAY_SIZE(mmpll_p_vco),
400 .clkr.hw.init = &(struct clk_init_data){
401 .name = "mmpll5_early",
402 .parent_names = (const char *[]){ "xo" },
404 .ops = &clk_alpha_pll_ops,
408 static struct clk_alpha_pll_postdiv mmpll5 = {
411 .clkr.hw.init = &(struct clk_init_data){
413 .parent_names = (const char *[]){ "mmpll5_early" },
415 .ops = &clk_alpha_pll_postdiv_ops,
416 .flags = CLK_SET_RATE_PARENT,
420 static struct clk_alpha_pll mmpll8_early = {
422 .vco_table = mmpll_gfx_vco,
423 .num_vco = ARRAY_SIZE(mmpll_gfx_vco),
424 .clkr.hw.init = &(struct clk_init_data){
425 .name = "mmpll8_early",
426 .parent_names = (const char *[]){ "xo" },
428 .ops = &clk_alpha_pll_ops,
432 static struct clk_alpha_pll_postdiv mmpll8 = {
435 .clkr.hw.init = &(struct clk_init_data){
437 .parent_names = (const char *[]){ "mmpll8_early" },
439 .ops = &clk_alpha_pll_postdiv_ops,
440 .flags = CLK_SET_RATE_PARENT,
444 static struct clk_alpha_pll mmpll9_early = {
446 .vco_table = mmpll_t_vco,
447 .num_vco = ARRAY_SIZE(mmpll_t_vco),
448 .clkr.hw.init = &(struct clk_init_data){
449 .name = "mmpll9_early",
450 .parent_names = (const char *[]){ "xo" },
452 .ops = &clk_alpha_pll_ops,
456 static struct clk_alpha_pll_postdiv mmpll9 = {
459 .clkr.hw.init = &(struct clk_init_data){
461 .parent_names = (const char *[]){ "mmpll9_early" },
463 .ops = &clk_alpha_pll_postdiv_ops,
464 .flags = CLK_SET_RATE_PARENT,
468 static const struct freq_tbl ftbl_ahb_clk_src[] = {
469 F(19200000, P_XO, 1, 0, 0),
470 F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
471 F(80000000, P_MMPLL0, 10, 0, 0),
475 static struct clk_rcg2 ahb_clk_src = {
478 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
479 .freq_tbl = ftbl_ahb_clk_src,
480 .clkr.hw.init = &(struct clk_init_data){
481 .name = "ahb_clk_src",
482 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
484 .ops = &clk_rcg2_ops,
488 static const struct freq_tbl ftbl_axi_clk_src[] = {
489 F(19200000, P_XO, 1, 0, 0),
490 F(75000000, P_GPLL0_DIV, 4, 0, 0),
491 F(100000000, P_GPLL0, 6, 0, 0),
492 F(171430000, P_GPLL0, 3.5, 0, 0),
493 F(200000000, P_GPLL0, 3, 0, 0),
494 F(320000000, P_MMPLL0, 2.5, 0, 0),
495 F(400000000, P_MMPLL0, 2, 0, 0),
499 static struct clk_rcg2 axi_clk_src = {
502 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
503 .freq_tbl = ftbl_axi_clk_src,
504 .clkr.hw.init = &(struct clk_init_data){
505 .name = "axi_clk_src",
506 .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
508 .ops = &clk_rcg2_ops,
512 static struct clk_rcg2 maxi_clk_src = {
515 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
516 .freq_tbl = ftbl_axi_clk_src,
517 .clkr.hw.init = &(struct clk_init_data){
518 .name = "maxi_clk_src",
519 .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
521 .ops = &clk_rcg2_ops,
525 static struct clk_rcg2 gfx3d_clk_src = {
528 .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
529 .clkr.hw.init = &(struct clk_init_data){
530 .name = "gfx3d_clk_src",
531 .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
533 .ops = &clk_gfx3d_ops,
534 .flags = CLK_SET_RATE_PARENT,
538 static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
539 F(19200000, P_XO, 1, 0, 0),
543 static struct clk_rcg2 rbbmtimer_clk_src = {
546 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
547 .freq_tbl = ftbl_rbbmtimer_clk_src,
548 .clkr.hw.init = &(struct clk_init_data){
549 .name = "rbbmtimer_clk_src",
550 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
552 .ops = &clk_rcg2_ops,
556 static struct clk_rcg2 isense_clk_src = {
559 .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map,
560 .clkr.hw.init = &(struct clk_init_data){
561 .name = "isense_clk_src",
562 .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div,
564 .ops = &clk_rcg2_ops,
568 static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
569 F(19200000, P_XO, 1, 0, 0),
570 F(50000000, P_GPLL0, 12, 0, 0),
574 static struct clk_rcg2 rbcpr_clk_src = {
577 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
578 .freq_tbl = ftbl_rbcpr_clk_src,
579 .clkr.hw.init = &(struct clk_init_data){
580 .name = "rbcpr_clk_src",
581 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
583 .ops = &clk_rcg2_ops,
587 static const struct freq_tbl ftbl_video_core_clk_src[] = {
588 F(75000000, P_GPLL0_DIV, 4, 0, 0),
589 F(150000000, P_GPLL0, 4, 0, 0),
590 F(346666667, P_MMPLL3, 3, 0, 0),
591 F(520000000, P_MMPLL3, 2, 0, 0),
595 static struct clk_rcg2 video_core_clk_src = {
599 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
600 .freq_tbl = ftbl_video_core_clk_src,
601 .clkr.hw.init = &(struct clk_init_data){
602 .name = "video_core_clk_src",
603 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
605 .ops = &clk_rcg2_ops,
609 static struct clk_rcg2 video_subcore0_clk_src = {
613 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
614 .freq_tbl = ftbl_video_core_clk_src,
615 .clkr.hw.init = &(struct clk_init_data){
616 .name = "video_subcore0_clk_src",
617 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
619 .ops = &clk_rcg2_ops,
623 static struct clk_rcg2 video_subcore1_clk_src = {
627 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
628 .freq_tbl = ftbl_video_core_clk_src,
629 .clkr.hw.init = &(struct clk_init_data){
630 .name = "video_subcore1_clk_src",
631 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
633 .ops = &clk_rcg2_ops,
637 static struct clk_rcg2 pclk0_clk_src = {
641 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
642 .clkr.hw.init = &(struct clk_init_data){
643 .name = "pclk0_clk_src",
644 .parent_names = mmss_xo_dsi0pll_dsi1pll,
646 .ops = &clk_pixel_ops,
647 .flags = CLK_SET_RATE_PARENT,
651 static struct clk_rcg2 pclk1_clk_src = {
655 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
656 .clkr.hw.init = &(struct clk_init_data){
657 .name = "pclk1_clk_src",
658 .parent_names = mmss_xo_dsi0pll_dsi1pll,
660 .ops = &clk_pixel_ops,
661 .flags = CLK_SET_RATE_PARENT,
665 static const struct freq_tbl ftbl_mdp_clk_src[] = {
666 F(85714286, P_GPLL0, 7, 0, 0),
667 F(100000000, P_GPLL0, 6, 0, 0),
668 F(150000000, P_GPLL0, 4, 0, 0),
669 F(171428571, P_GPLL0, 3.5, 0, 0),
670 F(200000000, P_GPLL0, 3, 0, 0),
671 F(275000000, P_MMPLL5, 3, 0, 0),
672 F(300000000, P_GPLL0, 2, 0, 0),
673 F(330000000, P_MMPLL5, 2.5, 0, 0),
674 F(412500000, P_MMPLL5, 2, 0, 0),
678 static struct clk_rcg2 mdp_clk_src = {
681 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
682 .freq_tbl = ftbl_mdp_clk_src,
683 .clkr.hw.init = &(struct clk_init_data){
684 .name = "mdp_clk_src",
685 .parent_names = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
687 .ops = &clk_rcg2_ops,
691 static struct freq_tbl extpclk_freq_tbl[] = {
692 { .src = P_HDMIPLL },
696 static struct clk_rcg2 extpclk_clk_src = {
699 .parent_map = mmss_xo_hdmi_map,
700 .freq_tbl = extpclk_freq_tbl,
701 .clkr.hw.init = &(struct clk_init_data){
702 .name = "extpclk_clk_src",
703 .parent_names = mmss_xo_hdmi,
705 .ops = &clk_byte_ops,
706 .flags = CLK_SET_RATE_PARENT,
710 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
711 F(19200000, P_XO, 1, 0, 0),
715 static struct clk_rcg2 vsync_clk_src = {
718 .parent_map = mmss_xo_gpll0_gpll0_div_map,
719 .freq_tbl = ftbl_mdss_vsync_clk,
720 .clkr.hw.init = &(struct clk_init_data){
721 .name = "vsync_clk_src",
722 .parent_names = mmss_xo_gpll0_gpll0_div,
724 .ops = &clk_rcg2_ops,
728 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
729 F(19200000, P_XO, 1, 0, 0),
733 static struct clk_rcg2 hdmi_clk_src = {
736 .parent_map = mmss_xo_gpll0_gpll0_div_map,
737 .freq_tbl = ftbl_mdss_hdmi_clk,
738 .clkr.hw.init = &(struct clk_init_data){
739 .name = "hdmi_clk_src",
740 .parent_names = mmss_xo_gpll0_gpll0_div,
742 .ops = &clk_rcg2_ops,
746 static struct clk_rcg2 byte0_clk_src = {
749 .parent_map = mmss_xo_dsibyte_map,
750 .clkr.hw.init = &(struct clk_init_data){
751 .name = "byte0_clk_src",
752 .parent_names = mmss_xo_dsibyte,
754 .ops = &clk_byte2_ops,
755 .flags = CLK_SET_RATE_PARENT,
759 static struct clk_rcg2 byte1_clk_src = {
762 .parent_map = mmss_xo_dsibyte_map,
763 .clkr.hw.init = &(struct clk_init_data){
764 .name = "byte1_clk_src",
765 .parent_names = mmss_xo_dsibyte,
767 .ops = &clk_byte2_ops,
768 .flags = CLK_SET_RATE_PARENT,
772 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
773 F(19200000, P_XO, 1, 0, 0),
777 static struct clk_rcg2 esc0_clk_src = {
780 .parent_map = mmss_xo_dsibyte_map,
781 .freq_tbl = ftbl_mdss_esc0_1_clk,
782 .clkr.hw.init = &(struct clk_init_data){
783 .name = "esc0_clk_src",
784 .parent_names = mmss_xo_dsibyte,
786 .ops = &clk_rcg2_ops,
790 static struct clk_rcg2 esc1_clk_src = {
793 .parent_map = mmss_xo_dsibyte_map,
794 .freq_tbl = ftbl_mdss_esc0_1_clk,
795 .clkr.hw.init = &(struct clk_init_data){
796 .name = "esc1_clk_src",
797 .parent_names = mmss_xo_dsibyte,
799 .ops = &clk_rcg2_ops,
803 static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {
804 F(10000, P_XO, 16, 1, 120),
805 F(24000, P_XO, 16, 1, 50),
806 F(6000000, P_GPLL0_DIV, 10, 1, 5),
807 F(12000000, P_GPLL0_DIV, 1, 1, 25),
808 F(13000000, P_GPLL0_DIV, 2, 13, 150),
809 F(24000000, P_GPLL0_DIV, 1, 2, 25),
813 static struct clk_rcg2 camss_gp0_clk_src = {
817 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
818 .freq_tbl = ftbl_camss_gp0_clk_src,
819 .clkr.hw.init = &(struct clk_init_data){
820 .name = "camss_gp0_clk_src",
821 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
823 .ops = &clk_rcg2_ops,
827 static struct clk_rcg2 camss_gp1_clk_src = {
831 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
832 .freq_tbl = ftbl_camss_gp0_clk_src,
833 .clkr.hw.init = &(struct clk_init_data){
834 .name = "camss_gp1_clk_src",
835 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
837 .ops = &clk_rcg2_ops,
841 static const struct freq_tbl ftbl_mclk0_clk_src[] = {
842 F(4800000, P_XO, 4, 0, 0),
843 F(6000000, P_GPLL0_DIV, 10, 1, 5),
844 F(8000000, P_GPLL0_DIV, 1, 2, 75),
845 F(9600000, P_XO, 2, 0, 0),
846 F(16666667, P_GPLL0_DIV, 2, 1, 9),
847 F(19200000, P_XO, 1, 0, 0),
848 F(24000000, P_GPLL0_DIV, 1, 2, 25),
849 F(33333333, P_GPLL0_DIV, 1, 1, 9),
850 F(48000000, P_GPLL0, 1, 2, 25),
851 F(66666667, P_GPLL0, 1, 1, 9),
855 static struct clk_rcg2 mclk0_clk_src = {
859 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
860 .freq_tbl = ftbl_mclk0_clk_src,
861 .clkr.hw.init = &(struct clk_init_data){
862 .name = "mclk0_clk_src",
863 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
865 .ops = &clk_rcg2_ops,
869 static struct clk_rcg2 mclk1_clk_src = {
873 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
874 .freq_tbl = ftbl_mclk0_clk_src,
875 .clkr.hw.init = &(struct clk_init_data){
876 .name = "mclk1_clk_src",
877 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
879 .ops = &clk_rcg2_ops,
883 static struct clk_rcg2 mclk2_clk_src = {
887 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
888 .freq_tbl = ftbl_mclk0_clk_src,
889 .clkr.hw.init = &(struct clk_init_data){
890 .name = "mclk2_clk_src",
891 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
893 .ops = &clk_rcg2_ops,
897 static struct clk_rcg2 mclk3_clk_src = {
901 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
902 .freq_tbl = ftbl_mclk0_clk_src,
903 .clkr.hw.init = &(struct clk_init_data){
904 .name = "mclk3_clk_src",
905 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
907 .ops = &clk_rcg2_ops,
911 static const struct freq_tbl ftbl_cci_clk_src[] = {
912 F(19200000, P_XO, 1, 0, 0),
913 F(37500000, P_GPLL0, 16, 0, 0),
914 F(50000000, P_GPLL0, 12, 0, 0),
915 F(100000000, P_GPLL0, 6, 0, 0),
919 static struct clk_rcg2 cci_clk_src = {
923 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
924 .freq_tbl = ftbl_cci_clk_src,
925 .clkr.hw.init = &(struct clk_init_data){
926 .name = "cci_clk_src",
927 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
929 .ops = &clk_rcg2_ops,
933 static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {
934 F(100000000, P_GPLL0_DIV, 3, 0, 0),
935 F(200000000, P_GPLL0, 3, 0, 0),
936 F(266666667, P_MMPLL0, 3, 0, 0),
940 static struct clk_rcg2 csi0phytimer_clk_src = {
943 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
944 .freq_tbl = ftbl_csi0phytimer_clk_src,
945 .clkr.hw.init = &(struct clk_init_data){
946 .name = "csi0phytimer_clk_src",
947 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
949 .ops = &clk_rcg2_ops,
953 static struct clk_rcg2 csi1phytimer_clk_src = {
956 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
957 .freq_tbl = ftbl_csi0phytimer_clk_src,
958 .clkr.hw.init = &(struct clk_init_data){
959 .name = "csi1phytimer_clk_src",
960 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
962 .ops = &clk_rcg2_ops,
966 static struct clk_rcg2 csi2phytimer_clk_src = {
969 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
970 .freq_tbl = ftbl_csi0phytimer_clk_src,
971 .clkr.hw.init = &(struct clk_init_data){
972 .name = "csi2phytimer_clk_src",
973 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
975 .ops = &clk_rcg2_ops,
979 static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = {
980 F(100000000, P_GPLL0_DIV, 3, 0, 0),
981 F(200000000, P_GPLL0, 3, 0, 0),
982 F(320000000, P_MMPLL4, 3, 0, 0),
983 F(384000000, P_MMPLL4, 2.5, 0, 0),
987 static struct clk_rcg2 csiphy0_3p_clk_src = {
990 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
991 .freq_tbl = ftbl_csiphy0_3p_clk_src,
992 .clkr.hw.init = &(struct clk_init_data){
993 .name = "csiphy0_3p_clk_src",
994 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
996 .ops = &clk_rcg2_ops,
1000 static struct clk_rcg2 csiphy1_3p_clk_src = {
1003 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1004 .freq_tbl = ftbl_csiphy0_3p_clk_src,
1005 .clkr.hw.init = &(struct clk_init_data){
1006 .name = "csiphy1_3p_clk_src",
1007 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1009 .ops = &clk_rcg2_ops,
1013 static struct clk_rcg2 csiphy2_3p_clk_src = {
1016 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1017 .freq_tbl = ftbl_csiphy0_3p_clk_src,
1018 .clkr.hw.init = &(struct clk_init_data){
1019 .name = "csiphy2_3p_clk_src",
1020 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1022 .ops = &clk_rcg2_ops,
1026 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
1027 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1028 F(150000000, P_GPLL0, 4, 0, 0),
1029 F(228571429, P_MMPLL0, 3.5, 0, 0),
1030 F(266666667, P_MMPLL0, 3, 0, 0),
1031 F(320000000, P_MMPLL0, 2.5, 0, 0),
1032 F(480000000, P_MMPLL4, 2, 0, 0),
1036 static struct clk_rcg2 jpeg0_clk_src = {
1039 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1040 .freq_tbl = ftbl_jpeg0_clk_src,
1041 .clkr.hw.init = &(struct clk_init_data){
1042 .name = "jpeg0_clk_src",
1043 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1045 .ops = &clk_rcg2_ops,
1049 static const struct freq_tbl ftbl_jpeg2_clk_src[] = {
1050 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1051 F(150000000, P_GPLL0, 4, 0, 0),
1052 F(228571429, P_MMPLL0, 3.5, 0, 0),
1053 F(266666667, P_MMPLL0, 3, 0, 0),
1054 F(320000000, P_MMPLL0, 2.5, 0, 0),
1058 static struct clk_rcg2 jpeg2_clk_src = {
1061 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1062 .freq_tbl = ftbl_jpeg2_clk_src,
1063 .clkr.hw.init = &(struct clk_init_data){
1064 .name = "jpeg2_clk_src",
1065 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1067 .ops = &clk_rcg2_ops,
1071 static struct clk_rcg2 jpeg_dma_clk_src = {
1074 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1075 .freq_tbl = ftbl_jpeg0_clk_src,
1076 .clkr.hw.init = &(struct clk_init_data){
1077 .name = "jpeg_dma_clk_src",
1078 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1080 .ops = &clk_rcg2_ops,
1084 static const struct freq_tbl ftbl_vfe0_clk_src[] = {
1085 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1086 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1087 F(300000000, P_GPLL0, 2, 0, 0),
1088 F(320000000, P_MMPLL0, 2.5, 0, 0),
1089 F(480000000, P_MMPLL4, 2, 0, 0),
1090 F(600000000, P_GPLL0, 1, 0, 0),
1094 static struct clk_rcg2 vfe0_clk_src = {
1097 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1098 .freq_tbl = ftbl_vfe0_clk_src,
1099 .clkr.hw.init = &(struct clk_init_data){
1100 .name = "vfe0_clk_src",
1101 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1103 .ops = &clk_rcg2_ops,
1107 static struct clk_rcg2 vfe1_clk_src = {
1110 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1111 .freq_tbl = ftbl_vfe0_clk_src,
1112 .clkr.hw.init = &(struct clk_init_data){
1113 .name = "vfe1_clk_src",
1114 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1116 .ops = &clk_rcg2_ops,
1120 static const struct freq_tbl ftbl_cpp_clk_src[] = {
1121 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1122 F(200000000, P_GPLL0, 3, 0, 0),
1123 F(320000000, P_MMPLL0, 2.5, 0, 0),
1124 F(480000000, P_MMPLL4, 2, 0, 0),
1125 F(640000000, P_MMPLL4, 1.5, 0, 0),
1129 static struct clk_rcg2 cpp_clk_src = {
1132 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1133 .freq_tbl = ftbl_cpp_clk_src,
1134 .clkr.hw.init = &(struct clk_init_data){
1135 .name = "cpp_clk_src",
1136 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1138 .ops = &clk_rcg2_ops,
1142 static const struct freq_tbl ftbl_csi0_clk_src[] = {
1143 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1144 F(200000000, P_GPLL0, 3, 0, 0),
1145 F(266666667, P_MMPLL0, 3, 0, 0),
1146 F(480000000, P_MMPLL4, 2, 0, 0),
1147 F(600000000, P_GPLL0, 1, 0, 0),
1151 static struct clk_rcg2 csi0_clk_src = {
1154 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1155 .freq_tbl = ftbl_csi0_clk_src,
1156 .clkr.hw.init = &(struct clk_init_data){
1157 .name = "csi0_clk_src",
1158 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1160 .ops = &clk_rcg2_ops,
1164 static struct clk_rcg2 csi1_clk_src = {
1167 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1168 .freq_tbl = ftbl_csi0_clk_src,
1169 .clkr.hw.init = &(struct clk_init_data){
1170 .name = "csi1_clk_src",
1171 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1173 .ops = &clk_rcg2_ops,
1177 static struct clk_rcg2 csi2_clk_src = {
1180 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1181 .freq_tbl = ftbl_csi0_clk_src,
1182 .clkr.hw.init = &(struct clk_init_data){
1183 .name = "csi2_clk_src",
1184 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1186 .ops = &clk_rcg2_ops,
1190 static struct clk_rcg2 csi3_clk_src = {
1193 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1194 .freq_tbl = ftbl_csi0_clk_src,
1195 .clkr.hw.init = &(struct clk_init_data){
1196 .name = "csi3_clk_src",
1197 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1199 .ops = &clk_rcg2_ops,
1203 static const struct freq_tbl ftbl_fd_core_clk_src[] = {
1204 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1205 F(200000000, P_GPLL0, 3, 0, 0),
1206 F(400000000, P_MMPLL0, 2, 0, 0),
1210 static struct clk_rcg2 fd_core_clk_src = {
1213 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
1214 .freq_tbl = ftbl_fd_core_clk_src,
1215 .clkr.hw.init = &(struct clk_init_data){
1216 .name = "fd_core_clk_src",
1217 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
1219 .ops = &clk_rcg2_ops,
1223 static struct clk_branch mmss_mmagic_ahb_clk = {
1226 .enable_reg = 0x5024,
1227 .enable_mask = BIT(0),
1228 .hw.init = &(struct clk_init_data){
1229 .name = "mmss_mmagic_ahb_clk",
1230 .parent_names = (const char *[]){ "ahb_clk_src" },
1232 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1233 .ops = &clk_branch2_ops,
1238 static struct clk_branch mmss_mmagic_cfg_ahb_clk = {
1241 .enable_reg = 0x5054,
1242 .enable_mask = BIT(0),
1243 .hw.init = &(struct clk_init_data){
1244 .name = "mmss_mmagic_cfg_ahb_clk",
1245 .parent_names = (const char *[]){ "ahb_clk_src" },
1247 .flags = CLK_SET_RATE_PARENT,
1248 .ops = &clk_branch2_ops,
1253 static struct clk_branch mmss_misc_ahb_clk = {
1256 .enable_reg = 0x5018,
1257 .enable_mask = BIT(0),
1258 .hw.init = &(struct clk_init_data){
1259 .name = "mmss_misc_ahb_clk",
1260 .parent_names = (const char *[]){ "ahb_clk_src" },
1262 .flags = CLK_SET_RATE_PARENT,
1263 .ops = &clk_branch2_ops,
1268 static struct clk_branch mmss_misc_cxo_clk = {
1271 .enable_reg = 0x5014,
1272 .enable_mask = BIT(0),
1273 .hw.init = &(struct clk_init_data){
1274 .name = "mmss_misc_cxo_clk",
1275 .parent_names = (const char *[]){ "xo" },
1277 .ops = &clk_branch2_ops,
1282 static struct clk_branch mmss_mmagic_maxi_clk = {
1285 .enable_reg = 0x5074,
1286 .enable_mask = BIT(0),
1287 .hw.init = &(struct clk_init_data){
1288 .name = "mmss_mmagic_maxi_clk",
1289 .parent_names = (const char *[]){ "maxi_clk_src" },
1291 .flags = CLK_SET_RATE_PARENT,
1292 .ops = &clk_branch2_ops,
1297 static struct clk_branch mmagic_camss_axi_clk = {
1300 .enable_reg = 0x3c44,
1301 .enable_mask = BIT(0),
1302 .hw.init = &(struct clk_init_data){
1303 .name = "mmagic_camss_axi_clk",
1304 .parent_names = (const char *[]){ "axi_clk_src" },
1306 .flags = CLK_SET_RATE_PARENT,
1307 .ops = &clk_branch2_ops,
1312 static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = {
1315 .enable_reg = 0x3c48,
1316 .enable_mask = BIT(0),
1317 .hw.init = &(struct clk_init_data){
1318 .name = "mmagic_camss_noc_cfg_ahb_clk",
1319 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1321 .flags = CLK_SET_RATE_PARENT,
1322 .ops = &clk_branch2_ops,
1327 static struct clk_branch smmu_vfe_ahb_clk = {
1330 .enable_reg = 0x3c04,
1331 .enable_mask = BIT(0),
1332 .hw.init = &(struct clk_init_data){
1333 .name = "smmu_vfe_ahb_clk",
1334 .parent_names = (const char *[]){ "ahb_clk_src" },
1336 .flags = CLK_SET_RATE_PARENT,
1337 .ops = &clk_branch2_ops,
1342 static struct clk_branch smmu_vfe_axi_clk = {
1345 .enable_reg = 0x3c08,
1346 .enable_mask = BIT(0),
1347 .hw.init = &(struct clk_init_data){
1348 .name = "smmu_vfe_axi_clk",
1349 .parent_names = (const char *[]){ "axi_clk_src" },
1351 .flags = CLK_SET_RATE_PARENT,
1352 .ops = &clk_branch2_ops,
1357 static struct clk_branch smmu_cpp_ahb_clk = {
1360 .enable_reg = 0x3c14,
1361 .enable_mask = BIT(0),
1362 .hw.init = &(struct clk_init_data){
1363 .name = "smmu_cpp_ahb_clk",
1364 .parent_names = (const char *[]){ "ahb_clk_src" },
1366 .flags = CLK_SET_RATE_PARENT,
1367 .ops = &clk_branch2_ops,
1372 static struct clk_branch smmu_cpp_axi_clk = {
1375 .enable_reg = 0x3c18,
1376 .enable_mask = BIT(0),
1377 .hw.init = &(struct clk_init_data){
1378 .name = "smmu_cpp_axi_clk",
1379 .parent_names = (const char *[]){ "axi_clk_src" },
1381 .flags = CLK_SET_RATE_PARENT,
1382 .ops = &clk_branch2_ops,
1387 static struct clk_branch smmu_jpeg_ahb_clk = {
1390 .enable_reg = 0x3c24,
1391 .enable_mask = BIT(0),
1392 .hw.init = &(struct clk_init_data){
1393 .name = "smmu_jpeg_ahb_clk",
1394 .parent_names = (const char *[]){ "ahb_clk_src" },
1396 .flags = CLK_SET_RATE_PARENT,
1397 .ops = &clk_branch2_ops,
1402 static struct clk_branch smmu_jpeg_axi_clk = {
1405 .enable_reg = 0x3c28,
1406 .enable_mask = BIT(0),
1407 .hw.init = &(struct clk_init_data){
1408 .name = "smmu_jpeg_axi_clk",
1409 .parent_names = (const char *[]){ "axi_clk_src" },
1411 .flags = CLK_SET_RATE_PARENT,
1412 .ops = &clk_branch2_ops,
1417 static struct clk_branch mmagic_mdss_axi_clk = {
1420 .enable_reg = 0x2474,
1421 .enable_mask = BIT(0),
1422 .hw.init = &(struct clk_init_data){
1423 .name = "mmagic_mdss_axi_clk",
1424 .parent_names = (const char *[]){ "axi_clk_src" },
1426 .flags = CLK_SET_RATE_PARENT,
1427 .ops = &clk_branch2_ops,
1432 static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = {
1435 .enable_reg = 0x2478,
1436 .enable_mask = BIT(0),
1437 .hw.init = &(struct clk_init_data){
1438 .name = "mmagic_mdss_noc_cfg_ahb_clk",
1439 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1441 .flags = CLK_SET_RATE_PARENT,
1442 .ops = &clk_branch2_ops,
1447 static struct clk_branch smmu_rot_ahb_clk = {
1450 .enable_reg = 0x2444,
1451 .enable_mask = BIT(0),
1452 .hw.init = &(struct clk_init_data){
1453 .name = "smmu_rot_ahb_clk",
1454 .parent_names = (const char *[]){ "ahb_clk_src" },
1456 .flags = CLK_SET_RATE_PARENT,
1457 .ops = &clk_branch2_ops,
1462 static struct clk_branch smmu_rot_axi_clk = {
1465 .enable_reg = 0x2448,
1466 .enable_mask = BIT(0),
1467 .hw.init = &(struct clk_init_data){
1468 .name = "smmu_rot_axi_clk",
1469 .parent_names = (const char *[]){ "axi_clk_src" },
1471 .flags = CLK_SET_RATE_PARENT,
1472 .ops = &clk_branch2_ops,
1477 static struct clk_branch smmu_mdp_ahb_clk = {
1480 .enable_reg = 0x2454,
1481 .enable_mask = BIT(0),
1482 .hw.init = &(struct clk_init_data){
1483 .name = "smmu_mdp_ahb_clk",
1484 .parent_names = (const char *[]){ "ahb_clk_src" },
1486 .flags = CLK_SET_RATE_PARENT,
1487 .ops = &clk_branch2_ops,
1492 static struct clk_branch smmu_mdp_axi_clk = {
1495 .enable_reg = 0x2458,
1496 .enable_mask = BIT(0),
1497 .hw.init = &(struct clk_init_data){
1498 .name = "smmu_mdp_axi_clk",
1499 .parent_names = (const char *[]){ "axi_clk_src" },
1501 .flags = CLK_SET_RATE_PARENT,
1502 .ops = &clk_branch2_ops,
1507 static struct clk_branch mmagic_video_axi_clk = {
1510 .enable_reg = 0x1194,
1511 .enable_mask = BIT(0),
1512 .hw.init = &(struct clk_init_data){
1513 .name = "mmagic_video_axi_clk",
1514 .parent_names = (const char *[]){ "axi_clk_src" },
1516 .flags = CLK_SET_RATE_PARENT,
1517 .ops = &clk_branch2_ops,
1522 static struct clk_branch mmagic_video_noc_cfg_ahb_clk = {
1525 .enable_reg = 0x1198,
1526 .enable_mask = BIT(0),
1527 .hw.init = &(struct clk_init_data){
1528 .name = "mmagic_video_noc_cfg_ahb_clk",
1529 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1531 .flags = CLK_SET_RATE_PARENT,
1532 .ops = &clk_branch2_ops,
1537 static struct clk_branch smmu_video_ahb_clk = {
1540 .enable_reg = 0x1174,
1541 .enable_mask = BIT(0),
1542 .hw.init = &(struct clk_init_data){
1543 .name = "smmu_video_ahb_clk",
1544 .parent_names = (const char *[]){ "ahb_clk_src" },
1546 .flags = CLK_SET_RATE_PARENT,
1547 .ops = &clk_branch2_ops,
1552 static struct clk_branch smmu_video_axi_clk = {
1555 .enable_reg = 0x1178,
1556 .enable_mask = BIT(0),
1557 .hw.init = &(struct clk_init_data){
1558 .name = "smmu_video_axi_clk",
1559 .parent_names = (const char *[]){ "axi_clk_src" },
1561 .flags = CLK_SET_RATE_PARENT,
1562 .ops = &clk_branch2_ops,
1567 static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = {
1570 .enable_reg = 0x5298,
1571 .enable_mask = BIT(0),
1572 .hw.init = &(struct clk_init_data){
1573 .name = "mmagic_bimc_noc_cfg_ahb_clk",
1574 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1576 .flags = CLK_SET_RATE_PARENT,
1577 .ops = &clk_branch2_ops,
1582 static struct clk_branch gpu_gx_gfx3d_clk = {
1585 .enable_reg = 0x4028,
1586 .enable_mask = BIT(0),
1587 .hw.init = &(struct clk_init_data){
1588 .name = "gpu_gx_gfx3d_clk",
1589 .parent_names = (const char *[]){ "gfx3d_clk_src" },
1591 .flags = CLK_SET_RATE_PARENT,
1592 .ops = &clk_branch2_ops,
1597 static struct clk_branch gpu_gx_rbbmtimer_clk = {
1600 .enable_reg = 0x40b0,
1601 .enable_mask = BIT(0),
1602 .hw.init = &(struct clk_init_data){
1603 .name = "gpu_gx_rbbmtimer_clk",
1604 .parent_names = (const char *[]){ "rbbmtimer_clk_src" },
1606 .flags = CLK_SET_RATE_PARENT,
1607 .ops = &clk_branch2_ops,
1612 static struct clk_branch gpu_ahb_clk = {
1615 .enable_reg = 0x403c,
1616 .enable_mask = BIT(0),
1617 .hw.init = &(struct clk_init_data){
1618 .name = "gpu_ahb_clk",
1619 .parent_names = (const char *[]){ "ahb_clk_src" },
1621 .flags = CLK_SET_RATE_PARENT,
1622 .ops = &clk_branch2_ops,
1627 static struct clk_branch gpu_aon_isense_clk = {
1630 .enable_reg = 0x4044,
1631 .enable_mask = BIT(0),
1632 .hw.init = &(struct clk_init_data){
1633 .name = "gpu_aon_isense_clk",
1634 .parent_names = (const char *[]){ "isense_clk_src" },
1636 .flags = CLK_SET_RATE_PARENT,
1637 .ops = &clk_branch2_ops,
1642 static struct clk_branch vmem_maxi_clk = {
1645 .enable_reg = 0x1204,
1646 .enable_mask = BIT(0),
1647 .hw.init = &(struct clk_init_data){
1648 .name = "vmem_maxi_clk",
1649 .parent_names = (const char *[]){ "maxi_clk_src" },
1651 .flags = CLK_SET_RATE_PARENT,
1652 .ops = &clk_branch2_ops,
1657 static struct clk_branch vmem_ahb_clk = {
1660 .enable_reg = 0x1208,
1661 .enable_mask = BIT(0),
1662 .hw.init = &(struct clk_init_data){
1663 .name = "vmem_ahb_clk",
1664 .parent_names = (const char *[]){ "ahb_clk_src" },
1666 .flags = CLK_SET_RATE_PARENT,
1667 .ops = &clk_branch2_ops,
1672 static struct clk_branch mmss_rbcpr_clk = {
1675 .enable_reg = 0x4084,
1676 .enable_mask = BIT(0),
1677 .hw.init = &(struct clk_init_data){
1678 .name = "mmss_rbcpr_clk",
1679 .parent_names = (const char *[]){ "rbcpr_clk_src" },
1681 .flags = CLK_SET_RATE_PARENT,
1682 .ops = &clk_branch2_ops,
1687 static struct clk_branch mmss_rbcpr_ahb_clk = {
1690 .enable_reg = 0x4088,
1691 .enable_mask = BIT(0),
1692 .hw.init = &(struct clk_init_data){
1693 .name = "mmss_rbcpr_ahb_clk",
1694 .parent_names = (const char *[]){ "ahb_clk_src" },
1696 .flags = CLK_SET_RATE_PARENT,
1697 .ops = &clk_branch2_ops,
1702 static struct clk_branch video_core_clk = {
1705 .enable_reg = 0x1028,
1706 .enable_mask = BIT(0),
1707 .hw.init = &(struct clk_init_data){
1708 .name = "video_core_clk",
1709 .parent_names = (const char *[]){ "video_core_clk_src" },
1711 .flags = CLK_SET_RATE_PARENT,
1712 .ops = &clk_branch2_ops,
1717 static struct clk_branch video_axi_clk = {
1720 .enable_reg = 0x1034,
1721 .enable_mask = BIT(0),
1722 .hw.init = &(struct clk_init_data){
1723 .name = "video_axi_clk",
1724 .parent_names = (const char *[]){ "axi_clk_src" },
1726 .flags = CLK_SET_RATE_PARENT,
1727 .ops = &clk_branch2_ops,
1732 static struct clk_branch video_maxi_clk = {
1735 .enable_reg = 0x1038,
1736 .enable_mask = BIT(0),
1737 .hw.init = &(struct clk_init_data){
1738 .name = "video_maxi_clk",
1739 .parent_names = (const char *[]){ "maxi_clk_src" },
1741 .flags = CLK_SET_RATE_PARENT,
1742 .ops = &clk_branch2_ops,
1747 static struct clk_branch video_ahb_clk = {
1750 .enable_reg = 0x1030,
1751 .enable_mask = BIT(0),
1752 .hw.init = &(struct clk_init_data){
1753 .name = "video_ahb_clk",
1754 .parent_names = (const char *[]){ "ahb_clk_src" },
1756 .flags = CLK_SET_RATE_PARENT,
1757 .ops = &clk_branch2_ops,
1762 static struct clk_branch video_subcore0_clk = {
1765 .enable_reg = 0x1048,
1766 .enable_mask = BIT(0),
1767 .hw.init = &(struct clk_init_data){
1768 .name = "video_subcore0_clk",
1769 .parent_names = (const char *[]){ "video_subcore0_clk_src" },
1771 .flags = CLK_SET_RATE_PARENT,
1772 .ops = &clk_branch2_ops,
1777 static struct clk_branch video_subcore1_clk = {
1780 .enable_reg = 0x104c,
1781 .enable_mask = BIT(0),
1782 .hw.init = &(struct clk_init_data){
1783 .name = "video_subcore1_clk",
1784 .parent_names = (const char *[]){ "video_subcore1_clk_src" },
1786 .flags = CLK_SET_RATE_PARENT,
1787 .ops = &clk_branch2_ops,
1792 static struct clk_branch mdss_ahb_clk = {
1795 .enable_reg = 0x2308,
1796 .enable_mask = BIT(0),
1797 .hw.init = &(struct clk_init_data){
1798 .name = "mdss_ahb_clk",
1799 .parent_names = (const char *[]){ "ahb_clk_src" },
1801 .flags = CLK_SET_RATE_PARENT,
1802 .ops = &clk_branch2_ops,
1807 static struct clk_branch mdss_hdmi_ahb_clk = {
1810 .enable_reg = 0x230c,
1811 .enable_mask = BIT(0),
1812 .hw.init = &(struct clk_init_data){
1813 .name = "mdss_hdmi_ahb_clk",
1814 .parent_names = (const char *[]){ "ahb_clk_src" },
1816 .flags = CLK_SET_RATE_PARENT,
1817 .ops = &clk_branch2_ops,
1822 static struct clk_branch mdss_axi_clk = {
1825 .enable_reg = 0x2310,
1826 .enable_mask = BIT(0),
1827 .hw.init = &(struct clk_init_data){
1828 .name = "mdss_axi_clk",
1829 .parent_names = (const char *[]){ "axi_clk_src" },
1831 .flags = CLK_SET_RATE_PARENT,
1832 .ops = &clk_branch2_ops,
1837 static struct clk_branch mdss_pclk0_clk = {
1840 .enable_reg = 0x2314,
1841 .enable_mask = BIT(0),
1842 .hw.init = &(struct clk_init_data){
1843 .name = "mdss_pclk0_clk",
1844 .parent_names = (const char *[]){ "pclk0_clk_src" },
1846 .flags = CLK_SET_RATE_PARENT,
1847 .ops = &clk_branch2_ops,
1852 static struct clk_branch mdss_pclk1_clk = {
1855 .enable_reg = 0x2318,
1856 .enable_mask = BIT(0),
1857 .hw.init = &(struct clk_init_data){
1858 .name = "mdss_pclk1_clk",
1859 .parent_names = (const char *[]){ "pclk1_clk_src" },
1861 .flags = CLK_SET_RATE_PARENT,
1862 .ops = &clk_branch2_ops,
1867 static struct clk_branch mdss_mdp_clk = {
1870 .enable_reg = 0x231c,
1871 .enable_mask = BIT(0),
1872 .hw.init = &(struct clk_init_data){
1873 .name = "mdss_mdp_clk",
1874 .parent_names = (const char *[]){ "mdp_clk_src" },
1876 .flags = CLK_SET_RATE_PARENT,
1877 .ops = &clk_branch2_ops,
1882 static struct clk_branch mdss_extpclk_clk = {
1885 .enable_reg = 0x2324,
1886 .enable_mask = BIT(0),
1887 .hw.init = &(struct clk_init_data){
1888 .name = "mdss_extpclk_clk",
1889 .parent_names = (const char *[]){ "extpclk_clk_src" },
1891 .flags = CLK_SET_RATE_PARENT,
1892 .ops = &clk_branch2_ops,
1897 static struct clk_branch mdss_vsync_clk = {
1900 .enable_reg = 0x2328,
1901 .enable_mask = BIT(0),
1902 .hw.init = &(struct clk_init_data){
1903 .name = "mdss_vsync_clk",
1904 .parent_names = (const char *[]){ "vsync_clk_src" },
1906 .flags = CLK_SET_RATE_PARENT,
1907 .ops = &clk_branch2_ops,
1912 static struct clk_branch mdss_hdmi_clk = {
1915 .enable_reg = 0x2338,
1916 .enable_mask = BIT(0),
1917 .hw.init = &(struct clk_init_data){
1918 .name = "mdss_hdmi_clk",
1919 .parent_names = (const char *[]){ "hdmi_clk_src" },
1921 .flags = CLK_SET_RATE_PARENT,
1922 .ops = &clk_branch2_ops,
1927 static struct clk_branch mdss_byte0_clk = {
1930 .enable_reg = 0x233c,
1931 .enable_mask = BIT(0),
1932 .hw.init = &(struct clk_init_data){
1933 .name = "mdss_byte0_clk",
1934 .parent_names = (const char *[]){ "byte0_clk_src" },
1936 .flags = CLK_SET_RATE_PARENT,
1937 .ops = &clk_branch2_ops,
1942 static struct clk_branch mdss_byte1_clk = {
1945 .enable_reg = 0x2340,
1946 .enable_mask = BIT(0),
1947 .hw.init = &(struct clk_init_data){
1948 .name = "mdss_byte1_clk",
1949 .parent_names = (const char *[]){ "byte1_clk_src" },
1951 .flags = CLK_SET_RATE_PARENT,
1952 .ops = &clk_branch2_ops,
1957 static struct clk_branch mdss_esc0_clk = {
1960 .enable_reg = 0x2344,
1961 .enable_mask = BIT(0),
1962 .hw.init = &(struct clk_init_data){
1963 .name = "mdss_esc0_clk",
1964 .parent_names = (const char *[]){ "esc0_clk_src" },
1966 .flags = CLK_SET_RATE_PARENT,
1967 .ops = &clk_branch2_ops,
1972 static struct clk_branch mdss_esc1_clk = {
1975 .enable_reg = 0x2348,
1976 .enable_mask = BIT(0),
1977 .hw.init = &(struct clk_init_data){
1978 .name = "mdss_esc1_clk",
1979 .parent_names = (const char *[]){ "esc1_clk_src" },
1981 .flags = CLK_SET_RATE_PARENT,
1982 .ops = &clk_branch2_ops,
1987 static struct clk_branch camss_top_ahb_clk = {
1990 .enable_reg = 0x3484,
1991 .enable_mask = BIT(0),
1992 .hw.init = &(struct clk_init_data){
1993 .name = "camss_top_ahb_clk",
1994 .parent_names = (const char *[]){ "ahb_clk_src" },
1996 .flags = CLK_SET_RATE_PARENT,
1997 .ops = &clk_branch2_ops,
2002 static struct clk_branch camss_ahb_clk = {
2005 .enable_reg = 0x348c,
2006 .enable_mask = BIT(0),
2007 .hw.init = &(struct clk_init_data){
2008 .name = "camss_ahb_clk",
2009 .parent_names = (const char *[]){ "ahb_clk_src" },
2011 .flags = CLK_SET_RATE_PARENT,
2012 .ops = &clk_branch2_ops,
2017 static struct clk_branch camss_micro_ahb_clk = {
2020 .enable_reg = 0x3494,
2021 .enable_mask = BIT(0),
2022 .hw.init = &(struct clk_init_data){
2023 .name = "camss_micro_ahb_clk",
2024 .parent_names = (const char *[]){ "ahb_clk_src" },
2026 .flags = CLK_SET_RATE_PARENT,
2027 .ops = &clk_branch2_ops,
2032 static struct clk_branch camss_gp0_clk = {
2035 .enable_reg = 0x3444,
2036 .enable_mask = BIT(0),
2037 .hw.init = &(struct clk_init_data){
2038 .name = "camss_gp0_clk",
2039 .parent_names = (const char *[]){ "camss_gp0_clk_src" },
2041 .flags = CLK_SET_RATE_PARENT,
2042 .ops = &clk_branch2_ops,
2047 static struct clk_branch camss_gp1_clk = {
2050 .enable_reg = 0x3474,
2051 .enable_mask = BIT(0),
2052 .hw.init = &(struct clk_init_data){
2053 .name = "camss_gp1_clk",
2054 .parent_names = (const char *[]){ "camss_gp1_clk_src" },
2056 .flags = CLK_SET_RATE_PARENT,
2057 .ops = &clk_branch2_ops,
2062 static struct clk_branch camss_mclk0_clk = {
2065 .enable_reg = 0x3384,
2066 .enable_mask = BIT(0),
2067 .hw.init = &(struct clk_init_data){
2068 .name = "camss_mclk0_clk",
2069 .parent_names = (const char *[]){ "mclk0_clk_src" },
2071 .flags = CLK_SET_RATE_PARENT,
2072 .ops = &clk_branch2_ops,
2077 static struct clk_branch camss_mclk1_clk = {
2080 .enable_reg = 0x33b4,
2081 .enable_mask = BIT(0),
2082 .hw.init = &(struct clk_init_data){
2083 .name = "camss_mclk1_clk",
2084 .parent_names = (const char *[]){ "mclk1_clk_src" },
2086 .flags = CLK_SET_RATE_PARENT,
2087 .ops = &clk_branch2_ops,
2092 static struct clk_branch camss_mclk2_clk = {
2095 .enable_reg = 0x33e4,
2096 .enable_mask = BIT(0),
2097 .hw.init = &(struct clk_init_data){
2098 .name = "camss_mclk2_clk",
2099 .parent_names = (const char *[]){ "mclk2_clk_src" },
2101 .flags = CLK_SET_RATE_PARENT,
2102 .ops = &clk_branch2_ops,
2107 static struct clk_branch camss_mclk3_clk = {
2110 .enable_reg = 0x3414,
2111 .enable_mask = BIT(0),
2112 .hw.init = &(struct clk_init_data){
2113 .name = "camss_mclk3_clk",
2114 .parent_names = (const char *[]){ "mclk3_clk_src" },
2116 .flags = CLK_SET_RATE_PARENT,
2117 .ops = &clk_branch2_ops,
2122 static struct clk_branch camss_cci_clk = {
2125 .enable_reg = 0x3344,
2126 .enable_mask = BIT(0),
2127 .hw.init = &(struct clk_init_data){
2128 .name = "camss_cci_clk",
2129 .parent_names = (const char *[]){ "cci_clk_src" },
2131 .flags = CLK_SET_RATE_PARENT,
2132 .ops = &clk_branch2_ops,
2137 static struct clk_branch camss_cci_ahb_clk = {
2140 .enable_reg = 0x3348,
2141 .enable_mask = BIT(0),
2142 .hw.init = &(struct clk_init_data){
2143 .name = "camss_cci_ahb_clk",
2144 .parent_names = (const char *[]){ "ahb_clk_src" },
2146 .flags = CLK_SET_RATE_PARENT,
2147 .ops = &clk_branch2_ops,
2152 static struct clk_branch camss_csi0phytimer_clk = {
2155 .enable_reg = 0x3024,
2156 .enable_mask = BIT(0),
2157 .hw.init = &(struct clk_init_data){
2158 .name = "camss_csi0phytimer_clk",
2159 .parent_names = (const char *[]){ "csi0phytimer_clk_src" },
2161 .flags = CLK_SET_RATE_PARENT,
2162 .ops = &clk_branch2_ops,
2167 static struct clk_branch camss_csi1phytimer_clk = {
2170 .enable_reg = 0x3054,
2171 .enable_mask = BIT(0),
2172 .hw.init = &(struct clk_init_data){
2173 .name = "camss_csi1phytimer_clk",
2174 .parent_names = (const char *[]){ "csi1phytimer_clk_src" },
2176 .flags = CLK_SET_RATE_PARENT,
2177 .ops = &clk_branch2_ops,
2182 static struct clk_branch camss_csi2phytimer_clk = {
2185 .enable_reg = 0x3084,
2186 .enable_mask = BIT(0),
2187 .hw.init = &(struct clk_init_data){
2188 .name = "camss_csi2phytimer_clk",
2189 .parent_names = (const char *[]){ "csi2phytimer_clk_src" },
2191 .flags = CLK_SET_RATE_PARENT,
2192 .ops = &clk_branch2_ops,
2197 static struct clk_branch camss_csiphy0_3p_clk = {
2200 .enable_reg = 0x3234,
2201 .enable_mask = BIT(0),
2202 .hw.init = &(struct clk_init_data){
2203 .name = "camss_csiphy0_3p_clk",
2204 .parent_names = (const char *[]){ "csiphy0_3p_clk_src" },
2206 .flags = CLK_SET_RATE_PARENT,
2207 .ops = &clk_branch2_ops,
2212 static struct clk_branch camss_csiphy1_3p_clk = {
2215 .enable_reg = 0x3254,
2216 .enable_mask = BIT(0),
2217 .hw.init = &(struct clk_init_data){
2218 .name = "camss_csiphy1_3p_clk",
2219 .parent_names = (const char *[]){ "csiphy1_3p_clk_src" },
2221 .flags = CLK_SET_RATE_PARENT,
2222 .ops = &clk_branch2_ops,
2227 static struct clk_branch camss_csiphy2_3p_clk = {
2230 .enable_reg = 0x3274,
2231 .enable_mask = BIT(0),
2232 .hw.init = &(struct clk_init_data){
2233 .name = "camss_csiphy2_3p_clk",
2234 .parent_names = (const char *[]){ "csiphy2_3p_clk_src" },
2236 .flags = CLK_SET_RATE_PARENT,
2237 .ops = &clk_branch2_ops,
2242 static struct clk_branch camss_jpeg0_clk = {
2245 .enable_reg = 0x35a8,
2246 .enable_mask = BIT(0),
2247 .hw.init = &(struct clk_init_data){
2248 .name = "camss_jpeg0_clk",
2249 .parent_names = (const char *[]){ "jpeg0_clk_src" },
2251 .flags = CLK_SET_RATE_PARENT,
2252 .ops = &clk_branch2_ops,
2257 static struct clk_branch camss_jpeg2_clk = {
2260 .enable_reg = 0x35b0,
2261 .enable_mask = BIT(0),
2262 .hw.init = &(struct clk_init_data){
2263 .name = "camss_jpeg2_clk",
2264 .parent_names = (const char *[]){ "jpeg2_clk_src" },
2266 .flags = CLK_SET_RATE_PARENT,
2267 .ops = &clk_branch2_ops,
2272 static struct clk_branch camss_jpeg_dma_clk = {
2275 .enable_reg = 0x35c0,
2276 .enable_mask = BIT(0),
2277 .hw.init = &(struct clk_init_data){
2278 .name = "camss_jpeg_dma_clk",
2279 .parent_names = (const char *[]){ "jpeg_dma_clk_src" },
2281 .flags = CLK_SET_RATE_PARENT,
2282 .ops = &clk_branch2_ops,
2287 static struct clk_branch camss_jpeg_ahb_clk = {
2290 .enable_reg = 0x35b4,
2291 .enable_mask = BIT(0),
2292 .hw.init = &(struct clk_init_data){
2293 .name = "camss_jpeg_ahb_clk",
2294 .parent_names = (const char *[]){ "ahb_clk_src" },
2296 .flags = CLK_SET_RATE_PARENT,
2297 .ops = &clk_branch2_ops,
2302 static struct clk_branch camss_jpeg_axi_clk = {
2305 .enable_reg = 0x35b8,
2306 .enable_mask = BIT(0),
2307 .hw.init = &(struct clk_init_data){
2308 .name = "camss_jpeg_axi_clk",
2309 .parent_names = (const char *[]){ "axi_clk_src" },
2311 .flags = CLK_SET_RATE_PARENT,
2312 .ops = &clk_branch2_ops,
2317 static struct clk_branch camss_vfe_ahb_clk = {
2320 .enable_reg = 0x36b8,
2321 .enable_mask = BIT(0),
2322 .hw.init = &(struct clk_init_data){
2323 .name = "camss_vfe_ahb_clk",
2324 .parent_names = (const char *[]){ "ahb_clk_src" },
2326 .flags = CLK_SET_RATE_PARENT,
2327 .ops = &clk_branch2_ops,
2332 static struct clk_branch camss_vfe_axi_clk = {
2335 .enable_reg = 0x36bc,
2336 .enable_mask = BIT(0),
2337 .hw.init = &(struct clk_init_data){
2338 .name = "camss_vfe_axi_clk",
2339 .parent_names = (const char *[]){ "axi_clk_src" },
2341 .flags = CLK_SET_RATE_PARENT,
2342 .ops = &clk_branch2_ops,
2347 static struct clk_branch camss_vfe0_clk = {
2350 .enable_reg = 0x36a8,
2351 .enable_mask = BIT(0),
2352 .hw.init = &(struct clk_init_data){
2353 .name = "camss_vfe0_clk",
2354 .parent_names = (const char *[]){ "vfe0_clk_src" },
2356 .flags = CLK_SET_RATE_PARENT,
2357 .ops = &clk_branch2_ops,
2362 static struct clk_branch camss_vfe0_stream_clk = {
2365 .enable_reg = 0x3720,
2366 .enable_mask = BIT(0),
2367 .hw.init = &(struct clk_init_data){
2368 .name = "camss_vfe0_stream_clk",
2369 .parent_names = (const char *[]){ "vfe0_clk_src" },
2371 .flags = CLK_SET_RATE_PARENT,
2372 .ops = &clk_branch2_ops,
2377 static struct clk_branch camss_vfe0_ahb_clk = {
2380 .enable_reg = 0x3668,
2381 .enable_mask = BIT(0),
2382 .hw.init = &(struct clk_init_data){
2383 .name = "camss_vfe0_ahb_clk",
2384 .parent_names = (const char *[]){ "ahb_clk_src" },
2386 .flags = CLK_SET_RATE_PARENT,
2387 .ops = &clk_branch2_ops,
2392 static struct clk_branch camss_vfe1_clk = {
2395 .enable_reg = 0x36ac,
2396 .enable_mask = BIT(0),
2397 .hw.init = &(struct clk_init_data){
2398 .name = "camss_vfe1_clk",
2399 .parent_names = (const char *[]){ "vfe1_clk_src" },
2401 .flags = CLK_SET_RATE_PARENT,
2402 .ops = &clk_branch2_ops,
2407 static struct clk_branch camss_vfe1_stream_clk = {
2410 .enable_reg = 0x3724,
2411 .enable_mask = BIT(0),
2412 .hw.init = &(struct clk_init_data){
2413 .name = "camss_vfe1_stream_clk",
2414 .parent_names = (const char *[]){ "vfe1_clk_src" },
2416 .flags = CLK_SET_RATE_PARENT,
2417 .ops = &clk_branch2_ops,
2422 static struct clk_branch camss_vfe1_ahb_clk = {
2425 .enable_reg = 0x3678,
2426 .enable_mask = BIT(0),
2427 .hw.init = &(struct clk_init_data){
2428 .name = "camss_vfe1_ahb_clk",
2429 .parent_names = (const char *[]){ "ahb_clk_src" },
2431 .flags = CLK_SET_RATE_PARENT,
2432 .ops = &clk_branch2_ops,
2437 static struct clk_branch camss_csi_vfe0_clk = {
2440 .enable_reg = 0x3704,
2441 .enable_mask = BIT(0),
2442 .hw.init = &(struct clk_init_data){
2443 .name = "camss_csi_vfe0_clk",
2444 .parent_names = (const char *[]){ "vfe0_clk_src" },
2446 .flags = CLK_SET_RATE_PARENT,
2447 .ops = &clk_branch2_ops,
2452 static struct clk_branch camss_csi_vfe1_clk = {
2455 .enable_reg = 0x3714,
2456 .enable_mask = BIT(0),
2457 .hw.init = &(struct clk_init_data){
2458 .name = "camss_csi_vfe1_clk",
2459 .parent_names = (const char *[]){ "vfe1_clk_src" },
2461 .flags = CLK_SET_RATE_PARENT,
2462 .ops = &clk_branch2_ops,
2467 static struct clk_branch camss_cpp_vbif_ahb_clk = {
2470 .enable_reg = 0x36c8,
2471 .enable_mask = BIT(0),
2472 .hw.init = &(struct clk_init_data){
2473 .name = "camss_cpp_vbif_ahb_clk",
2474 .parent_names = (const char *[]){ "ahb_clk_src" },
2476 .flags = CLK_SET_RATE_PARENT,
2477 .ops = &clk_branch2_ops,
2482 static struct clk_branch camss_cpp_axi_clk = {
2485 .enable_reg = 0x36c4,
2486 .enable_mask = BIT(0),
2487 .hw.init = &(struct clk_init_data){
2488 .name = "camss_cpp_axi_clk",
2489 .parent_names = (const char *[]){ "axi_clk_src" },
2491 .flags = CLK_SET_RATE_PARENT,
2492 .ops = &clk_branch2_ops,
2497 static struct clk_branch camss_cpp_clk = {
2500 .enable_reg = 0x36b0,
2501 .enable_mask = BIT(0),
2502 .hw.init = &(struct clk_init_data){
2503 .name = "camss_cpp_clk",
2504 .parent_names = (const char *[]){ "cpp_clk_src" },
2506 .flags = CLK_SET_RATE_PARENT,
2507 .ops = &clk_branch2_ops,
2512 static struct clk_branch camss_cpp_ahb_clk = {
2515 .enable_reg = 0x36b4,
2516 .enable_mask = BIT(0),
2517 .hw.init = &(struct clk_init_data){
2518 .name = "camss_cpp_ahb_clk",
2519 .parent_names = (const char *[]){ "ahb_clk_src" },
2521 .flags = CLK_SET_RATE_PARENT,
2522 .ops = &clk_branch2_ops,
2527 static struct clk_branch camss_csi0_clk = {
2530 .enable_reg = 0x30b4,
2531 .enable_mask = BIT(0),
2532 .hw.init = &(struct clk_init_data){
2533 .name = "camss_csi0_clk",
2534 .parent_names = (const char *[]){ "csi0_clk_src" },
2536 .flags = CLK_SET_RATE_PARENT,
2537 .ops = &clk_branch2_ops,
2542 static struct clk_branch camss_csi0_ahb_clk = {
2545 .enable_reg = 0x30bc,
2546 .enable_mask = BIT(0),
2547 .hw.init = &(struct clk_init_data){
2548 .name = "camss_csi0_ahb_clk",
2549 .parent_names = (const char *[]){ "ahb_clk_src" },
2551 .flags = CLK_SET_RATE_PARENT,
2552 .ops = &clk_branch2_ops,
2557 static struct clk_branch camss_csi0phy_clk = {
2560 .enable_reg = 0x30c4,
2561 .enable_mask = BIT(0),
2562 .hw.init = &(struct clk_init_data){
2563 .name = "camss_csi0phy_clk",
2564 .parent_names = (const char *[]){ "csi0_clk_src" },
2566 .flags = CLK_SET_RATE_PARENT,
2567 .ops = &clk_branch2_ops,
2572 static struct clk_branch camss_csi0rdi_clk = {
2575 .enable_reg = 0x30d4,
2576 .enable_mask = BIT(0),
2577 .hw.init = &(struct clk_init_data){
2578 .name = "camss_csi0rdi_clk",
2579 .parent_names = (const char *[]){ "csi0_clk_src" },
2581 .flags = CLK_SET_RATE_PARENT,
2582 .ops = &clk_branch2_ops,
2587 static struct clk_branch camss_csi0pix_clk = {
2590 .enable_reg = 0x30e4,
2591 .enable_mask = BIT(0),
2592 .hw.init = &(struct clk_init_data){
2593 .name = "camss_csi0pix_clk",
2594 .parent_names = (const char *[]){ "csi0_clk_src" },
2596 .flags = CLK_SET_RATE_PARENT,
2597 .ops = &clk_branch2_ops,
2602 static struct clk_branch camss_csi1_clk = {
2605 .enable_reg = 0x3124,
2606 .enable_mask = BIT(0),
2607 .hw.init = &(struct clk_init_data){
2608 .name = "camss_csi1_clk",
2609 .parent_names = (const char *[]){ "csi1_clk_src" },
2611 .flags = CLK_SET_RATE_PARENT,
2612 .ops = &clk_branch2_ops,
2617 static struct clk_branch camss_csi1_ahb_clk = {
2620 .enable_reg = 0x3128,
2621 .enable_mask = BIT(0),
2622 .hw.init = &(struct clk_init_data){
2623 .name = "camss_csi1_ahb_clk",
2624 .parent_names = (const char *[]){ "ahb_clk_src" },
2626 .flags = CLK_SET_RATE_PARENT,
2627 .ops = &clk_branch2_ops,
2632 static struct clk_branch camss_csi1phy_clk = {
2635 .enable_reg = 0x3134,
2636 .enable_mask = BIT(0),
2637 .hw.init = &(struct clk_init_data){
2638 .name = "camss_csi1phy_clk",
2639 .parent_names = (const char *[]){ "csi1_clk_src" },
2641 .flags = CLK_SET_RATE_PARENT,
2642 .ops = &clk_branch2_ops,
2647 static struct clk_branch camss_csi1rdi_clk = {
2650 .enable_reg = 0x3144,
2651 .enable_mask = BIT(0),
2652 .hw.init = &(struct clk_init_data){
2653 .name = "camss_csi1rdi_clk",
2654 .parent_names = (const char *[]){ "csi1_clk_src" },
2656 .flags = CLK_SET_RATE_PARENT,
2657 .ops = &clk_branch2_ops,
2662 static struct clk_branch camss_csi1pix_clk = {
2665 .enable_reg = 0x3154,
2666 .enable_mask = BIT(0),
2667 .hw.init = &(struct clk_init_data){
2668 .name = "camss_csi1pix_clk",
2669 .parent_names = (const char *[]){ "csi1_clk_src" },
2671 .flags = CLK_SET_RATE_PARENT,
2672 .ops = &clk_branch2_ops,
2677 static struct clk_branch camss_csi2_clk = {
2680 .enable_reg = 0x3184,
2681 .enable_mask = BIT(0),
2682 .hw.init = &(struct clk_init_data){
2683 .name = "camss_csi2_clk",
2684 .parent_names = (const char *[]){ "csi2_clk_src" },
2686 .flags = CLK_SET_RATE_PARENT,
2687 .ops = &clk_branch2_ops,
2692 static struct clk_branch camss_csi2_ahb_clk = {
2695 .enable_reg = 0x3188,
2696 .enable_mask = BIT(0),
2697 .hw.init = &(struct clk_init_data){
2698 .name = "camss_csi2_ahb_clk",
2699 .parent_names = (const char *[]){ "ahb_clk_src" },
2701 .flags = CLK_SET_RATE_PARENT,
2702 .ops = &clk_branch2_ops,
2707 static struct clk_branch camss_csi2phy_clk = {
2710 .enable_reg = 0x3194,
2711 .enable_mask = BIT(0),
2712 .hw.init = &(struct clk_init_data){
2713 .name = "camss_csi2phy_clk",
2714 .parent_names = (const char *[]){ "csi2_clk_src" },
2716 .flags = CLK_SET_RATE_PARENT,
2717 .ops = &clk_branch2_ops,
2722 static struct clk_branch camss_csi2rdi_clk = {
2725 .enable_reg = 0x31a4,
2726 .enable_mask = BIT(0),
2727 .hw.init = &(struct clk_init_data){
2728 .name = "camss_csi2rdi_clk",
2729 .parent_names = (const char *[]){ "csi2_clk_src" },
2731 .flags = CLK_SET_RATE_PARENT,
2732 .ops = &clk_branch2_ops,
2737 static struct clk_branch camss_csi2pix_clk = {
2740 .enable_reg = 0x31b4,
2741 .enable_mask = BIT(0),
2742 .hw.init = &(struct clk_init_data){
2743 .name = "camss_csi2pix_clk",
2744 .parent_names = (const char *[]){ "csi2_clk_src" },
2746 .flags = CLK_SET_RATE_PARENT,
2747 .ops = &clk_branch2_ops,
2752 static struct clk_branch camss_csi3_clk = {
2755 .enable_reg = 0x31e4,
2756 .enable_mask = BIT(0),
2757 .hw.init = &(struct clk_init_data){
2758 .name = "camss_csi3_clk",
2759 .parent_names = (const char *[]){ "csi3_clk_src" },
2761 .flags = CLK_SET_RATE_PARENT,
2762 .ops = &clk_branch2_ops,
2767 static struct clk_branch camss_csi3_ahb_clk = {
2770 .enable_reg = 0x31e8,
2771 .enable_mask = BIT(0),
2772 .hw.init = &(struct clk_init_data){
2773 .name = "camss_csi3_ahb_clk",
2774 .parent_names = (const char *[]){ "ahb_clk_src" },
2776 .flags = CLK_SET_RATE_PARENT,
2777 .ops = &clk_branch2_ops,
2782 static struct clk_branch camss_csi3phy_clk = {
2785 .enable_reg = 0x31f4,
2786 .enable_mask = BIT(0),
2787 .hw.init = &(struct clk_init_data){
2788 .name = "camss_csi3phy_clk",
2789 .parent_names = (const char *[]){ "csi3_clk_src" },
2791 .flags = CLK_SET_RATE_PARENT,
2792 .ops = &clk_branch2_ops,
2797 static struct clk_branch camss_csi3rdi_clk = {
2800 .enable_reg = 0x3204,
2801 .enable_mask = BIT(0),
2802 .hw.init = &(struct clk_init_data){
2803 .name = "camss_csi3rdi_clk",
2804 .parent_names = (const char *[]){ "csi3_clk_src" },
2806 .flags = CLK_SET_RATE_PARENT,
2807 .ops = &clk_branch2_ops,
2812 static struct clk_branch camss_csi3pix_clk = {
2815 .enable_reg = 0x3214,
2816 .enable_mask = BIT(0),
2817 .hw.init = &(struct clk_init_data){
2818 .name = "camss_csi3pix_clk",
2819 .parent_names = (const char *[]){ "csi3_clk_src" },
2821 .flags = CLK_SET_RATE_PARENT,
2822 .ops = &clk_branch2_ops,
2827 static struct clk_branch camss_ispif_ahb_clk = {
2830 .enable_reg = 0x3224,
2831 .enable_mask = BIT(0),
2832 .hw.init = &(struct clk_init_data){
2833 .name = "camss_ispif_ahb_clk",
2834 .parent_names = (const char *[]){ "ahb_clk_src" },
2836 .flags = CLK_SET_RATE_PARENT,
2837 .ops = &clk_branch2_ops,
2842 static struct clk_branch fd_core_clk = {
2845 .enable_reg = 0x3b68,
2846 .enable_mask = BIT(0),
2847 .hw.init = &(struct clk_init_data){
2848 .name = "fd_core_clk",
2849 .parent_names = (const char *[]){ "fd_core_clk_src" },
2851 .flags = CLK_SET_RATE_PARENT,
2852 .ops = &clk_branch2_ops,
2857 static struct clk_branch fd_core_uar_clk = {
2860 .enable_reg = 0x3b6c,
2861 .enable_mask = BIT(0),
2862 .hw.init = &(struct clk_init_data){
2863 .name = "fd_core_uar_clk",
2864 .parent_names = (const char *[]){ "fd_core_clk_src" },
2866 .flags = CLK_SET_RATE_PARENT,
2867 .ops = &clk_branch2_ops,
2872 static struct clk_branch fd_ahb_clk = {
2873 .halt_reg = 0x3ba74,
2875 .enable_reg = 0x3ba74,
2876 .enable_mask = BIT(0),
2877 .hw.init = &(struct clk_init_data){
2878 .name = "fd_ahb_clk",
2879 .parent_names = (const char *[]){ "ahb_clk_src" },
2881 .flags = CLK_SET_RATE_PARENT,
2882 .ops = &clk_branch2_ops,
2887 static struct clk_hw *mmcc_msm8996_hws[] = {
2891 static struct gdsc mmagic_bimc_gdsc = {
2894 .name = "mmagic_bimc",
2896 .pwrsts = PWRSTS_OFF_ON,
2899 static struct gdsc mmagic_video_gdsc = {
2901 .gds_hw_ctrl = 0x120c,
2903 .name = "mmagic_video",
2905 .pwrsts = PWRSTS_OFF_ON,
2909 static struct gdsc mmagic_mdss_gdsc = {
2911 .gds_hw_ctrl = 0x2480,
2913 .name = "mmagic_mdss",
2915 .pwrsts = PWRSTS_OFF_ON,
2919 static struct gdsc mmagic_camss_gdsc = {
2921 .gds_hw_ctrl = 0x3c50,
2923 .name = "mmagic_camss",
2925 .pwrsts = PWRSTS_OFF_ON,
2929 static struct gdsc venus_gdsc = {
2931 .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
2936 .parent = &mmagic_video_gdsc.pd,
2937 .pwrsts = PWRSTS_OFF_ON,
2940 static struct gdsc venus_core0_gdsc = {
2942 .cxcs = (unsigned int []){ 0x1048 },
2945 .name = "venus_core0",
2947 .pwrsts = PWRSTS_OFF_ON,
2950 static struct gdsc venus_core1_gdsc = {
2952 .cxcs = (unsigned int []){ 0x104c },
2955 .name = "venus_core1",
2957 .pwrsts = PWRSTS_OFF_ON,
2960 static struct gdsc camss_gdsc = {
2962 .cxcs = (unsigned int []){ 0x36bc, 0x36c4 },
2967 .parent = &mmagic_camss_gdsc.pd,
2968 .pwrsts = PWRSTS_OFF_ON,
2971 static struct gdsc vfe0_gdsc = {
2973 .cxcs = (unsigned int []){ 0x36a8 },
2978 .parent = &camss_gdsc.pd,
2979 .pwrsts = PWRSTS_OFF_ON,
2982 static struct gdsc vfe1_gdsc = {
2984 .cxcs = (unsigned int []){ 0x36ac },
2989 .parent = &camss_gdsc.pd,
2990 .pwrsts = PWRSTS_OFF_ON,
2993 static struct gdsc jpeg_gdsc = {
2995 .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 },
3000 .parent = &camss_gdsc.pd,
3001 .pwrsts = PWRSTS_OFF_ON,
3004 static struct gdsc cpp_gdsc = {
3006 .cxcs = (unsigned int []){ 0x36b0 },
3011 .parent = &camss_gdsc.pd,
3012 .pwrsts = PWRSTS_OFF_ON,
3015 static struct gdsc fd_gdsc = {
3017 .cxcs = (unsigned int []){ 0x3b68, 0x3b6c },
3022 .parent = &camss_gdsc.pd,
3023 .pwrsts = PWRSTS_OFF_ON,
3026 static struct gdsc mdss_gdsc = {
3028 .cxcs = (unsigned int []){ 0x2310, 0x231c },
3033 .parent = &mmagic_mdss_gdsc.pd,
3034 .pwrsts = PWRSTS_OFF_ON,
3037 static struct clk_regmap *mmcc_msm8996_clocks[] = {
3038 [MMPLL0_EARLY] = &mmpll0_early.clkr,
3039 [MMPLL0_PLL] = &mmpll0.clkr,
3040 [MMPLL1_EARLY] = &mmpll1_early.clkr,
3041 [MMPLL1_PLL] = &mmpll1.clkr,
3042 [MMPLL2_EARLY] = &mmpll2_early.clkr,
3043 [MMPLL2_PLL] = &mmpll2.clkr,
3044 [MMPLL3_EARLY] = &mmpll3_early.clkr,
3045 [MMPLL3_PLL] = &mmpll3.clkr,
3046 [MMPLL4_EARLY] = &mmpll4_early.clkr,
3047 [MMPLL4_PLL] = &mmpll4.clkr,
3048 [MMPLL5_EARLY] = &mmpll5_early.clkr,
3049 [MMPLL5_PLL] = &mmpll5.clkr,
3050 [MMPLL8_EARLY] = &mmpll8_early.clkr,
3051 [MMPLL8_PLL] = &mmpll8.clkr,
3052 [MMPLL9_EARLY] = &mmpll9_early.clkr,
3053 [MMPLL9_PLL] = &mmpll9.clkr,
3054 [AHB_CLK_SRC] = &ahb_clk_src.clkr,
3055 [AXI_CLK_SRC] = &axi_clk_src.clkr,
3056 [MAXI_CLK_SRC] = &maxi_clk_src.clkr,
3057 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3058 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
3059 [ISENSE_CLK_SRC] = &isense_clk_src.clkr,
3060 [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
3061 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
3062 [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
3063 [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
3064 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3065 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3066 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3067 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
3068 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3069 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
3070 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3071 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3072 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3073 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3074 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3075 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3076 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3077 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3078 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3079 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
3080 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3081 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3082 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3083 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
3084 [CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr,
3085 [CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr,
3086 [CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr,
3087 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3088 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
3089 [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr,
3090 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3091 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3092 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3093 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3094 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3095 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3096 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
3097 [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
3098 [MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr,
3099 [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr,
3100 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
3101 [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr,
3102 [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr,
3103 [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr,
3104 [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr,
3105 [SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr,
3106 [SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr,
3107 [SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr,
3108 [SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr,
3109 [SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr,
3110 [SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr,
3111 [MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr,
3112 [MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr,
3113 [SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr,
3114 [SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr,
3115 [SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr,
3116 [SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr,
3117 [MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr,
3118 [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr,
3119 [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr,
3120 [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr,
3121 [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr,
3122 [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr,
3123 [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr,
3124 [GPU_AHB_CLK] = &gpu_ahb_clk.clkr,
3125 [GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr,
3126 [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
3127 [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
3128 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3129 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3130 [VIDEO_CORE_CLK] = &video_core_clk.clkr,
3131 [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
3132 [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
3133 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
3134 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
3135 [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
3136 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3137 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3138 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3139 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3140 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3141 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3142 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3143 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3144 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3145 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3146 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3147 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3148 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3149 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3150 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3151 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3152 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3153 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3154 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3155 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3156 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3157 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3158 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
3159 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
3160 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
3161 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
3162 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
3163 [CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr,
3164 [CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr,
3165 [CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr,
3166 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
3167 [CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr,
3168 [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr,
3169 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
3170 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
3171 [CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr,
3172 [CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr,
3173 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
3174 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
3175 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
3176 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
3177 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
3178 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
3179 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3180 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3181 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
3182 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
3183 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
3184 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
3185 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3186 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3187 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3188 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3189 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3190 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3191 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3192 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3193 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3194 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3195 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3196 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3197 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3198 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3199 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3200 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3201 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3202 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3203 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3204 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3205 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3206 [FD_CORE_CLK] = &fd_core_clk.clkr,
3207 [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
3208 [FD_AHB_CLK] = &fd_ahb_clk.clkr,
3211 static struct gdsc *mmcc_msm8996_gdscs[] = {
3212 [MMAGIC_BIMC_GDSC] = &mmagic_bimc_gdsc,
3213 [MMAGIC_VIDEO_GDSC] = &mmagic_video_gdsc,
3214 [MMAGIC_MDSS_GDSC] = &mmagic_mdss_gdsc,
3215 [MMAGIC_CAMSS_GDSC] = &mmagic_camss_gdsc,
3216 [VENUS_GDSC] = &venus_gdsc,
3217 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
3218 [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
3219 [CAMSS_GDSC] = &camss_gdsc,
3220 [VFE0_GDSC] = &vfe0_gdsc,
3221 [VFE1_GDSC] = &vfe1_gdsc,
3222 [JPEG_GDSC] = &jpeg_gdsc,
3223 [CPP_GDSC] = &cpp_gdsc,
3224 [FD_GDSC] = &fd_gdsc,
3225 [MDSS_GDSC] = &mdss_gdsc,
3228 static const struct qcom_reset_map mmcc_msm8996_resets[] = {
3229 [MMAGICAHB_BCR] = { 0x5020 },
3230 [MMAGIC_CFG_BCR] = { 0x5050 },
3231 [MISC_BCR] = { 0x5010 },
3232 [BTO_BCR] = { 0x5030 },
3233 [MMAGICAXI_BCR] = { 0x5060 },
3234 [MMAGICMAXI_BCR] = { 0x5070 },
3235 [DSA_BCR] = { 0x50a0 },
3236 [MMAGIC_CAMSS_BCR] = { 0x3c40 },
3237 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
3238 [SMMU_VFE_BCR] = { 0x3c00 },
3239 [SMMU_CPP_BCR] = { 0x3c10 },
3240 [SMMU_JPEG_BCR] = { 0x3c20 },
3241 [MMAGIC_MDSS_BCR] = { 0x2470 },
3242 [THROTTLE_MDSS_BCR] = { 0x2460 },
3243 [SMMU_ROT_BCR] = { 0x2440 },
3244 [SMMU_MDP_BCR] = { 0x2450 },
3245 [MMAGIC_VIDEO_BCR] = { 0x1190 },
3246 [THROTTLE_VIDEO_BCR] = { 0x1180 },
3247 [SMMU_VIDEO_BCR] = { 0x1170 },
3248 [MMAGIC_BIMC_BCR] = { 0x5290 },
3249 [GPU_GX_BCR] = { 0x4020 },
3250 [GPU_BCR] = { 0x4030 },
3251 [GPU_AON_BCR] = { 0x4040 },
3252 [VMEM_BCR] = { 0x1200 },
3253 [MMSS_RBCPR_BCR] = { 0x4080 },
3254 [VIDEO_BCR] = { 0x1020 },
3255 [MDSS_BCR] = { 0x2300 },
3256 [CAMSS_TOP_BCR] = { 0x3480 },
3257 [CAMSS_AHB_BCR] = { 0x3488 },
3258 [CAMSS_MICRO_BCR] = { 0x3490 },
3259 [CAMSS_CCI_BCR] = { 0x3340 },
3260 [CAMSS_PHY0_BCR] = { 0x3020 },
3261 [CAMSS_PHY1_BCR] = { 0x3050 },
3262 [CAMSS_PHY2_BCR] = { 0x3080 },
3263 [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 },
3264 [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 },
3265 [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 },
3266 [CAMSS_JPEG_BCR] = { 0x35a0 },
3267 [CAMSS_VFE_BCR] = { 0x36a0 },
3268 [CAMSS_VFE0_BCR] = { 0x3660 },
3269 [CAMSS_VFE1_BCR] = { 0x3670 },
3270 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
3271 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
3272 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
3273 [CAMSS_CPP_BCR] = { 0x36d0 },
3274 [CAMSS_CSI0_BCR] = { 0x30b0 },
3275 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
3276 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
3277 [CAMSS_CSI1_BCR] = { 0x3120 },
3278 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
3279 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
3280 [CAMSS_CSI2_BCR] = { 0x3180 },
3281 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
3282 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
3283 [CAMSS_CSI3_BCR] = { 0x31e0 },
3284 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
3285 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
3286 [CAMSS_ISPIF_BCR] = { 0x3220 },
3287 [FD_BCR] = { 0x3b60 },
3288 [MMSS_SPDM_RM_BCR] = { 0x300 },
3291 static const struct regmap_config mmcc_msm8996_regmap_config = {
3295 .max_register = 0xb008,
3299 static const struct qcom_cc_desc mmcc_msm8996_desc = {
3300 .config = &mmcc_msm8996_regmap_config,
3301 .clks = mmcc_msm8996_clocks,
3302 .num_clks = ARRAY_SIZE(mmcc_msm8996_clocks),
3303 .resets = mmcc_msm8996_resets,
3304 .num_resets = ARRAY_SIZE(mmcc_msm8996_resets),
3305 .gdscs = mmcc_msm8996_gdscs,
3306 .num_gdscs = ARRAY_SIZE(mmcc_msm8996_gdscs),
3309 static const struct of_device_id mmcc_msm8996_match_table[] = {
3310 { .compatible = "qcom,mmcc-msm8996" },
3313 MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table);
3315 static int mmcc_msm8996_probe(struct platform_device *pdev)
3317 struct device *dev = &pdev->dev;
3319 struct regmap *regmap;
3321 regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc);
3323 return PTR_ERR(regmap);
3325 /* Disable the AHB DCD */
3326 regmap_update_bits(regmap, 0x50d8, BIT(31), 0);
3327 /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */
3328 regmap_update_bits(regmap, 0x5054, BIT(15), 0);
3330 for (i = 0; i < ARRAY_SIZE(mmcc_msm8996_hws); i++) {
3331 ret = devm_clk_hw_register(dev, mmcc_msm8996_hws[i]);
3336 return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap);
3339 static struct platform_driver mmcc_msm8996_driver = {
3340 .probe = mmcc_msm8996_probe,
3342 .name = "mmcc-msm8996",
3343 .of_match_table = mmcc_msm8996_match_table,
3346 module_platform_driver(mmcc_msm8996_driver);
3348 MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver");
3349 MODULE_LICENSE("GPL v2");
3350 MODULE_ALIAS("platform:mmcc-msm8996");