2 * r8a7778 Core CPG Clocks
4 * Copyright (C) 2014 Ulrich Hecht
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
11 #include <linux/clk-provider.h>
12 #include <linux/clk/renesas.h>
13 #include <linux/of_address.h>
14 #include <linux/slab.h>
15 #include <linux/soc/renesas/rcar-rst.h>
18 struct clk_onecell_data data;
23 /* PLL multipliers per bits 11, 12, and 18 of MODEMR */
25 unsigned long plla_mult;
26 unsigned long pllb_mult;
27 } r8a7778_rates[] __initconst = {
37 /* Clock dividers per bits 1 and 2 of MODEMR */
41 } r8a7778_divs[6] __initconst = {
42 { "b", { 12, 12, 16, 18 } },
43 { "out", { 12, 12, 16, 18 } },
44 { "p", { 16, 12, 16, 12 } },
45 { "s", { 4, 3, 4, 3 } },
46 { "s1", { 8, 6, 8, 6 } },
49 static u32 cpg_mode_rates __initdata;
50 static u32 cpg_mode_divs __initdata;
52 static struct clk * __init
53 r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg,
56 if (!strcmp(name, "plla")) {
57 return clk_register_fixed_factor(NULL, "plla",
58 of_clk_get_parent_name(np, 0), 0,
59 r8a7778_rates[cpg_mode_rates].plla_mult, 1);
60 } else if (!strcmp(name, "pllb")) {
61 return clk_register_fixed_factor(NULL, "pllb",
62 of_clk_get_parent_name(np, 0), 0,
63 r8a7778_rates[cpg_mode_rates].pllb_mult, 1);
67 for (i = 0; i < ARRAY_SIZE(r8a7778_divs); i++) {
68 if (!strcmp(name, r8a7778_divs[i].name)) {
69 return clk_register_fixed_factor(NULL,
72 r8a7778_divs[i].div[cpg_mode_divs]);
77 return ERR_PTR(-EINVAL);
81 static void __init r8a7778_cpg_clocks_init(struct device_node *np)
83 struct r8a7778_cpg *cpg;
89 if (rcar_rst_read_mode_pins(&mode))
92 BUG_ON(!(mode & BIT(19)));
94 cpg_mode_rates = (!!(mode & BIT(18)) << 2) |
95 (!!(mode & BIT(12)) << 1) |
97 cpg_mode_divs = (!!(mode & BIT(2)) << 1) |
100 num_clks = of_property_count_strings(np, "clock-output-names");
102 pr_err("%s: failed to count clocks\n", __func__);
106 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
107 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
108 if (cpg == NULL || clks == NULL) {
109 /* We're leaking memory on purpose, there's no point in cleaning
110 * up as the system won't boot anyway.
115 spin_lock_init(&cpg->lock);
117 cpg->data.clks = clks;
118 cpg->data.clk_num = num_clks;
120 cpg->reg = of_iomap(np, 0);
121 if (WARN_ON(cpg->reg == NULL))
124 for (i = 0; i < num_clks; ++i) {
128 of_property_read_string_index(np, "clock-output-names", i,
131 clk = r8a7778_cpg_register_clock(np, cpg, name);
133 pr_err("%s: failed to register %s %s clock (%ld)\n",
134 __func__, np->name, name, PTR_ERR(clk));
136 cpg->data.clks[i] = clk;
139 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
141 cpg_mstp_add_clk_domain(np);
144 CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
145 r8a7778_cpg_clocks_init);