drivers/clk/renesas/r8a7796-cpg-mssr.c

   1 /*
   2  * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
   3  *
   4  * Copyright (C) 2016 Glider bvba
   5  *
   6  * Based on r8a7795-cpg-mssr.c
   7  *
   8  * Copyright (C) 2015 Glider bvba
   9  * Copyright (C) 2015 Renesas Electronics Corp.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; version 2 of the License.
  14  */
  15
  16 #include <linux/device.h>
  17 #include <linux/init.h>
  18 #include <linux/kernel.h>
  19 #include <linux/soc/renesas/rcar-rst.h>
  20
  21 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
  22
  23 #include "renesas-cpg-mssr.h"
  24 #include "rcar-gen3-cpg.h"
  25
  26 enum clk_ids {
  27         /* Core Clock Outputs exported to DT */
  28         LAST_DT_CORE_CLK = R8A7796_CLK_OSC,
  29
  30         /* External Input Clocks */
  31         CLK_EXTAL,
  32         CLK_EXTALR,
  33
  34         /* Internal Core Clocks */
  35         CLK_MAIN,
  36         CLK_PLL0,
  37         CLK_PLL1,
  38         CLK_PLL2,
  39         CLK_PLL3,
  40         CLK_PLL4,
  41         CLK_PLL1_DIV2,
  42         CLK_PLL1_DIV4,
  43         CLK_S0,
  44         CLK_S1,
  45         CLK_S2,
  46         CLK_S3,
  47         CLK_SDSRC,
  48         CLK_SSPSRC,
  49         CLK_RINT,
  50
  51         /* Module Clocks */
  52         MOD_CLK_BASE
  53 };
  54
  55 static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
  56         /* External Clock Inputs */
  57         DEF_INPUT("extal",  CLK_EXTAL),
  58         DEF_INPUT("extalr", CLK_EXTALR),
  59
  60         /* Internal Core Clocks */
  61         DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
  62         DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
  63         DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
  64         DEF_BASE(".pll2",       CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
  65         DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
  66         DEF_BASE(".pll4",       CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
  67
  68         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
  69         DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
  70         DEF_FIXED(".s0",        CLK_S0,            CLK_PLL1_DIV2,  2, 1),
  71         DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),
  72         DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
  73         DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
  74         DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
  75
  76         /* Core Clock Outputs */
  77         DEF_FIXED("ztr",        R8A7796_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
  78         DEF_FIXED("ztrd2",      R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
  79         DEF_FIXED("zt",         R8A7796_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
  80         DEF_FIXED("zx",         R8A7796_CLK_ZX,    CLK_PLL1_DIV2,  2, 1),
  81         DEF_FIXED("s0d1",       R8A7796_CLK_S0D1,  CLK_S0,         1, 1),
  82         DEF_FIXED("s0d2",       R8A7796_CLK_S0D2,  CLK_S0,         2, 1),
  83         DEF_FIXED("s0d3",       R8A7796_CLK_S0D3,  CLK_S0,         3, 1),
  84         DEF_FIXED("s0d4",       R8A7796_CLK_S0D4,  CLK_S0,         4, 1),
  85         DEF_FIXED("s0d6",       R8A7796_CLK_S0D6,  CLK_S0,         6, 1),
  86         DEF_FIXED("s0d8",       R8A7796_CLK_S0D8,  CLK_S0,         8, 1),
  87         DEF_FIXED("s0d12",      R8A7796_CLK_S0D12, CLK_S0,        12, 1),
  88         DEF_FIXED("s1d1",       R8A7796_CLK_S1D1,  CLK_S1,         1, 1),
  89         DEF_FIXED("s1d2",       R8A7796_CLK_S1D2,  CLK_S1,         2, 1),
  90         DEF_FIXED("s1d4",       R8A7796_CLK_S1D4,  CLK_S1,         4, 1),
  91         DEF_FIXED("s2d1",       R8A7796_CLK_S2D1,  CLK_S2,         1, 1),
  92         DEF_FIXED("s2d2",       R8A7796_CLK_S2D2,  CLK_S2,         2, 1),
  93         DEF_FIXED("s2d4",       R8A7796_CLK_S2D4,  CLK_S2,         4, 1),
  94         DEF_FIXED("s3d1",       R8A7796_CLK_S3D1,  CLK_S3,         1, 1),
  95         DEF_FIXED("s3d2",       R8A7796_CLK_S3D2,  CLK_S3,         2, 1),
  96         DEF_FIXED("s3d4",       R8A7796_CLK_S3D4,  CLK_S3,         4, 1),
  97
  98         DEF_GEN3_SD("sd0",      R8A7796_CLK_SD0,   CLK_SDSRC,    0x0074),
  99         DEF_GEN3_SD("sd1",      R8A7796_CLK_SD1,   CLK_SDSRC,    0x0078),
 100         DEF_GEN3_SD("sd2",      R8A7796_CLK_SD2,   CLK_SDSRC,    0x0268),
 101         DEF_GEN3_SD("sd3",      R8A7796_CLK_SD3,   CLK_SDSRC,    0x026c),
 102
 103         DEF_FIXED("cl",         R8A7796_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 104         DEF_FIXED("cp",         R8A7796_CLK_CP,    CLK_EXTAL,      2, 1),
 105
 106         DEF_DIV6P1("csi0",      R8A7796_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
 107
 108         DEF_DIV6_RO("osc",      R8A7796_CLK_OSC,   CLK_EXTAL, CPG_RCKCR,  8),
 109         DEF_DIV6_RO("r_int",    CLK_RINT,          CLK_EXTAL, CPG_RCKCR, 32),
 110
 111         DEF_BASE("r",           R8A7796_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),
 112 };
 113
 114 static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
 115         DEF_MOD("scif5",                 202,   R8A7796_CLK_S3D4),
 116         DEF_MOD("scif4",                 203,   R8A7796_CLK_S3D4),
 117         DEF_MOD("scif3",                 204,   R8A7796_CLK_S3D4),
 118         DEF_MOD("scif1",                 206,   R8A7796_CLK_S3D4),
 119         DEF_MOD("scif0",                 207,   R8A7796_CLK_S3D4),
 120         DEF_MOD("sys-dmac2",             217,   R8A7796_CLK_S0D3),
 121         DEF_MOD("sys-dmac1",             218,   R8A7796_CLK_S0D3),
 122         DEF_MOD("sys-dmac0",             219,   R8A7796_CLK_S0D3),
 123         DEF_MOD("cmt3",                  300,   R8A7796_CLK_R),
 124         DEF_MOD("cmt2",                  301,   R8A7796_CLK_R),
 125         DEF_MOD("cmt1",                  302,   R8A7796_CLK_R),
 126         DEF_MOD("cmt0",                  303,   R8A7796_CLK_R),
 127         DEF_MOD("scif2",                 310,   R8A7796_CLK_S3D4),
 128         DEF_MOD("sdif3",                 311,   R8A7796_CLK_SD3),
 129         DEF_MOD("sdif2",                 312,   R8A7796_CLK_SD2),
 130         DEF_MOD("sdif1",                 313,   R8A7796_CLK_SD1),
 131         DEF_MOD("sdif0",                 314,   R8A7796_CLK_SD0),
 132         DEF_MOD("rwdt0",                 402,   R8A7796_CLK_R),
 133         DEF_MOD("intc-ap",               408,   R8A7796_CLK_S3D1),
 134         DEF_MOD("drif7",                 508,   R8A7796_CLK_S3D2),
 135         DEF_MOD("drif6",                 509,   R8A7796_CLK_S3D2),
 136         DEF_MOD("drif5",                 510,   R8A7796_CLK_S3D2),
 137         DEF_MOD("drif4",                 511,   R8A7796_CLK_S3D2),
 138         DEF_MOD("drif3",                 512,   R8A7796_CLK_S3D2),
 139         DEF_MOD("drif2",                 513,   R8A7796_CLK_S3D2),
 140         DEF_MOD("drif1",                 514,   R8A7796_CLK_S3D2),
 141         DEF_MOD("drif0",                 515,   R8A7796_CLK_S3D2),
 142         DEF_MOD("hscif4",                516,   R8A7796_CLK_S3D1),
 143         DEF_MOD("hscif3",                517,   R8A7796_CLK_S3D1),
 144         DEF_MOD("hscif2",                518,   R8A7796_CLK_S3D1),
 145         DEF_MOD("hscif1",                519,   R8A7796_CLK_S3D1),
 146         DEF_MOD("hscif0",                520,   R8A7796_CLK_S3D1),
 147         DEF_MOD("thermal",               522,   R8A7796_CLK_CP),
 148         DEF_MOD("fcpvd2",                601,   R8A7796_CLK_S0D2),
 149         DEF_MOD("fcpvd1",                602,   R8A7796_CLK_S0D2),
 150         DEF_MOD("fcpvd0",                603,   R8A7796_CLK_S0D2),
 151         DEF_MOD("fcpvb0",                607,   R8A7796_CLK_S0D1),
 152         DEF_MOD("fcpvi0",                611,   R8A7796_CLK_S0D1),
 153         DEF_MOD("fcpf0",                 615,   R8A7796_CLK_S0D1),
 154         DEF_MOD("fcpci0",                617,   R8A7796_CLK_S0D2),
 155         DEF_MOD("fcpcs",                 619,   R8A7796_CLK_S0D2),
 156         DEF_MOD("vspd2",                 621,   R8A7796_CLK_S0D2),
 157         DEF_MOD("vspd1",                 622,   R8A7796_CLK_S0D2),
 158         DEF_MOD("vspd0",                 623,   R8A7796_CLK_S0D2),
 159         DEF_MOD("vspb",                  626,   R8A7796_CLK_S0D1),
 160         DEF_MOD("vspi0",                 631,   R8A7796_CLK_S0D1),
 161         DEF_MOD("csi20",                 714,   R8A7796_CLK_CSI0),
 162         DEF_MOD("csi40",                 716,   R8A7796_CLK_CSI0),
 163         DEF_MOD("du2",                   722,   R8A7796_CLK_S2D1),
 164         DEF_MOD("du1",                   723,   R8A7796_CLK_S2D1),
 165         DEF_MOD("du0",                   724,   R8A7796_CLK_S2D1),
 166         DEF_MOD("lvds",                  727,   R8A7796_CLK_S2D1),
 167         DEF_MOD("vin7",                  804,   R8A7796_CLK_S0D2),
 168         DEF_MOD("vin6",                  805,   R8A7796_CLK_S0D2),
 169         DEF_MOD("vin5",                  806,   R8A7796_CLK_S0D2),
 170         DEF_MOD("vin4",                  807,   R8A7796_CLK_S0D2),
 171         DEF_MOD("vin3",                  808,   R8A7796_CLK_S0D2),
 172         DEF_MOD("vin2",                  809,   R8A7796_CLK_S0D2),
 173         DEF_MOD("vin1",                  810,   R8A7796_CLK_S0D2),
 174         DEF_MOD("vin0",                  811,   R8A7796_CLK_S0D2),
 175         DEF_MOD("etheravb",              812,   R8A7796_CLK_S0D6),
 176         DEF_MOD("gpio7",                 905,   R8A7796_CLK_S3D4),
 177         DEF_MOD("gpio6",                 906,   R8A7796_CLK_S3D4),
 178         DEF_MOD("gpio5",                 907,   R8A7796_CLK_S3D4),
 179         DEF_MOD("gpio4",                 908,   R8A7796_CLK_S3D4),
 180         DEF_MOD("gpio3",                 909,   R8A7796_CLK_S3D4),
 181         DEF_MOD("gpio2",                 910,   R8A7796_CLK_S3D4),
 182         DEF_MOD("gpio1",                 911,   R8A7796_CLK_S3D4),
 183         DEF_MOD("gpio0",                 912,   R8A7796_CLK_S3D4),
 184         DEF_MOD("i2c6",                  918,   R8A7796_CLK_S0D6),
 185         DEF_MOD("i2c5",                  919,   R8A7796_CLK_S0D6),
 186         DEF_MOD("i2c4",                  927,   R8A7796_CLK_S0D6),
 187         DEF_MOD("i2c3",                  928,   R8A7796_CLK_S0D6),
 188         DEF_MOD("i2c2",                  929,   R8A7796_CLK_S3D2),
 189         DEF_MOD("i2c1",                  930,   R8A7796_CLK_S3D2),
 190         DEF_MOD("i2c0",                  931,   R8A7796_CLK_S3D2),
 191 };
 192
 193 static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
 194         MOD_CLK_ID(408),        /* INTC-AP (GIC) */
 195 };
 196
 197
 198 /*
 199  * CPG Clock Data
 200  */
 201
 202 /*
 203  *   MD         EXTAL           PLL0    PLL1    PLL2    PLL3    PLL4
 204  * 14 13 19 17  (MHz)
 205  *-------------------------------------------------------------------
 206  * 0  0  0  0   16.66 x 1       x180    x192    x144    x192    x144
 207  * 0  0  0  1   16.66 x 1       x180    x192    x144    x128    x144
 208  * 0  0  1  0   Prohibited setting
 209  * 0  0  1  1   16.66 x 1       x180    x192    x144    x192    x144
 210  * 0  1  0  0   20    x 1       x150    x160    x120    x160    x120
 211  * 0  1  0  1   20    x 1       x150    x160    x120    x106    x120
 212  * 0  1  1  0   Prohibited setting
 213  * 0  1  1  1   20    x 1       x150    x160    x120    x160    x120
 214  * 1  0  0  0   25    x 1       x120    x128    x96     x128    x96
 215  * 1  0  0  1   25    x 1       x120    x128    x96     x84     x96
 216  * 1  0  1  0   Prohibited setting
 217  * 1  0  1  1   25    x 1       x120    x128    x96     x128    x96
 218  * 1  1  0  0   33.33 / 2       x180    x192    x144    x192    x144
 219  * 1  1  0  1   33.33 / 2       x180    x192    x144    x128    x144
 220  * 1  1  1  0   Prohibited setting
 221  * 1  1  1  1   33.33 / 2       x180    x192    x144    x192    x144
 222  */
 223 #define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 11) | \
 224                                          (((md) & BIT(13)) >> 11) | \
 225                                          (((md) & BIT(19)) >> 18) | \
 226                                          (((md) & BIT(17)) >> 17))
 227
 228 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
 229         /* EXTAL div    PLL1 mult       PLL3 mult */
 230         { 1,            192,            192,    },
 231         { 1,            192,            128,    },
 232         { 0, /* Prohibited setting */           },
 233         { 1,            192,            192,    },
 234         { 1,            160,            160,    },
 235         { 1,            160,            106,    },
 236         { 0, /* Prohibited setting */           },
 237         { 1,            160,            160,    },
 238         { 1,            128,            128,    },
 239         { 1,            128,            84,     },
 240         { 0, /* Prohibited setting */           },
 241         { 1,            128,            128,    },
 242         { 2,            192,            192,    },
 243         { 2,            192,            128,    },
 244         { 0, /* Prohibited setting */           },
 245         { 2,            192,            192,    },
 246 };
 247
 248 static int __init r8a7796_cpg_mssr_init(struct device *dev)
 249 {
 250         const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
 251         u32 cpg_mode;
 252         int error;
 253
 254         error = rcar_rst_read_mode_pins(&cpg_mode);
 255         if (error)
 256                 return error;
 257
 258         cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
 259         if (!cpg_pll_config->extal_div) {
 260                 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
 261                 return -EINVAL;
 262         }
 263
 264         return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR);
 265 }
 266
 267 const struct cpg_mssr_info r8a7796_cpg_mssr_info __initconst = {
 268         /* Core Clocks */
 269         .core_clks = r8a7796_core_clks,
 270         .num_core_clks = ARRAY_SIZE(r8a7796_core_clks),
 271         .last_dt_core_clk = LAST_DT_CORE_CLK,
 272         .num_total_core_clks = MOD_CLK_BASE,
 273
 274         /* Module Clocks */
 275         .mod_clks = r8a7796_mod_clks,
 276         .num_mod_clks = ARRAY_SIZE(r8a7796_mod_clks),
 277         .num_hw_mod_clks = 12 * 32,
 278
 279         /* Critical Module Clocks */
 280         .crit_mod_clks = r8a7796_crit_mod_clks,
 281         .num_crit_mod_clks = ARRAY_SIZE(r8a7796_crit_mod_clks),
 282
 283         /* Callbacks */
 284         .init = r8a7796_cpg_mssr_init,
 285         .cpg_clk_register = rcar_gen3_cpg_clk_register,
 286 };