drivers/clk/renesas/renesas-cpg-mssr.c

   1 /*
   2  * Renesas Clock Pulse Generator / Module Standby and Software Reset
   3  *
   4  * Copyright (C) 2015 Glider bvba
   5  *
   6  * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
   7  *
   8  * Copyright (C) 2013 Ideas On Board SPRL
   9  * Copyright (C) 2015 Renesas Electronics Corp.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; version 2 of the License.
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/clk-provider.h>
  18 #include <linux/clk/renesas.h>
  19 #include <linux/delay.h>
  20 #include <linux/device.h>
  21 #include <linux/init.h>
  22 #include <linux/mod_devicetable.h>
  23 #include <linux/module.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_device.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_clock.h>
  28 #include <linux/pm_domain.h>
  29 #include <linux/reset-controller.h>
  30 #include <linux/slab.h>
  31
  32 #include <dt-bindings/clock/renesas-cpg-mssr.h>
  33
  34 #include "renesas-cpg-mssr.h"
  35 #include "clk-div6.h"
  36
  37 #ifdef DEBUG
  38 #define WARN_DEBUG(x)   WARN_ON(x)
  39 #else
  40 #define WARN_DEBUG(x)   do { } while (0)
  41 #endif
  42
  43
  44 /*
  45  * Module Standby and Software Reset register offets.
  46  *
  47  * If the registers exist, these are valid for SH-Mobile, R-Mobile,
  48  * R-Car Gen2, R-Car Gen3, and RZ/G1.
  49  * These are NOT valid for R-Car Gen1 and RZ/A1!
  50  */
  51
  52 /*
  53  * Module Stop Status Register offsets
  54  */
  55
  56 static const u16 mstpsr[] = {
  57         0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
  58         0x9A0, 0x9A4, 0x9A8, 0x9AC,
  59 };
  60
  61 #define MSTPSR(i)       mstpsr[i]
  62
  63
  64 /*
  65  * System Module Stop Control Register offsets
  66  */
  67
  68 static const u16 smstpcr[] = {
  69         0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
  70         0x990, 0x994, 0x998, 0x99C,
  71 };
  72
  73 #define SMSTPCR(i)      smstpcr[i]
  74
  75
  76 /*
  77  * Software Reset Register offsets
  78  */
  79
  80 static const u16 srcr[] = {
  81         0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
  82         0x920, 0x924, 0x928, 0x92C,
  83 };
  84
  85 #define SRCR(i)         srcr[i]
  86
  87
  88 /* Realtime Module Stop Control Register offsets */
  89 #define RMSTPCR(i)      (smstpcr[i] - 0x20)
  90
  91 /* Modem Module Stop Control Register offsets (r8a73a4) */
  92 #define MMSTPCR(i)      (smstpcr[i] + 0x20)
  93
  94 /* Software Reset Clearing Register offsets */
  95 #define SRSTCLR(i)      (0x940 + (i) * 4)
  96
  97
  98 /**
  99  * Clock Pulse Generator / Module Standby and Software Reset Private Data
 100  *
 101  * @rcdev: Optional reset controller entity
 102  * @dev: CPG/MSSR device
 103  * @base: CPG/MSSR register block base address
 104  * @rmw_lock: protects RMW register accesses
 105  * @clks: Array containing all Core and Module Clocks
 106  * @num_core_clks: Number of Core Clocks in clks[]
 107  * @num_mod_clks: Number of Module Clocks in clks[]
 108  * @last_dt_core_clk: ID of the last Core Clock exported to DT
 109  */
 110 struct cpg_mssr_priv {
 111 #ifdef CONFIG_RESET_CONTROLLER
 112         struct reset_controller_dev rcdev;
 113 #endif
 114         struct device *dev;
 115         void __iomem *base;
 116         spinlock_t rmw_lock;
 117
 118         struct clk **clks;
 119         unsigned int num_core_clks;
 120         unsigned int num_mod_clks;
 121         unsigned int last_dt_core_clk;
 122 };
 123
 124
 125 /**
 126  * struct mstp_clock - MSTP gating clock
 127  * @hw: handle between common and hardware-specific interfaces
 128  * @index: MSTP clock number
 129  * @priv: CPG/MSSR private data
 130  */
 131 struct mstp_clock {
 132         struct clk_hw hw;
 133         u32 index;
 134         struct cpg_mssr_priv *priv;
 135 };
 136
 137 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
 138
 139 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
 140 {
 141         struct mstp_clock *clock = to_mstp_clock(hw);
 142         struct cpg_mssr_priv *priv = clock->priv;
 143         unsigned int reg = clock->index / 32;
 144         unsigned int bit = clock->index % 32;
 145         struct device *dev = priv->dev;
 146         u32 bitmask = BIT(bit);
 147         unsigned long flags;
 148         unsigned int i;
 149         u32 value;
 150
 151         dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
 152                 enable ? "ON" : "OFF");
 153         spin_lock_irqsave(&priv->rmw_lock, flags);
 154
 155         value = readl(priv->base + SMSTPCR(reg));
 156         if (enable)
 157                 value &= ~bitmask;
 158         else
 159                 value |= bitmask;
 160         writel(value, priv->base + SMSTPCR(reg));
 161
 162         spin_unlock_irqrestore(&priv->rmw_lock, flags);
 163
 164         if (!enable)
 165                 return 0;
 166
 167         for (i = 1000; i > 0; --i) {
 168                 if (!(readl(priv->base + MSTPSR(reg)) & bitmask))
 169                         break;
 170                 cpu_relax();
 171         }
 172
 173         if (!i) {
 174                 dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
 175                         priv->base + SMSTPCR(reg), bit);
 176                 return -ETIMEDOUT;
 177         }
 178
 179         return 0;
 180 }
 181
 182 static int cpg_mstp_clock_enable(struct clk_hw *hw)
 183 {
 184         return cpg_mstp_clock_endisable(hw, true);
 185 }
 186
 187 static void cpg_mstp_clock_disable(struct clk_hw *hw)
 188 {
 189         cpg_mstp_clock_endisable(hw, false);
 190 }
 191
 192 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
 193 {
 194         struct mstp_clock *clock = to_mstp_clock(hw);
 195         struct cpg_mssr_priv *priv = clock->priv;
 196         u32 value;
 197
 198         value = readl(priv->base + MSTPSR(clock->index / 32));
 199
 200         return !(value & BIT(clock->index % 32));
 201 }
 202
 203 static const struct clk_ops cpg_mstp_clock_ops = {
 204         .enable = cpg_mstp_clock_enable,
 205         .disable = cpg_mstp_clock_disable,
 206         .is_enabled = cpg_mstp_clock_is_enabled,
 207 };
 208
 209 static
 210 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
 211                                          void *data)
 212 {
 213         unsigned int clkidx = clkspec->args[1];
 214         struct cpg_mssr_priv *priv = data;
 215         struct device *dev = priv->dev;
 216         unsigned int idx;
 217         const char *type;
 218         struct clk *clk;
 219
 220         switch (clkspec->args[0]) {
 221         case CPG_CORE:
 222                 type = "core";
 223                 if (clkidx > priv->last_dt_core_clk) {
 224                         dev_err(dev, "Invalid %s clock index %u\n", type,
 225                                clkidx);
 226                         return ERR_PTR(-EINVAL);
 227                 }
 228                 clk = priv->clks[clkidx];
 229                 break;
 230
 231         case CPG_MOD:
 232                 type = "module";
 233                 idx = MOD_CLK_PACK(clkidx);
 234                 if (clkidx % 100 > 31 || idx >= priv->num_mod_clks) {
 235                         dev_err(dev, "Invalid %s clock index %u\n", type,
 236                                 clkidx);
 237                         return ERR_PTR(-EINVAL);
 238                 }
 239                 clk = priv->clks[priv->num_core_clks + idx];
 240                 break;
 241
 242         default:
 243                 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
 244                 return ERR_PTR(-EINVAL);
 245         }
 246
 247         if (IS_ERR(clk))
 248                 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
 249                        PTR_ERR(clk));
 250         else
 251                 dev_dbg(dev, "clock (%u, %u) is %pC at %pCr Hz\n",
 252                         clkspec->args[0], clkspec->args[1], clk, clk);
 253         return clk;
 254 }
 255
 256 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
 257                                               const struct cpg_mssr_info *info,
 258                                               struct cpg_mssr_priv *priv)
 259 {
 260         struct clk *clk = NULL, *parent;
 261         struct device *dev = priv->dev;
 262         unsigned int id = core->id, div = core->div;
 263         const char *parent_name;
 264
 265         WARN_DEBUG(id >= priv->num_core_clks);
 266         WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
 267
 268         switch (core->type) {
 269         case CLK_TYPE_IN:
 270                 clk = of_clk_get_by_name(priv->dev->of_node, core->name);
 271                 break;
 272
 273         case CLK_TYPE_FF:
 274         case CLK_TYPE_DIV6P1:
 275         case CLK_TYPE_DIV6_RO:
 276                 WARN_DEBUG(core->parent >= priv->num_core_clks);
 277                 parent = priv->clks[core->parent];
 278                 if (IS_ERR(parent)) {
 279                         clk = parent;
 280                         goto fail;
 281                 }
 282
 283                 parent_name = __clk_get_name(parent);
 284
 285                 if (core->type == CLK_TYPE_DIV6_RO)
 286                         /* Multiply with the DIV6 register value */
 287                         div *= (readl(priv->base + core->offset) & 0x3f) + 1;
 288
 289                 if (core->type == CLK_TYPE_DIV6P1) {
 290                         clk = cpg_div6_register(core->name, 1, &parent_name,
 291                                                 priv->base + core->offset);
 292                 } else {
 293                         clk = clk_register_fixed_factor(NULL, core->name,
 294                                                         parent_name, 0,
 295                                                         core->mult, div);
 296                 }
 297                 break;
 298
 299         default:
 300                 if (info->cpg_clk_register)
 301                         clk = info->cpg_clk_register(dev, core, info,
 302                                                      priv->clks, priv->base);
 303                 else
 304                         dev_err(dev, "%s has unsupported core clock type %u\n",
 305                                 core->name, core->type);
 306                 break;
 307         }
 308
 309         if (IS_ERR_OR_NULL(clk))
 310                 goto fail;
 311
 312         dev_dbg(dev, "Core clock %pC at %pCr Hz\n", clk, clk);
 313         priv->clks[id] = clk;
 314         return;
 315
 316 fail:
 317         dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
 318                 core->name, PTR_ERR(clk));
 319 }
 320
 321 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
 322                                              const struct cpg_mssr_info *info,
 323                                              struct cpg_mssr_priv *priv)
 324 {
 325         struct mstp_clock *clock = NULL;
 326         struct device *dev = priv->dev;
 327         unsigned int id = mod->id;
 328         struct clk_init_data init;
 329         struct clk *parent, *clk;
 330         const char *parent_name;
 331         unsigned int i;
 332
 333         WARN_DEBUG(id < priv->num_core_clks);
 334         WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
 335         WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
 336         WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
 337
 338         parent = priv->clks[mod->parent];
 339         if (IS_ERR(parent)) {
 340                 clk = parent;
 341                 goto fail;
 342         }
 343
 344         clock = kzalloc(sizeof(*clock), GFP_KERNEL);
 345         if (!clock) {
 346                 clk = ERR_PTR(-ENOMEM);
 347                 goto fail;
 348         }
 349
 350         init.name = mod->name;
 351         init.ops = &cpg_mstp_clock_ops;
 352         init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
 353         for (i = 0; i < info->num_crit_mod_clks; i++)
 354                 if (id == info->crit_mod_clks[i]) {
 355                         dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
 356                                 mod->name);
 357                         init.flags |= CLK_IS_CRITICAL;
 358                         break;
 359                 }
 360
 361         parent_name = __clk_get_name(parent);
 362         init.parent_names = &parent_name;
 363         init.num_parents = 1;
 364
 365         clock->index = id - priv->num_core_clks;
 366         clock->priv = priv;
 367         clock->hw.init = &init;
 368
 369         clk = clk_register(NULL, &clock->hw);
 370         if (IS_ERR(clk))
 371                 goto fail;
 372
 373         dev_dbg(dev, "Module clock %pC at %pCr Hz\n", clk, clk);
 374         priv->clks[id] = clk;
 375         return;
 376
 377 fail:
 378         dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
 379                 mod->name, PTR_ERR(clk));
 380         kfree(clock);
 381 }
 382
 383 struct cpg_mssr_clk_domain {
 384         struct generic_pm_domain genpd;
 385         struct device_node *np;
 386         unsigned int num_core_pm_clks;
 387         unsigned int core_pm_clks[0];
 388 };
 389
 390 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
 391
 392 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
 393                                struct cpg_mssr_clk_domain *pd)
 394 {
 395         unsigned int i;
 396
 397         if (clkspec->np != pd->np || clkspec->args_count != 2)
 398                 return false;
 399
 400         switch (clkspec->args[0]) {
 401         case CPG_CORE:
 402                 for (i = 0; i < pd->num_core_pm_clks; i++)
 403                         if (clkspec->args[1] == pd->core_pm_clks[i])
 404                                 return true;
 405                 return false;
 406
 407         case CPG_MOD:
 408                 return true;
 409
 410         default:
 411                 return false;
 412         }
 413 }
 414
 415 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
 416 {
 417         struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
 418         struct device_node *np = dev->of_node;
 419         struct of_phandle_args clkspec;
 420         struct clk *clk;
 421         int i = 0;
 422         int error;
 423
 424         if (!pd) {
 425                 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
 426                 return -EPROBE_DEFER;
 427         }
 428
 429         while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
 430                                            &clkspec)) {
 431                 if (cpg_mssr_is_pm_clk(&clkspec, pd))
 432                         goto found;
 433
 434                 of_node_put(clkspec.np);
 435                 i++;
 436         }
 437
 438         return 0;
 439
 440 found:
 441         clk = of_clk_get_from_provider(&clkspec);
 442         of_node_put(clkspec.np);
 443
 444         if (IS_ERR(clk))
 445                 return PTR_ERR(clk);
 446
 447         error = pm_clk_create(dev);
 448         if (error) {
 449                 dev_err(dev, "pm_clk_create failed %d\n", error);
 450                 goto fail_put;
 451         }
 452
 453         error = pm_clk_add_clk(dev, clk);
 454         if (error) {
 455                 dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
 456                 goto fail_destroy;
 457         }
 458
 459         return 0;
 460
 461 fail_destroy:
 462         pm_clk_destroy(dev);
 463 fail_put:
 464         clk_put(clk);
 465         return error;
 466 }
 467
 468 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
 469 {
 470         if (!list_empty(&dev->power.subsys_data->clock_list))
 471                 pm_clk_destroy(dev);
 472 }
 473
 474 static int __init cpg_mssr_add_clk_domain(struct device *dev,
 475                                           const unsigned int *core_pm_clks,
 476                                           unsigned int num_core_pm_clks)
 477 {
 478         struct device_node *np = dev->of_node;
 479         struct generic_pm_domain *genpd;
 480         struct cpg_mssr_clk_domain *pd;
 481         size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
 482
 483         pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
 484         if (!pd)
 485                 return -ENOMEM;
 486
 487         pd->np = np;
 488         pd->num_core_pm_clks = num_core_pm_clks;
 489         memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
 490
 491         genpd = &pd->genpd;
 492         genpd->name = np->name;
 493         genpd->flags = GENPD_FLAG_PM_CLK;
 494         genpd->attach_dev = cpg_mssr_attach_dev;
 495         genpd->detach_dev = cpg_mssr_detach_dev;
 496         pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
 497         cpg_mssr_clk_domain = pd;
 498
 499         of_genpd_add_provider_simple(np, genpd);
 500         return 0;
 501 }
 502
 503 #ifdef CONFIG_RESET_CONTROLLER
 504
 505 #define rcdev_to_priv(x)        container_of(x, struct cpg_mssr_priv, rcdev)
 506
 507 static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
 508                           unsigned long id)
 509 {
 510         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 511         unsigned int reg = id / 32;
 512         unsigned int bit = id % 32;
 513         u32 bitmask = BIT(bit);
 514         unsigned long flags;
 515         u32 value;
 516
 517         dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
 518
 519         /* Reset module */
 520         spin_lock_irqsave(&priv->rmw_lock, flags);
 521         value = readl(priv->base + SRCR(reg));
 522         value |= bitmask;
 523         writel(value, priv->base + SRCR(reg));
 524         spin_unlock_irqrestore(&priv->rmw_lock, flags);
 525
 526         /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
 527         udelay(35);
 528
 529         /* Release module from reset state */
 530         writel(bitmask, priv->base + SRSTCLR(reg));
 531
 532         return 0;
 533 }
 534
 535 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
 536 {
 537         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 538         unsigned int reg = id / 32;
 539         unsigned int bit = id % 32;
 540         u32 bitmask = BIT(bit);
 541         unsigned long flags;
 542         u32 value;
 543
 544         dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
 545
 546         spin_lock_irqsave(&priv->rmw_lock, flags);
 547         value = readl(priv->base + SRCR(reg));
 548         value |= bitmask;
 549         writel(value, priv->base + SRCR(reg));
 550         spin_unlock_irqrestore(&priv->rmw_lock, flags);
 551         return 0;
 552 }
 553
 554 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
 555                              unsigned long id)
 556 {
 557         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 558         unsigned int reg = id / 32;
 559         unsigned int bit = id % 32;
 560         u32 bitmask = BIT(bit);
 561
 562         dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
 563
 564         writel(bitmask, priv->base + SRSTCLR(reg));
 565         return 0;
 566 }
 567
 568 static int cpg_mssr_status(struct reset_controller_dev *rcdev,
 569                            unsigned long id)
 570 {
 571         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 572         unsigned int reg = id / 32;
 573         unsigned int bit = id % 32;
 574         u32 bitmask = BIT(bit);
 575
 576         return !!(readl(priv->base + SRCR(reg)) & bitmask);
 577 }
 578
 579 static const struct reset_control_ops cpg_mssr_reset_ops = {
 580         .reset = cpg_mssr_reset,
 581         .assert = cpg_mssr_assert,
 582         .deassert = cpg_mssr_deassert,
 583         .status = cpg_mssr_status,
 584 };
 585
 586 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev,
 587                                 const struct of_phandle_args *reset_spec)
 588 {
 589         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 590         unsigned int unpacked = reset_spec->args[0];
 591         unsigned int idx = MOD_CLK_PACK(unpacked);
 592
 593         if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) {
 594                 dev_err(priv->dev, "Invalid reset index %u\n", unpacked);
 595                 return -EINVAL;
 596         }
 597
 598         return idx;
 599 }
 600
 601 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
 602 {
 603         priv->rcdev.ops = &cpg_mssr_reset_ops;
 604         priv->rcdev.of_node = priv->dev->of_node;
 605         priv->rcdev.of_reset_n_cells = 1;
 606         priv->rcdev.of_xlate = cpg_mssr_reset_xlate;
 607         priv->rcdev.nr_resets = priv->num_mod_clks;
 608         return devm_reset_controller_register(priv->dev, &priv->rcdev);
 609 }
 610
 611 #else /* !CONFIG_RESET_CONTROLLER */
 612 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
 613 {
 614         return 0;
 615 }
 616 #endif /* !CONFIG_RESET_CONTROLLER */
 617
 618
 619 static const struct of_device_id cpg_mssr_match[] = {
 620 #ifdef CONFIG_ARCH_R8A7743
 621         {
 622                 .compatible = "renesas,r8a7743-cpg-mssr",
 623                 .data = &r8a7743_cpg_mssr_info,
 624         },
 625 #endif
 626 #ifdef CONFIG_ARCH_R8A7745
 627         {
 628                 .compatible = "renesas,r8a7745-cpg-mssr",
 629                 .data = &r8a7745_cpg_mssr_info,
 630         },
 631 #endif
 632 #ifdef CONFIG_ARCH_R8A7795
 633         {
 634                 .compatible = "renesas,r8a7795-cpg-mssr",
 635                 .data = &r8a7795_cpg_mssr_info,
 636         },
 637 #endif
 638 #ifdef CONFIG_ARCH_R8A7796
 639         {
 640                 .compatible = "renesas,r8a7796-cpg-mssr",
 641                 .data = &r8a7796_cpg_mssr_info,
 642         },
 643 #endif
 644         { /* sentinel */ }
 645 };
 646
 647 static void cpg_mssr_del_clk_provider(void *data)
 648 {
 649         of_clk_del_provider(data);
 650 }
 651
 652 static int __init cpg_mssr_probe(struct platform_device *pdev)
 653 {
 654         struct device *dev = &pdev->dev;
 655         struct device_node *np = dev->of_node;
 656         const struct cpg_mssr_info *info;
 657         struct cpg_mssr_priv *priv;
 658         unsigned int nclks, i;
 659         struct resource *res;
 660         struct clk **clks;
 661         int error;
 662
 663         info = of_match_node(cpg_mssr_match, np)->data;
 664         if (info->init) {
 665                 error = info->init(dev);
 666                 if (error)
 667                         return error;
 668         }
 669
 670         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 671         if (!priv)
 672                 return -ENOMEM;
 673
 674         priv->dev = dev;
 675         spin_lock_init(&priv->rmw_lock);
 676
 677         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 678         priv->base = devm_ioremap_resource(dev, res);
 679         if (IS_ERR(priv->base))
 680                 return PTR_ERR(priv->base);
 681
 682         nclks = info->num_total_core_clks + info->num_hw_mod_clks;
 683         clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
 684         if (!clks)
 685                 return -ENOMEM;
 686
 687         priv->clks = clks;
 688         priv->num_core_clks = info->num_total_core_clks;
 689         priv->num_mod_clks = info->num_hw_mod_clks;
 690         priv->last_dt_core_clk = info->last_dt_core_clk;
 691
 692         for (i = 0; i < nclks; i++)
 693                 clks[i] = ERR_PTR(-ENOENT);
 694
 695         for (i = 0; i < info->num_core_clks; i++)
 696                 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
 697
 698         for (i = 0; i < info->num_mod_clks; i++)
 699                 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
 700
 701         error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
 702         if (error)
 703                 return error;
 704
 705         error = devm_add_action_or_reset(dev,
 706                                          cpg_mssr_del_clk_provider,
 707                                          np);
 708         if (error)
 709                 return error;
 710
 711         error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
 712                                         info->num_core_pm_clks);
 713         if (error)
 714                 return error;
 715
 716         error = cpg_mssr_reset_controller_register(priv);
 717         if (error)
 718                 return error;
 719
 720         return 0;
 721 }
 722
 723 static struct platform_driver cpg_mssr_driver = {
 724         .driver         = {
 725                 .name   = "renesas-cpg-mssr",
 726                 .of_match_table = cpg_mssr_match,
 727         },
 728 };
 729
 730 static int __init cpg_mssr_init(void)
 731 {
 732         return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
 733 }
 734
 735 subsys_initcall(cpg_mssr_init);
 736
 737 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
 738 MODULE_LICENSE("GPL v2");