drivers/clk/rockchip/clk-pll.c

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
   6  * Author: Xing Zheng <zhengxing@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <asm/div64.h>
  20 #include <linux/slab.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk-provider.h>
  24 #include <linux/regmap.h>
  25 #include <linux/clk.h>
  26 #include "clk.h"
  27
  28 #define PLL_MODE_MASK           0x3
  29 #define PLL_MODE_SLOW           0x0
  30 #define PLL_MODE_NORM           0x1
  31 #define PLL_MODE_DEEP           0x2
  32 #define PLL_RK3328_MODE_MASK    0x1
  33
  34 struct rockchip_clk_pll {
  35         struct clk_hw           hw;
  36
  37         struct clk_mux          pll_mux;
  38         const struct clk_ops    *pll_mux_ops;
  39
  40         struct notifier_block   clk_nb;
  41
  42         void __iomem            *reg_base;
  43         int                     lock_offset;
  44         unsigned int            lock_shift;
  45         enum rockchip_pll_type  type;
  46         u8                      flags;
  47         const struct rockchip_pll_rate_table *rate_table;
  48         unsigned int            rate_count;
  49         spinlock_t              *lock;
  50
  51         struct rockchip_clk_provider *ctx;
  52 };
  53
  54 #define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw)
  55 #define to_rockchip_clk_pll_nb(nb) \
  56                         container_of(nb, struct rockchip_clk_pll, clk_nb)
  57
  58 static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
  59                             struct rockchip_clk_pll *pll, unsigned long rate)
  60 {
  61         const struct rockchip_pll_rate_table  *rate_table = pll->rate_table;
  62         int i;
  63
  64         for (i = 0; i < pll->rate_count; i++) {
  65                 if (rate == rate_table[i].rate)
  66                         return &rate_table[i];
  67         }
  68
  69         return NULL;
  70 }
  71
  72 static long rockchip_pll_round_rate(struct clk_hw *hw,
  73                             unsigned long drate, unsigned long *prate)
  74 {
  75         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
  76         const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
  77         int i;
  78
  79         /* Assumming rate_table is in descending order */
  80         for (i = 0; i < pll->rate_count; i++) {
  81                 if (drate >= rate_table[i].rate)
  82                         return rate_table[i].rate;
  83         }
  84
  85         /* return minimum supported value */
  86         return rate_table[i - 1].rate;
  87 }
  88
  89 /*
  90  * Wait for the pll to reach the locked state.
  91  * The calling set_rate function is responsible for making sure the
  92  * grf regmap is available.
  93  */
  94 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
  95 {
  96         struct regmap *grf = pll->ctx->grf;
  97         unsigned int val;
  98         int delay = 24000000, ret;
  99
 100         while (delay > 0) {
 101                 ret = regmap_read(grf, pll->lock_offset, &val);
 102                 if (ret) {
 103                         pr_err("%s: failed to read pll lock status: %d\n",
 104                                __func__, ret);
 105                         return ret;
 106                 }
 107
 108                 if (val & BIT(pll->lock_shift))
 109                         return 0;
 110                 delay--;
 111         }
 112
 113         pr_err("%s: timeout waiting for pll to lock\n", __func__);
 114         return -ETIMEDOUT;
 115 }
 116
 117 /**
 118  * PLL used in RK3036
 119  */
 120
 121 #define RK3036_PLLCON(i)                        (i * 0x4)
 122 #define RK3036_PLLCON0_FBDIV_MASK               0xfff
 123 #define RK3036_PLLCON0_FBDIV_SHIFT              0
 124 #define RK3036_PLLCON0_POSTDIV1_MASK            0x7
 125 #define RK3036_PLLCON0_POSTDIV1_SHIFT           12
 126 #define RK3036_PLLCON1_REFDIV_MASK              0x3f
 127 #define RK3036_PLLCON1_REFDIV_SHIFT             0
 128 #define RK3036_PLLCON1_POSTDIV2_MASK            0x7
 129 #define RK3036_PLLCON1_POSTDIV2_SHIFT           6
 130 #define RK3036_PLLCON1_DSMPD_MASK               0x1
 131 #define RK3036_PLLCON1_DSMPD_SHIFT              12
 132 #define RK3036_PLLCON2_FRAC_MASK                0xffffff
 133 #define RK3036_PLLCON2_FRAC_SHIFT               0
 134
 135 #define RK3036_PLLCON1_PWRDOWN                  (1 << 13)
 136
 137 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
 138                                         struct rockchip_pll_rate_table *rate)
 139 {
 140         u32 pllcon;
 141
 142         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
 143         rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT)
 144                                 & RK3036_PLLCON0_FBDIV_MASK);
 145         rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT)
 146                                 & RK3036_PLLCON0_POSTDIV1_MASK);
 147
 148         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
 149         rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT)
 150                                 & RK3036_PLLCON1_REFDIV_MASK);
 151         rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT)
 152                                 & RK3036_PLLCON1_POSTDIV2_MASK);
 153         rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT)
 154                                 & RK3036_PLLCON1_DSMPD_MASK);
 155
 156         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
 157         rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT)
 158                                 & RK3036_PLLCON2_FRAC_MASK);
 159 }
 160
 161 static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
 162                                                      unsigned long prate)
 163 {
 164         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 165         struct rockchip_pll_rate_table cur;
 166         u64 rate64 = prate;
 167
 168         rockchip_rk3036_pll_get_params(pll, &cur);
 169
 170         rate64 *= cur.fbdiv;
 171         do_div(rate64, cur.refdiv);
 172
 173         if (cur.dsmpd == 0) {
 174                 /* fractional mode */
 175                 u64 frac_rate64 = prate * cur.frac;
 176
 177                 do_div(frac_rate64, cur.refdiv);
 178                 rate64 += frac_rate64 >> 24;
 179         }
 180
 181         do_div(rate64, cur.postdiv1);
 182         do_div(rate64, cur.postdiv2);
 183
 184         return (unsigned long)rate64;
 185 }
 186
 187 static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
 188                                 const struct rockchip_pll_rate_table *rate)
 189 {
 190         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
 191         struct clk_mux *pll_mux = &pll->pll_mux;
 192         struct rockchip_pll_rate_table cur;
 193         u32 pllcon;
 194         int rate_change_remuxed = 0;
 195         int cur_parent;
 196         int ret;
 197
 198         pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 199                 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
 200                 rate->postdiv2, rate->dsmpd, rate->frac);
 201
 202         rockchip_rk3036_pll_get_params(pll, &cur);
 203         cur.rate = 0;
 204
 205         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 206         if (cur_parent == PLL_MODE_NORM) {
 207                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 208                 rate_change_remuxed = 1;
 209         }
 210
 211         /* update pll values */
 212         writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
 213                                           RK3036_PLLCON0_FBDIV_SHIFT) |
 214                        HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK,
 215                                              RK3036_PLLCON0_POSTDIV1_SHIFT),
 216                        pll->reg_base + RK3036_PLLCON(0));
 217
 218         writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK,
 219                                                    RK3036_PLLCON1_REFDIV_SHIFT) |
 220                        HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK,
 221                                                      RK3036_PLLCON1_POSTDIV2_SHIFT) |
 222                        HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK,
 223                                                   RK3036_PLLCON1_DSMPD_SHIFT),
 224                        pll->reg_base + RK3036_PLLCON(1));
 225
 226         /* GPLL CON2 is not HIWORD_MASK */
 227         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
 228         pllcon &= ~(RK3036_PLLCON2_FRAC_MASK << RK3036_PLLCON2_FRAC_SHIFT);
 229         pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
 230         writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
 231
 232         /* wait for the pll to lock */
 233         ret = rockchip_pll_wait_lock(pll);
 234         if (ret) {
 235                 pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
 236                         __func__);
 237                 rockchip_rk3036_pll_set_params(pll, &cur);
 238         }
 239
 240         if (rate_change_remuxed)
 241                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 242
 243         return ret;
 244 }
 245
 246 static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 247                                         unsigned long prate)
 248 {
 249         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 250         const struct rockchip_pll_rate_table *rate;
 251
 252         pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
 253                  __func__, __clk_get_name(hw->clk), drate, prate);
 254
 255         /* Get required rate settings from table */
 256         rate = rockchip_get_pll_settings(pll, drate);
 257         if (!rate) {
 258                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 259                         drate, __clk_get_name(hw->clk));
 260                 return -EINVAL;
 261         }
 262
 263         return rockchip_rk3036_pll_set_params(pll, rate);
 264 }
 265
 266 static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
 267 {
 268         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 269
 270         writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
 271                pll->reg_base + RK3036_PLLCON(1));
 272
 273         return 0;
 274 }
 275
 276 static void rockchip_rk3036_pll_disable(struct clk_hw *hw)
 277 {
 278         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 279
 280         writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
 281                              RK3036_PLLCON1_PWRDOWN, 0),
 282                pll->reg_base + RK3036_PLLCON(1));
 283 }
 284
 285 static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw)
 286 {
 287         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 288         u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));
 289
 290         return !(pllcon & RK3036_PLLCON1_PWRDOWN);
 291 }
 292
 293 static void rockchip_rk3036_pll_init(struct clk_hw *hw)
 294 {
 295         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 296         const struct rockchip_pll_rate_table *rate;
 297         struct rockchip_pll_rate_table cur;
 298         unsigned long drate;
 299
 300         if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
 301                 return;
 302
 303         drate = clk_hw_get_rate(hw);
 304         rate = rockchip_get_pll_settings(pll, drate);
 305
 306         /* when no rate setting for the current rate, rely on clk_set_rate */
 307         if (!rate)
 308                 return;
 309
 310         rockchip_rk3036_pll_get_params(pll, &cur);
 311
 312         pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
 313                  drate);
 314         pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 315                  cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
 316                  cur.dsmpd, cur.frac);
 317         pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 318                  rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
 319                  rate->dsmpd, rate->frac);
 320
 321         if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
 322                 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
 323                 rate->dsmpd != cur.dsmpd ||
 324                 (!cur.dsmpd && (rate->frac != cur.frac))) {
 325                 struct clk *parent = clk_get_parent(hw->clk);
 326
 327                 if (!parent) {
 328                         pr_warn("%s: parent of %s not available\n",
 329                                 __func__, __clk_get_name(hw->clk));
 330                         return;
 331                 }
 332
 333                 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
 334                          __func__, __clk_get_name(hw->clk));
 335                 rockchip_rk3036_pll_set_params(pll, rate);
 336         }
 337 }
 338
 339 static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = {
 340         .recalc_rate = rockchip_rk3036_pll_recalc_rate,
 341         .enable = rockchip_rk3036_pll_enable,
 342         .disable = rockchip_rk3036_pll_disable,
 343         .is_enabled = rockchip_rk3036_pll_is_enabled,
 344 };
 345
 346 static const struct clk_ops rockchip_rk3036_pll_clk_ops = {
 347         .recalc_rate = rockchip_rk3036_pll_recalc_rate,
 348         .round_rate = rockchip_pll_round_rate,
 349         .set_rate = rockchip_rk3036_pll_set_rate,
 350         .enable = rockchip_rk3036_pll_enable,
 351         .disable = rockchip_rk3036_pll_disable,
 352         .is_enabled = rockchip_rk3036_pll_is_enabled,
 353         .init = rockchip_rk3036_pll_init,
 354 };
 355
 356 /**
 357  * PLL used in RK3066, RK3188 and RK3288
 358  */
 359
 360 #define RK3066_PLL_RESET_DELAY(nr)      ((nr * 500) / 24 + 1)
 361
 362 #define RK3066_PLLCON(i)                (i * 0x4)
 363 #define RK3066_PLLCON0_OD_MASK          0xf
 364 #define RK3066_PLLCON0_OD_SHIFT         0
 365 #define RK3066_PLLCON0_NR_MASK          0x3f
 366 #define RK3066_PLLCON0_NR_SHIFT         8
 367 #define RK3066_PLLCON1_NF_MASK          0x1fff
 368 #define RK3066_PLLCON1_NF_SHIFT         0
 369 #define RK3066_PLLCON2_NB_MASK          0xfff
 370 #define RK3066_PLLCON2_NB_SHIFT         0
 371 #define RK3066_PLLCON3_RESET            (1 << 5)
 372 #define RK3066_PLLCON3_PWRDOWN          (1 << 1)
 373 #define RK3066_PLLCON3_BYPASS           (1 << 0)
 374
 375 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll,
 376                                         struct rockchip_pll_rate_table *rate)
 377 {
 378         u32 pllcon;
 379
 380         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
 381         rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT)
 382                                 & RK3066_PLLCON0_NR_MASK) + 1;
 383         rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT)
 384                                 & RK3066_PLLCON0_OD_MASK) + 1;
 385
 386         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
 387         rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT)
 388                                 & RK3066_PLLCON1_NF_MASK) + 1;
 389
 390         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
 391         rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT)
 392                                 & RK3066_PLLCON2_NB_MASK) + 1;
 393 }
 394
 395 static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw,
 396                                                      unsigned long prate)
 397 {
 398         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 399         struct rockchip_pll_rate_table cur;
 400         u64 rate64 = prate;
 401         u32 pllcon;
 402
 403         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
 404         if (pllcon & RK3066_PLLCON3_BYPASS) {
 405                 pr_debug("%s: pll %s is bypassed\n", __func__,
 406                         clk_hw_get_name(hw));
 407                 return prate;
 408         }
 409
 410         rockchip_rk3066_pll_get_params(pll, &cur);
 411
 412         rate64 *= cur.nf;
 413         do_div(rate64, cur.nr);
 414         do_div(rate64, cur.no);
 415
 416         return (unsigned long)rate64;
 417 }
 418
 419 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll,
 420                                 const struct rockchip_pll_rate_table *rate)
 421 {
 422         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
 423         struct clk_mux *pll_mux = &pll->pll_mux;
 424         struct rockchip_pll_rate_table cur;
 425         int rate_change_remuxed = 0;
 426         int cur_parent;
 427         int ret;
 428
 429         pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n",
 430                  __func__, rate->rate, rate->nr, rate->no, rate->nf);
 431
 432         rockchip_rk3066_pll_get_params(pll, &cur);
 433         cur.rate = 0;
 434
 435         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 436         if (cur_parent == PLL_MODE_NORM) {
 437                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 438                 rate_change_remuxed = 1;
 439         }
 440
 441         /* enter reset mode */
 442         writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0),
 443                pll->reg_base + RK3066_PLLCON(3));
 444
 445         /* update pll values */
 446         writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
 447                                            RK3066_PLLCON0_NR_SHIFT) |
 448                HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK,
 449                                            RK3066_PLLCON0_OD_SHIFT),
 450                pll->reg_base + RK3066_PLLCON(0));
 451
 452         writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
 453                                                    RK3066_PLLCON1_NF_SHIFT),
 454                        pll->reg_base + RK3066_PLLCON(1));
 455         writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK,
 456                                                    RK3066_PLLCON2_NB_SHIFT),
 457                        pll->reg_base + RK3066_PLLCON(2));
 458
 459         /* leave reset and wait the reset_delay */
 460         writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0),
 461                pll->reg_base + RK3066_PLLCON(3));
 462         udelay(RK3066_PLL_RESET_DELAY(rate->nr));
 463
 464         /* wait for the pll to lock */
 465         ret = rockchip_pll_wait_lock(pll);
 466         if (ret) {
 467                 pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
 468                         __func__);
 469                 rockchip_rk3066_pll_set_params(pll, &cur);
 470         }
 471
 472         if (rate_change_remuxed)
 473                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 474
 475         return ret;
 476 }
 477
 478 static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 479                                         unsigned long prate)
 480 {
 481         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 482         const struct rockchip_pll_rate_table *rate;
 483
 484         pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
 485                  __func__, clk_hw_get_name(hw), drate, prate);
 486
 487         /* Get required rate settings from table */
 488         rate = rockchip_get_pll_settings(pll, drate);
 489         if (!rate) {
 490                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 491                         drate, clk_hw_get_name(hw));
 492                 return -EINVAL;
 493         }
 494
 495         return rockchip_rk3066_pll_set_params(pll, rate);
 496 }
 497
 498 static int rockchip_rk3066_pll_enable(struct clk_hw *hw)
 499 {
 500         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 501
 502         writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),
 503                pll->reg_base + RK3066_PLLCON(3));
 504
 505         return 0;
 506 }
 507
 508 static void rockchip_rk3066_pll_disable(struct clk_hw *hw)
 509 {
 510         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 511
 512         writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN,
 513                              RK3066_PLLCON3_PWRDOWN, 0),
 514                pll->reg_base + RK3066_PLLCON(3));
 515 }
 516
 517 static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw)
 518 {
 519         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 520         u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
 521
 522         return !(pllcon & RK3066_PLLCON3_PWRDOWN);
 523 }
 524
 525 static void rockchip_rk3066_pll_init(struct clk_hw *hw)
 526 {
 527         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 528         const struct rockchip_pll_rate_table *rate;
 529         struct rockchip_pll_rate_table cur;
 530         unsigned long drate;
 531
 532         if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
 533                 return;
 534
 535         drate = clk_hw_get_rate(hw);
 536         rate = rockchip_get_pll_settings(pll, drate);
 537
 538         /* when no rate setting for the current rate, rely on clk_set_rate */
 539         if (!rate)
 540                 return;
 541
 542         rockchip_rk3066_pll_get_params(pll, &cur);
 543
 544         pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n",
 545                  __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr,
 546                  rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb);
 547         if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf
 548                                                      || rate->nb != cur.nb) {
 549                 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
 550                          __func__, clk_hw_get_name(hw));
 551                 rockchip_rk3066_pll_set_params(pll, rate);
 552         }
 553 }
 554
 555 static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = {
 556         .recalc_rate = rockchip_rk3066_pll_recalc_rate,
 557         .enable = rockchip_rk3066_pll_enable,
 558         .disable = rockchip_rk3066_pll_disable,
 559         .is_enabled = rockchip_rk3066_pll_is_enabled,
 560 };
 561
 562 static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
 563         .recalc_rate = rockchip_rk3066_pll_recalc_rate,
 564         .round_rate = rockchip_pll_round_rate,
 565         .set_rate = rockchip_rk3066_pll_set_rate,
 566         .enable = rockchip_rk3066_pll_enable,
 567         .disable = rockchip_rk3066_pll_disable,
 568         .is_enabled = rockchip_rk3066_pll_is_enabled,
 569         .init = rockchip_rk3066_pll_init,
 570 };
 571
 572 /**
 573  * PLL used in RK3399
 574  */
 575
 576 #define RK3399_PLLCON(i)                        (i * 0x4)
 577 #define RK3399_PLLCON0_FBDIV_MASK               0xfff
 578 #define RK3399_PLLCON0_FBDIV_SHIFT              0
 579 #define RK3399_PLLCON1_REFDIV_MASK              0x3f
 580 #define RK3399_PLLCON1_REFDIV_SHIFT             0
 581 #define RK3399_PLLCON1_POSTDIV1_MASK            0x7
 582 #define RK3399_PLLCON1_POSTDIV1_SHIFT           8
 583 #define RK3399_PLLCON1_POSTDIV2_MASK            0x7
 584 #define RK3399_PLLCON1_POSTDIV2_SHIFT           12
 585 #define RK3399_PLLCON2_FRAC_MASK                0xffffff
 586 #define RK3399_PLLCON2_FRAC_SHIFT               0
 587 #define RK3399_PLLCON2_LOCK_STATUS              BIT(31)
 588 #define RK3399_PLLCON3_PWRDOWN                  BIT(0)
 589 #define RK3399_PLLCON3_DSMPD_MASK               0x1
 590 #define RK3399_PLLCON3_DSMPD_SHIFT              3
 591
 592 static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll)
 593 {
 594         u32 pllcon;
 595         int delay = 24000000;
 596
 597         /* poll check the lock status in rk3399 xPLLCON2 */
 598         while (delay > 0) {
 599                 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
 600                 if (pllcon & RK3399_PLLCON2_LOCK_STATUS)
 601                         return 0;
 602
 603                 delay--;
 604         }
 605
 606         pr_err("%s: timeout waiting for pll to lock\n", __func__);
 607         return -ETIMEDOUT;
 608 }
 609
 610 static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll,
 611                                         struct rockchip_pll_rate_table *rate)
 612 {
 613         u32 pllcon;
 614
 615         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0));
 616         rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT)
 617                                 & RK3399_PLLCON0_FBDIV_MASK);
 618
 619         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1));
 620         rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT)
 621                                 & RK3399_PLLCON1_REFDIV_MASK);
 622         rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT)
 623                                 & RK3399_PLLCON1_POSTDIV1_MASK);
 624         rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT)
 625                                 & RK3399_PLLCON1_POSTDIV2_MASK);
 626
 627         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
 628         rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT)
 629                                 & RK3399_PLLCON2_FRAC_MASK);
 630
 631         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3));
 632         rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT)
 633                                 & RK3399_PLLCON3_DSMPD_MASK);
 634 }
 635
 636 static unsigned long rockchip_rk3399_pll_recalc_rate(struct clk_hw *hw,
 637                                                      unsigned long prate)
 638 {
 639         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 640         struct rockchip_pll_rate_table cur;
 641         u64 rate64 = prate;
 642
 643         rockchip_rk3399_pll_get_params(pll, &cur);
 644
 645         rate64 *= cur.fbdiv;
 646         do_div(rate64, cur.refdiv);
 647
 648         if (cur.dsmpd == 0) {
 649                 /* fractional mode */
 650                 u64 frac_rate64 = prate * cur.frac;
 651
 652                 do_div(frac_rate64, cur.refdiv);
 653                 rate64 += frac_rate64 >> 24;
 654         }
 655
 656         do_div(rate64, cur.postdiv1);
 657         do_div(rate64, cur.postdiv2);
 658
 659         return (unsigned long)rate64;
 660 }
 661
 662 static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,
 663                                 const struct rockchip_pll_rate_table *rate)
 664 {
 665         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
 666         struct clk_mux *pll_mux = &pll->pll_mux;
 667         struct rockchip_pll_rate_table cur;
 668         u32 pllcon;
 669         int rate_change_remuxed = 0;
 670         int cur_parent;
 671         int ret;
 672
 673         pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 674                 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
 675                 rate->postdiv2, rate->dsmpd, rate->frac);
 676
 677         rockchip_rk3399_pll_get_params(pll, &cur);
 678         cur.rate = 0;
 679
 680         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 681         if (cur_parent == PLL_MODE_NORM) {
 682                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 683                 rate_change_remuxed = 1;
 684         }
 685
 686         /* update pll values */
 687         writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
 688                                                   RK3399_PLLCON0_FBDIV_SHIFT),
 689                        pll->reg_base + RK3399_PLLCON(0));
 690
 691         writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK,
 692                                                    RK3399_PLLCON1_REFDIV_SHIFT) |
 693                        HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK,
 694                                                      RK3399_PLLCON1_POSTDIV1_SHIFT) |
 695                        HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK,
 696                                                      RK3399_PLLCON1_POSTDIV2_SHIFT),
 697                        pll->reg_base + RK3399_PLLCON(1));
 698
 699         /* xPLL CON2 is not HIWORD_MASK */
 700         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
 701         pllcon &= ~(RK3399_PLLCON2_FRAC_MASK << RK3399_PLLCON2_FRAC_SHIFT);
 702         pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT;
 703         writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2));
 704
 705         writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK,
 706                                             RK3399_PLLCON3_DSMPD_SHIFT),
 707                        pll->reg_base + RK3399_PLLCON(3));
 708
 709         /* wait for the pll to lock */
 710         ret = rockchip_rk3399_pll_wait_lock(pll);
 711         if (ret) {
 712                 pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
 713                         __func__);
 714                 rockchip_rk3399_pll_set_params(pll, &cur);
 715         }
 716
 717         if (rate_change_remuxed)
 718                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 719
 720         return ret;
 721 }
 722
 723 static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 724                                         unsigned long prate)
 725 {
 726         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 727         const struct rockchip_pll_rate_table *rate;
 728
 729         pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
 730                  __func__, __clk_get_name(hw->clk), drate, prate);
 731
 732         /* Get required rate settings from table */
 733         rate = rockchip_get_pll_settings(pll, drate);
 734         if (!rate) {
 735                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 736                         drate, __clk_get_name(hw->clk));
 737                 return -EINVAL;
 738         }
 739
 740         return rockchip_rk3399_pll_set_params(pll, rate);
 741 }
 742
 743 static int rockchip_rk3399_pll_enable(struct clk_hw *hw)
 744 {
 745         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 746
 747         writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0),
 748                pll->reg_base + RK3399_PLLCON(3));
 749
 750         return 0;
 751 }
 752
 753 static void rockchip_rk3399_pll_disable(struct clk_hw *hw)
 754 {
 755         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 756
 757         writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
 758                              RK3399_PLLCON3_PWRDOWN, 0),
 759                pll->reg_base + RK3399_PLLCON(3));
 760 }
 761
 762 static int rockchip_rk3399_pll_is_enabled(struct clk_hw *hw)
 763 {
 764         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 765         u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3));
 766
 767         return !(pllcon & RK3399_PLLCON3_PWRDOWN);
 768 }
 769
 770 static void rockchip_rk3399_pll_init(struct clk_hw *hw)
 771 {
 772         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 773         const struct rockchip_pll_rate_table *rate;
 774         struct rockchip_pll_rate_table cur;
 775         unsigned long drate;
 776
 777         if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
 778                 return;
 779
 780         drate = clk_hw_get_rate(hw);
 781         rate = rockchip_get_pll_settings(pll, drate);
 782
 783         /* when no rate setting for the current rate, rely on clk_set_rate */
 784         if (!rate)
 785                 return;
 786
 787         rockchip_rk3399_pll_get_params(pll, &cur);
 788
 789         pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
 790                  drate);
 791         pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 792                  cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
 793                  cur.dsmpd, cur.frac);
 794         pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 795                  rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
 796                  rate->dsmpd, rate->frac);
 797
 798         if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
 799                 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
 800                 rate->dsmpd != cur.dsmpd ||
 801                 (!cur.dsmpd && (rate->frac != cur.frac))) {
 802                 struct clk *parent = clk_get_parent(hw->clk);
 803
 804                 if (!parent) {
 805                         pr_warn("%s: parent of %s not available\n",
 806                                 __func__, __clk_get_name(hw->clk));
 807                         return;
 808                 }
 809
 810                 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
 811                          __func__, __clk_get_name(hw->clk));
 812                 rockchip_rk3399_pll_set_params(pll, rate);
 813         }
 814 }
 815
 816 static const struct clk_ops rockchip_rk3399_pll_clk_norate_ops = {
 817         .recalc_rate = rockchip_rk3399_pll_recalc_rate,
 818         .enable = rockchip_rk3399_pll_enable,
 819         .disable = rockchip_rk3399_pll_disable,
 820         .is_enabled = rockchip_rk3399_pll_is_enabled,
 821 };
 822
 823 static const struct clk_ops rockchip_rk3399_pll_clk_ops = {
 824         .recalc_rate = rockchip_rk3399_pll_recalc_rate,
 825         .round_rate = rockchip_pll_round_rate,
 826         .set_rate = rockchip_rk3399_pll_set_rate,
 827         .enable = rockchip_rk3399_pll_enable,
 828         .disable = rockchip_rk3399_pll_disable,
 829         .is_enabled = rockchip_rk3399_pll_is_enabled,
 830         .init = rockchip_rk3399_pll_init,
 831 };
 832
 833 /*
 834  * Common registering of pll clocks
 835  */
 836
 837 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
 838                 enum rockchip_pll_type pll_type,
 839                 const char *name, const char *const *parent_names,
 840                 u8 num_parents, int con_offset, int grf_lock_offset,
 841                 int lock_shift, int mode_offset, int mode_shift,
 842                 struct rockchip_pll_rate_table *rate_table,
 843                 unsigned long flags, u8 clk_pll_flags)
 844 {
 845         const char *pll_parents[3];
 846         struct clk_init_data init;
 847         struct rockchip_clk_pll *pll;
 848         struct clk_mux *pll_mux;
 849         struct clk *pll_clk, *mux_clk;
 850         char pll_name[20];
 851
 852         if ((pll_type != pll_rk3328 && num_parents != 2) ||
 853             (pll_type == pll_rk3328 && num_parents != 1)) {
 854                 pr_err("%s: needs two parent clocks\n", __func__);
 855                 return ERR_PTR(-EINVAL);
 856         }
 857
 858         /* name the actual pll */
 859         snprintf(pll_name, sizeof(pll_name), "pll_%s", name);
 860
 861         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 862         if (!pll)
 863                 return ERR_PTR(-ENOMEM);
 864
 865         /* create the mux on top of the real pll */
 866         pll->pll_mux_ops = &clk_mux_ops;
 867         pll_mux = &pll->pll_mux;
 868         pll_mux->reg = ctx->reg_base + mode_offset;
 869         pll_mux->shift = mode_shift;
 870         if (pll_type == pll_rk3328)
 871                 pll_mux->mask = PLL_RK3328_MODE_MASK;
 872         else
 873                 pll_mux->mask = PLL_MODE_MASK;
 874         pll_mux->flags = 0;
 875         pll_mux->lock = &ctx->lock;
 876         pll_mux->hw.init = &init;
 877
 878         if (pll_type == pll_rk3036 ||
 879             pll_type == pll_rk3066 ||
 880             pll_type == pll_rk3328 ||
 881             pll_type == pll_rk3399)
 882                 pll_mux->flags |= CLK_MUX_HIWORD_MASK;
 883
 884         /* the actual muxing is xin24m, pll-output, xin32k */
 885         pll_parents[0] = parent_names[0];
 886         pll_parents[1] = pll_name;
 887         pll_parents[2] = parent_names[1];
 888
 889         init.name = name;
 890         init.flags = CLK_SET_RATE_PARENT;
 891         init.ops = pll->pll_mux_ops;
 892         init.parent_names = pll_parents;
 893         if (pll_type == pll_rk3328)
 894                 init.num_parents = 2;
 895         else
 896                 init.num_parents = ARRAY_SIZE(pll_parents);
 897
 898         mux_clk = clk_register(NULL, &pll_mux->hw);
 899         if (IS_ERR(mux_clk))
 900                 goto err_mux;
 901
 902         /* now create the actual pll */
 903         init.name = pll_name;
 904
 905         /* keep all plls untouched for now */
 906         init.flags = flags | CLK_IGNORE_UNUSED;
 907
 908         init.parent_names = &parent_names[0];
 909         init.num_parents = 1;
 910
 911         if (rate_table) {
 912                 int len;
 913
 914                 /* find count of rates in rate_table */
 915                 for (len = 0; rate_table[len].rate != 0; )
 916                         len++;
 917
 918                 pll->rate_count = len;
 919                 pll->rate_table = kmemdup(rate_table,
 920                                         pll->rate_count *
 921                                         sizeof(struct rockchip_pll_rate_table),
 922                                         GFP_KERNEL);
 923                 WARN(!pll->rate_table,
 924                         "%s: could not allocate rate table for %s\n",
 925                         __func__, name);
 926         }
 927
 928         switch (pll_type) {
 929         case pll_rk3036:
 930         case pll_rk3328:
 931                 if (!pll->rate_table || IS_ERR(ctx->grf))
 932                         init.ops = &rockchip_rk3036_pll_clk_norate_ops;
 933                 else
 934                         init.ops = &rockchip_rk3036_pll_clk_ops;
 935                 break;
 936         case pll_rk3066:
 937                 if (!pll->rate_table || IS_ERR(ctx->grf))
 938                         init.ops = &rockchip_rk3066_pll_clk_norate_ops;
 939                 else
 940                         init.ops = &rockchip_rk3066_pll_clk_ops;
 941                 break;
 942         case pll_rk3399:
 943                 if (!pll->rate_table)
 944                         init.ops = &rockchip_rk3399_pll_clk_norate_ops;
 945                 else
 946                         init.ops = &rockchip_rk3399_pll_clk_ops;
 947                 break;
 948         default:
 949                 pr_warn("%s: Unknown pll type for pll clk %s\n",
 950                         __func__, name);
 951         }
 952
 953         pll->hw.init = &init;
 954         pll->type = pll_type;
 955         pll->reg_base = ctx->reg_base + con_offset;
 956         pll->lock_offset = grf_lock_offset;
 957         pll->lock_shift = lock_shift;
 958         pll->flags = clk_pll_flags;
 959         pll->lock = &ctx->lock;
 960         pll->ctx = ctx;
 961
 962         pll_clk = clk_register(NULL, &pll->hw);
 963         if (IS_ERR(pll_clk)) {
 964                 pr_err("%s: failed to register pll clock %s : %ld\n",
 965                         __func__, name, PTR_ERR(pll_clk));
 966                 goto err_pll;
 967         }
 968
 969         return mux_clk;
 970
 971 err_pll:
 972         clk_unregister(mux_clk);
 973         mux_clk = pll_clk;
 974 err_mux:
 975         kfree(pll);
 976         return mux_clk;
 977 }