drivers/clk/rockchip/clk-pll.c

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
   6  * Author: Xing Zheng <zhengxing@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <asm/div64.h>
  20 #include <linux/slab.h>
  21 #include <linux/io.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk-provider.h>
  24 #include <linux/regmap.h>
  25 #include <linux/clk.h>
  26 #include "clk.h"
  27
  28 #define PLL_MODE_MASK           0x3
  29 #define PLL_MODE_SLOW           0x0
  30 #define PLL_MODE_NORM           0x1
  31 #define PLL_MODE_DEEP           0x2
  32
  33 struct rockchip_clk_pll {
  34         struct clk_hw           hw;
  35
  36         struct clk_mux          pll_mux;
  37         const struct clk_ops    *pll_mux_ops;
  38
  39         struct notifier_block   clk_nb;
  40
  41         void __iomem            *reg_base;
  42         int                     lock_offset;
  43         unsigned int            lock_shift;
  44         enum rockchip_pll_type  type;
  45         u8                      flags;
  46         const struct rockchip_pll_rate_table *rate_table;
  47         unsigned int            rate_count;
  48         spinlock_t              *lock;
  49
  50         struct rockchip_clk_provider *ctx;
  51 };
  52
  53 #define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw)
  54 #define to_rockchip_clk_pll_nb(nb) \
  55                         container_of(nb, struct rockchip_clk_pll, clk_nb)
  56
  57 static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
  58                             struct rockchip_clk_pll *pll, unsigned long rate)
  59 {
  60         const struct rockchip_pll_rate_table  *rate_table = pll->rate_table;
  61         int i;
  62
  63         for (i = 0; i < pll->rate_count; i++) {
  64                 if (rate == rate_table[i].rate)
  65                         return &rate_table[i];
  66         }
  67
  68         return NULL;
  69 }
  70
  71 static long rockchip_pll_round_rate(struct clk_hw *hw,
  72                             unsigned long drate, unsigned long *prate)
  73 {
  74         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
  75         const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
  76         int i;
  77
  78         /* Assumming rate_table is in descending order */
  79         for (i = 0; i < pll->rate_count; i++) {
  80                 if (drate >= rate_table[i].rate)
  81                         return rate_table[i].rate;
  82         }
  83
  84         /* return minimum supported value */
  85         return rate_table[i - 1].rate;
  86 }
  87
  88 /*
  89  * Wait for the pll to reach the locked state.
  90  * The calling set_rate function is responsible for making sure the
  91  * grf regmap is available.
  92  */
  93 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
  94 {
  95         struct regmap *grf = pll->ctx->grf;
  96         unsigned int val;
  97         int delay = 24000000, ret;
  98
  99         while (delay > 0) {
 100                 ret = regmap_read(grf, pll->lock_offset, &val);
 101                 if (ret) {
 102                         pr_err("%s: failed to read pll lock status: %d\n",
 103                                __func__, ret);
 104                         return ret;
 105                 }
 106
 107                 if (val & BIT(pll->lock_shift))
 108                         return 0;
 109                 delay--;
 110         }
 111
 112         pr_err("%s: timeout waiting for pll to lock\n", __func__);
 113         return -ETIMEDOUT;
 114 }
 115
 116 /**
 117  * PLL used in RK3036
 118  */
 119
 120 #define RK3036_PLLCON(i)                        (i * 0x4)
 121 #define RK3036_PLLCON0_FBDIV_MASK               0xfff
 122 #define RK3036_PLLCON0_FBDIV_SHIFT              0
 123 #define RK3036_PLLCON0_POSTDIV1_MASK            0x7
 124 #define RK3036_PLLCON0_POSTDIV1_SHIFT           12
 125 #define RK3036_PLLCON1_REFDIV_MASK              0x3f
 126 #define RK3036_PLLCON1_REFDIV_SHIFT             0
 127 #define RK3036_PLLCON1_POSTDIV2_MASK            0x7
 128 #define RK3036_PLLCON1_POSTDIV2_SHIFT           6
 129 #define RK3036_PLLCON1_DSMPD_MASK               0x1
 130 #define RK3036_PLLCON1_DSMPD_SHIFT              12
 131 #define RK3036_PLLCON2_FRAC_MASK                0xffffff
 132 #define RK3036_PLLCON2_FRAC_SHIFT               0
 133
 134 #define RK3036_PLLCON1_PWRDOWN                  (1 << 13)
 135
 136 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
 137                                         struct rockchip_pll_rate_table *rate)
 138 {
 139         u32 pllcon;
 140
 141         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
 142         rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT)
 143                                 & RK3036_PLLCON0_FBDIV_MASK);
 144         rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT)
 145                                 & RK3036_PLLCON0_POSTDIV1_MASK);
 146
 147         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
 148         rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT)
 149                                 & RK3036_PLLCON1_REFDIV_MASK);
 150         rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT)
 151                                 & RK3036_PLLCON1_POSTDIV2_MASK);
 152         rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT)
 153                                 & RK3036_PLLCON1_DSMPD_MASK);
 154
 155         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
 156         rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT)
 157                                 & RK3036_PLLCON2_FRAC_MASK);
 158 }
 159
 160 static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
 161                                                      unsigned long prate)
 162 {
 163         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 164         struct rockchip_pll_rate_table cur;
 165         u64 rate64 = prate;
 166
 167         rockchip_rk3036_pll_get_params(pll, &cur);
 168
 169         rate64 *= cur.fbdiv;
 170         do_div(rate64, cur.refdiv);
 171
 172         if (cur.dsmpd == 0) {
 173                 /* fractional mode */
 174                 u64 frac_rate64 = prate * cur.frac;
 175
 176                 do_div(frac_rate64, cur.refdiv);
 177                 rate64 += frac_rate64 >> 24;
 178         }
 179
 180         do_div(rate64, cur.postdiv1);
 181         do_div(rate64, cur.postdiv2);
 182
 183         return (unsigned long)rate64;
 184 }
 185
 186 static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
 187                                 const struct rockchip_pll_rate_table *rate)
 188 {
 189         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
 190         struct clk_mux *pll_mux = &pll->pll_mux;
 191         struct rockchip_pll_rate_table cur;
 192         u32 pllcon;
 193         int rate_change_remuxed = 0;
 194         int cur_parent;
 195         int ret;
 196
 197         pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 198                 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
 199                 rate->postdiv2, rate->dsmpd, rate->frac);
 200
 201         rockchip_rk3036_pll_get_params(pll, &cur);
 202         cur.rate = 0;
 203
 204         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 205         if (cur_parent == PLL_MODE_NORM) {
 206                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 207                 rate_change_remuxed = 1;
 208         }
 209
 210         /* update pll values */
 211         writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
 212                                           RK3036_PLLCON0_FBDIV_SHIFT) |
 213                        HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK,
 214                                              RK3036_PLLCON0_POSTDIV1_SHIFT),
 215                        pll->reg_base + RK3036_PLLCON(0));
 216
 217         writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK,
 218                                                    RK3036_PLLCON1_REFDIV_SHIFT) |
 219                        HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK,
 220                                                      RK3036_PLLCON1_POSTDIV2_SHIFT) |
 221                        HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK,
 222                                                   RK3036_PLLCON1_DSMPD_SHIFT),
 223                        pll->reg_base + RK3036_PLLCON(1));
 224
 225         /* GPLL CON2 is not HIWORD_MASK */
 226         pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
 227         pllcon &= ~(RK3036_PLLCON2_FRAC_MASK << RK3036_PLLCON2_FRAC_SHIFT);
 228         pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
 229         writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
 230
 231         /* wait for the pll to lock */
 232         ret = rockchip_pll_wait_lock(pll);
 233         if (ret) {
 234                 pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
 235                         __func__);
 236                 rockchip_rk3036_pll_set_params(pll, &cur);
 237         }
 238
 239         if (rate_change_remuxed)
 240                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 241
 242         return ret;
 243 }
 244
 245 static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 246                                         unsigned long prate)
 247 {
 248         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 249         const struct rockchip_pll_rate_table *rate;
 250         unsigned long old_rate = rockchip_rk3036_pll_recalc_rate(hw, prate);
 251
 252         pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
 253                  __func__, __clk_get_name(hw->clk), old_rate, drate, prate);
 254
 255         /* Get required rate settings from table */
 256         rate = rockchip_get_pll_settings(pll, drate);
 257         if (!rate) {
 258                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 259                         drate, __clk_get_name(hw->clk));
 260                 return -EINVAL;
 261         }
 262
 263         return rockchip_rk3036_pll_set_params(pll, rate);
 264 }
 265
 266 static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
 267 {
 268         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 269
 270         writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
 271                pll->reg_base + RK3036_PLLCON(1));
 272
 273         return 0;
 274 }
 275
 276 static void rockchip_rk3036_pll_disable(struct clk_hw *hw)
 277 {
 278         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 279
 280         writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
 281                              RK3036_PLLCON1_PWRDOWN, 0),
 282                pll->reg_base + RK3036_PLLCON(1));
 283 }
 284
 285 static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw)
 286 {
 287         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 288         u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));
 289
 290         return !(pllcon & RK3036_PLLCON1_PWRDOWN);
 291 }
 292
 293 static void rockchip_rk3036_pll_init(struct clk_hw *hw)
 294 {
 295         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 296         const struct rockchip_pll_rate_table *rate;
 297         struct rockchip_pll_rate_table cur;
 298         unsigned long drate;
 299
 300         if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
 301                 return;
 302
 303         drate = clk_hw_get_rate(hw);
 304         rate = rockchip_get_pll_settings(pll, drate);
 305
 306         /* when no rate setting for the current rate, rely on clk_set_rate */
 307         if (!rate)
 308                 return;
 309
 310         rockchip_rk3036_pll_get_params(pll, &cur);
 311
 312         pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
 313                  drate);
 314         pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 315                  cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
 316                  cur.dsmpd, cur.frac);
 317         pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 318                  rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
 319                  rate->dsmpd, rate->frac);
 320
 321         if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
 322                 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
 323                 rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) {
 324                 struct clk *parent = clk_get_parent(hw->clk);
 325
 326                 if (!parent) {
 327                         pr_warn("%s: parent of %s not available\n",
 328                                 __func__, __clk_get_name(hw->clk));
 329                         return;
 330                 }
 331
 332                 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
 333                          __func__, __clk_get_name(hw->clk));
 334                 rockchip_rk3036_pll_set_params(pll, rate);
 335         }
 336 }
 337
 338 static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = {
 339         .recalc_rate = rockchip_rk3036_pll_recalc_rate,
 340         .enable = rockchip_rk3036_pll_enable,
 341         .disable = rockchip_rk3036_pll_disable,
 342         .is_enabled = rockchip_rk3036_pll_is_enabled,
 343 };
 344
 345 static const struct clk_ops rockchip_rk3036_pll_clk_ops = {
 346         .recalc_rate = rockchip_rk3036_pll_recalc_rate,
 347         .round_rate = rockchip_pll_round_rate,
 348         .set_rate = rockchip_rk3036_pll_set_rate,
 349         .enable = rockchip_rk3036_pll_enable,
 350         .disable = rockchip_rk3036_pll_disable,
 351         .is_enabled = rockchip_rk3036_pll_is_enabled,
 352         .init = rockchip_rk3036_pll_init,
 353 };
 354
 355 /**
 356  * PLL used in RK3066, RK3188 and RK3288
 357  */
 358
 359 #define RK3066_PLL_RESET_DELAY(nr)      ((nr * 500) / 24 + 1)
 360
 361 #define RK3066_PLLCON(i)                (i * 0x4)
 362 #define RK3066_PLLCON0_OD_MASK          0xf
 363 #define RK3066_PLLCON0_OD_SHIFT         0
 364 #define RK3066_PLLCON0_NR_MASK          0x3f
 365 #define RK3066_PLLCON0_NR_SHIFT         8
 366 #define RK3066_PLLCON1_NF_MASK          0x1fff
 367 #define RK3066_PLLCON1_NF_SHIFT         0
 368 #define RK3066_PLLCON2_NB_MASK          0xfff
 369 #define RK3066_PLLCON2_NB_SHIFT         0
 370 #define RK3066_PLLCON3_RESET            (1 << 5)
 371 #define RK3066_PLLCON3_PWRDOWN          (1 << 1)
 372 #define RK3066_PLLCON3_BYPASS           (1 << 0)
 373
 374 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll,
 375                                         struct rockchip_pll_rate_table *rate)
 376 {
 377         u32 pllcon;
 378
 379         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
 380         rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT)
 381                                 & RK3066_PLLCON0_NR_MASK) + 1;
 382         rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT)
 383                                 & RK3066_PLLCON0_OD_MASK) + 1;
 384
 385         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
 386         rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT)
 387                                 & RK3066_PLLCON1_NF_MASK) + 1;
 388
 389         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
 390         rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT)
 391                                 & RK3066_PLLCON2_NB_MASK) + 1;
 392 }
 393
 394 static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw,
 395                                                      unsigned long prate)
 396 {
 397         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 398         struct rockchip_pll_rate_table cur;
 399         u64 rate64 = prate;
 400         u32 pllcon;
 401
 402         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
 403         if (pllcon & RK3066_PLLCON3_BYPASS) {
 404                 pr_debug("%s: pll %s is bypassed\n", __func__,
 405                         clk_hw_get_name(hw));
 406                 return prate;
 407         }
 408
 409         rockchip_rk3066_pll_get_params(pll, &cur);
 410
 411         rate64 *= cur.nf;
 412         do_div(rate64, cur.nr);
 413         do_div(rate64, cur.no);
 414
 415         return (unsigned long)rate64;
 416 }
 417
 418 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll,
 419                                 const struct rockchip_pll_rate_table *rate)
 420 {
 421         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
 422         struct clk_mux *pll_mux = &pll->pll_mux;
 423         struct rockchip_pll_rate_table cur;
 424         int rate_change_remuxed = 0;
 425         int cur_parent;
 426         int ret;
 427
 428         pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n",
 429                  __func__, rate->rate, rate->nr, rate->no, rate->nf);
 430
 431         rockchip_rk3066_pll_get_params(pll, &cur);
 432         cur.rate = 0;
 433
 434         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 435         if (cur_parent == PLL_MODE_NORM) {
 436                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 437                 rate_change_remuxed = 1;
 438         }
 439
 440         /* enter reset mode */
 441         writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0),
 442                pll->reg_base + RK3066_PLLCON(3));
 443
 444         /* update pll values */
 445         writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
 446                                            RK3066_PLLCON0_NR_SHIFT) |
 447                HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK,
 448                                            RK3066_PLLCON0_OD_SHIFT),
 449                pll->reg_base + RK3066_PLLCON(0));
 450
 451         writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
 452                                                    RK3066_PLLCON1_NF_SHIFT),
 453                        pll->reg_base + RK3066_PLLCON(1));
 454         writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK,
 455                                                    RK3066_PLLCON2_NB_SHIFT),
 456                        pll->reg_base + RK3066_PLLCON(2));
 457
 458         /* leave reset and wait the reset_delay */
 459         writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0),
 460                pll->reg_base + RK3066_PLLCON(3));
 461         udelay(RK3066_PLL_RESET_DELAY(rate->nr));
 462
 463         /* wait for the pll to lock */
 464         ret = rockchip_pll_wait_lock(pll);
 465         if (ret) {
 466                 pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
 467                         __func__);
 468                 rockchip_rk3066_pll_set_params(pll, &cur);
 469         }
 470
 471         if (rate_change_remuxed)
 472                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 473
 474         return ret;
 475 }
 476
 477 static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 478                                         unsigned long prate)
 479 {
 480         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 481         const struct rockchip_pll_rate_table *rate;
 482         unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate);
 483
 484         pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
 485                  __func__, clk_hw_get_name(hw), old_rate, drate, prate);
 486
 487         /* Get required rate settings from table */
 488         rate = rockchip_get_pll_settings(pll, drate);
 489         if (!rate) {
 490                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 491                         drate, clk_hw_get_name(hw));
 492                 return -EINVAL;
 493         }
 494
 495         return rockchip_rk3066_pll_set_params(pll, rate);
 496 }
 497
 498 static int rockchip_rk3066_pll_enable(struct clk_hw *hw)
 499 {
 500         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 501
 502         writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),
 503                pll->reg_base + RK3066_PLLCON(3));
 504
 505         return 0;
 506 }
 507
 508 static void rockchip_rk3066_pll_disable(struct clk_hw *hw)
 509 {
 510         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 511
 512         writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN,
 513                              RK3066_PLLCON3_PWRDOWN, 0),
 514                pll->reg_base + RK3066_PLLCON(3));
 515 }
 516
 517 static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw)
 518 {
 519         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 520         u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
 521
 522         return !(pllcon & RK3066_PLLCON3_PWRDOWN);
 523 }
 524
 525 static void rockchip_rk3066_pll_init(struct clk_hw *hw)
 526 {
 527         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 528         const struct rockchip_pll_rate_table *rate;
 529         struct rockchip_pll_rate_table cur;
 530         unsigned long drate;
 531
 532         if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
 533                 return;
 534
 535         drate = clk_hw_get_rate(hw);
 536         rate = rockchip_get_pll_settings(pll, drate);
 537
 538         /* when no rate setting for the current rate, rely on clk_set_rate */
 539         if (!rate)
 540                 return;
 541
 542         rockchip_rk3066_pll_get_params(pll, &cur);
 543
 544         pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n",
 545                  __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr,
 546                  rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb);
 547         if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf
 548                                                      || rate->nb != cur.nb) {
 549                 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
 550                          __func__, clk_hw_get_name(hw));
 551                 rockchip_rk3066_pll_set_params(pll, rate);
 552         }
 553 }
 554
 555 static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = {
 556         .recalc_rate = rockchip_rk3066_pll_recalc_rate,
 557         .enable = rockchip_rk3066_pll_enable,
 558         .disable = rockchip_rk3066_pll_disable,
 559         .is_enabled = rockchip_rk3066_pll_is_enabled,
 560 };
 561
 562 static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
 563         .recalc_rate = rockchip_rk3066_pll_recalc_rate,
 564         .round_rate = rockchip_pll_round_rate,
 565         .set_rate = rockchip_rk3066_pll_set_rate,
 566         .enable = rockchip_rk3066_pll_enable,
 567         .disable = rockchip_rk3066_pll_disable,
 568         .is_enabled = rockchip_rk3066_pll_is_enabled,
 569         .init = rockchip_rk3066_pll_init,
 570 };
 571
 572 /**
 573  * PLL used in RK3399
 574  */
 575
 576 #define RK3399_PLLCON(i)                        (i * 0x4)
 577 #define RK3399_PLLCON0_FBDIV_MASK               0xfff
 578 #define RK3399_PLLCON0_FBDIV_SHIFT              0
 579 #define RK3399_PLLCON1_REFDIV_MASK              0x3f
 580 #define RK3399_PLLCON1_REFDIV_SHIFT             0
 581 #define RK3399_PLLCON1_POSTDIV1_MASK            0x7
 582 #define RK3399_PLLCON1_POSTDIV1_SHIFT           8
 583 #define RK3399_PLLCON1_POSTDIV2_MASK            0x7
 584 #define RK3399_PLLCON1_POSTDIV2_SHIFT           12
 585 #define RK3399_PLLCON2_FRAC_MASK                0xffffff
 586 #define RK3399_PLLCON2_FRAC_SHIFT               0
 587 #define RK3399_PLLCON2_LOCK_STATUS              BIT(31)
 588 #define RK3399_PLLCON3_PWRDOWN                  BIT(0)
 589 #define RK3399_PLLCON3_DSMPD_MASK               0x1
 590 #define RK3399_PLLCON3_DSMPD_SHIFT              3
 591
 592 static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll)
 593 {
 594         u32 pllcon;
 595         int delay = 24000000;
 596
 597         /* poll check the lock status in rk3399 xPLLCON2 */
 598         while (delay > 0) {
 599                 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
 600                 if (pllcon & RK3399_PLLCON2_LOCK_STATUS)
 601                         return 0;
 602
 603                 delay--;
 604         }
 605
 606         pr_err("%s: timeout waiting for pll to lock\n", __func__);
 607         return -ETIMEDOUT;
 608 }
 609
 610 static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll,
 611                                         struct rockchip_pll_rate_table *rate)
 612 {
 613         u32 pllcon;
 614
 615         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0));
 616         rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT)
 617                                 & RK3399_PLLCON0_FBDIV_MASK);
 618
 619         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1));
 620         rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT)
 621                                 & RK3399_PLLCON1_REFDIV_MASK);
 622         rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT)
 623                                 & RK3399_PLLCON1_POSTDIV1_MASK);
 624         rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT)
 625                                 & RK3399_PLLCON1_POSTDIV2_MASK);
 626
 627         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
 628         rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT)
 629                                 & RK3399_PLLCON2_FRAC_MASK);
 630
 631         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3));
 632         rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT)
 633                                 & RK3399_PLLCON3_DSMPD_MASK);
 634 }
 635
 636 static unsigned long rockchip_rk3399_pll_recalc_rate(struct clk_hw *hw,
 637                                                      unsigned long prate)
 638 {
 639         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 640         struct rockchip_pll_rate_table cur;
 641         u64 rate64 = prate;
 642
 643         rockchip_rk3399_pll_get_params(pll, &cur);
 644
 645         rate64 *= cur.fbdiv;
 646         do_div(rate64, cur.refdiv);
 647
 648         if (cur.dsmpd == 0) {
 649                 /* fractional mode */
 650                 u64 frac_rate64 = prate * cur.frac;
 651
 652                 do_div(frac_rate64, cur.refdiv);
 653                 rate64 += frac_rate64 >> 24;
 654         }
 655
 656         do_div(rate64, cur.postdiv1);
 657         do_div(rate64, cur.postdiv2);
 658
 659         return (unsigned long)rate64;
 660 }
 661
 662 static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,
 663                                 const struct rockchip_pll_rate_table *rate)
 664 {
 665         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
 666         struct clk_mux *pll_mux = &pll->pll_mux;
 667         struct rockchip_pll_rate_table cur;
 668         u32 pllcon;
 669         int rate_change_remuxed = 0;
 670         int cur_parent;
 671         int ret;
 672
 673         pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 674                 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
 675                 rate->postdiv2, rate->dsmpd, rate->frac);
 676
 677         rockchip_rk3399_pll_get_params(pll, &cur);
 678         cur.rate = 0;
 679
 680         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 681         if (cur_parent == PLL_MODE_NORM) {
 682                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 683                 rate_change_remuxed = 1;
 684         }
 685
 686         /* update pll values */
 687         writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
 688                                                   RK3399_PLLCON0_FBDIV_SHIFT),
 689                        pll->reg_base + RK3399_PLLCON(0));
 690
 691         writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK,
 692                                                    RK3399_PLLCON1_REFDIV_SHIFT) |
 693                        HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK,
 694                                                      RK3399_PLLCON1_POSTDIV1_SHIFT) |
 695                        HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK,
 696                                                      RK3399_PLLCON1_POSTDIV2_SHIFT),
 697                        pll->reg_base + RK3399_PLLCON(1));
 698
 699         /* xPLL CON2 is not HIWORD_MASK */
 700         pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
 701         pllcon &= ~(RK3399_PLLCON2_FRAC_MASK << RK3399_PLLCON2_FRAC_SHIFT);
 702         pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT;
 703         writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2));
 704
 705         writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK,
 706                                             RK3399_PLLCON3_DSMPD_SHIFT),
 707                        pll->reg_base + RK3399_PLLCON(3));
 708
 709         /* wait for the pll to lock */
 710         ret = rockchip_rk3399_pll_wait_lock(pll);
 711         if (ret) {
 712                 pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
 713                         __func__);
 714                 rockchip_rk3399_pll_set_params(pll, &cur);
 715         }
 716
 717         if (rate_change_remuxed)
 718                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 719
 720         return ret;
 721 }
 722
 723 static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 724                                         unsigned long prate)
 725 {
 726         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 727         const struct rockchip_pll_rate_table *rate;
 728         unsigned long old_rate = rockchip_rk3399_pll_recalc_rate(hw, prate);
 729
 730         pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
 731                  __func__, __clk_get_name(hw->clk), old_rate, drate, prate);
 732
 733         /* Get required rate settings from table */
 734         rate = rockchip_get_pll_settings(pll, drate);
 735         if (!rate) {
 736                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 737                         drate, __clk_get_name(hw->clk));
 738                 return -EINVAL;
 739         }
 740
 741         return rockchip_rk3399_pll_set_params(pll, rate);
 742 }
 743
 744 static int rockchip_rk3399_pll_enable(struct clk_hw *hw)
 745 {
 746         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 747
 748         writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0),
 749                pll->reg_base + RK3399_PLLCON(3));
 750
 751         return 0;
 752 }
 753
 754 static void rockchip_rk3399_pll_disable(struct clk_hw *hw)
 755 {
 756         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 757
 758         writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
 759                              RK3399_PLLCON3_PWRDOWN, 0),
 760                pll->reg_base + RK3399_PLLCON(3));
 761 }
 762
 763 static int rockchip_rk3399_pll_is_enabled(struct clk_hw *hw)
 764 {
 765         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 766         u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3));
 767
 768         return !(pllcon & RK3399_PLLCON3_PWRDOWN);
 769 }
 770
 771 static void rockchip_rk3399_pll_init(struct clk_hw *hw)
 772 {
 773         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 774         const struct rockchip_pll_rate_table *rate;
 775         struct rockchip_pll_rate_table cur;
 776         unsigned long drate;
 777
 778         if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
 779                 return;
 780
 781         drate = clk_hw_get_rate(hw);
 782         rate = rockchip_get_pll_settings(pll, drate);
 783
 784         /* when no rate setting for the current rate, rely on clk_set_rate */
 785         if (!rate)
 786                 return;
 787
 788         rockchip_rk3399_pll_get_params(pll, &cur);
 789
 790         pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
 791                  drate);
 792         pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 793                  cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
 794                  cur.dsmpd, cur.frac);
 795         pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
 796                  rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
 797                  rate->dsmpd, rate->frac);
 798
 799         if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
 800                 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
 801                 rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) {
 802                 struct clk *parent = clk_get_parent(hw->clk);
 803
 804                 if (!parent) {
 805                         pr_warn("%s: parent of %s not available\n",
 806                                 __func__, __clk_get_name(hw->clk));
 807                         return;
 808                 }
 809
 810                 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
 811                          __func__, __clk_get_name(hw->clk));
 812                 rockchip_rk3399_pll_set_params(pll, rate);
 813         }
 814 }
 815
 816 static const struct clk_ops rockchip_rk3399_pll_clk_norate_ops = {
 817         .recalc_rate = rockchip_rk3399_pll_recalc_rate,
 818         .enable = rockchip_rk3399_pll_enable,
 819         .disable = rockchip_rk3399_pll_disable,
 820         .is_enabled = rockchip_rk3399_pll_is_enabled,
 821 };
 822
 823 static const struct clk_ops rockchip_rk3399_pll_clk_ops = {
 824         .recalc_rate = rockchip_rk3399_pll_recalc_rate,
 825         .round_rate = rockchip_pll_round_rate,
 826         .set_rate = rockchip_rk3399_pll_set_rate,
 827         .enable = rockchip_rk3399_pll_enable,
 828         .disable = rockchip_rk3399_pll_disable,
 829         .is_enabled = rockchip_rk3399_pll_is_enabled,
 830         .init = rockchip_rk3399_pll_init,
 831 };
 832
 833 /*
 834  * Common registering of pll clocks
 835  */
 836
 837 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
 838                 enum rockchip_pll_type pll_type,
 839                 const char *name, const char *const *parent_names,
 840                 u8 num_parents, int con_offset, int grf_lock_offset,
 841                 int lock_shift, int mode_offset, int mode_shift,
 842                 struct rockchip_pll_rate_table *rate_table,
 843                 u8 clk_pll_flags)
 844 {
 845         const char *pll_parents[3];
 846         struct clk_init_data init;
 847         struct rockchip_clk_pll *pll;
 848         struct clk_mux *pll_mux;
 849         struct clk *pll_clk, *mux_clk;
 850         char pll_name[20];
 851
 852         if (num_parents != 2) {
 853                 pr_err("%s: needs two parent clocks\n", __func__);
 854                 return ERR_PTR(-EINVAL);
 855         }
 856
 857         /* name the actual pll */
 858         snprintf(pll_name, sizeof(pll_name), "pll_%s", name);
 859
 860         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 861         if (!pll)
 862                 return ERR_PTR(-ENOMEM);
 863
 864         /* create the mux on top of the real pll */
 865         pll->pll_mux_ops = &clk_mux_ops;
 866         pll_mux = &pll->pll_mux;
 867         pll_mux->reg = ctx->reg_base + mode_offset;
 868         pll_mux->shift = mode_shift;
 869         pll_mux->mask = PLL_MODE_MASK;
 870         pll_mux->flags = 0;
 871         pll_mux->lock = &ctx->lock;
 872         pll_mux->hw.init = &init;
 873
 874         if (pll_type == pll_rk3036 ||
 875             pll_type == pll_rk3066 ||
 876             pll_type == pll_rk3399)
 877                 pll_mux->flags |= CLK_MUX_HIWORD_MASK;
 878
 879         /* the actual muxing is xin24m, pll-output, xin32k */
 880         pll_parents[0] = parent_names[0];
 881         pll_parents[1] = pll_name;
 882         pll_parents[2] = parent_names[1];
 883
 884         init.name = name;
 885         init.flags = CLK_SET_RATE_PARENT;
 886         init.ops = pll->pll_mux_ops;
 887         init.parent_names = pll_parents;
 888         init.num_parents = ARRAY_SIZE(pll_parents);
 889
 890         mux_clk = clk_register(NULL, &pll_mux->hw);
 891         if (IS_ERR(mux_clk))
 892                 goto err_mux;
 893
 894         /* now create the actual pll */
 895         init.name = pll_name;
 896
 897         /* keep all plls untouched for now */
 898         init.flags = CLK_IGNORE_UNUSED;
 899
 900         init.parent_names = &parent_names[0];
 901         init.num_parents = 1;
 902
 903         if (rate_table) {
 904                 int len;
 905
 906                 /* find count of rates in rate_table */
 907                 for (len = 0; rate_table[len].rate != 0; )
 908                         len++;
 909
 910                 pll->rate_count = len;
 911                 pll->rate_table = kmemdup(rate_table,
 912                                         pll->rate_count *
 913                                         sizeof(struct rockchip_pll_rate_table),
 914                                         GFP_KERNEL);
 915                 WARN(!pll->rate_table,
 916                         "%s: could not allocate rate table for %s\n",
 917                         __func__, name);
 918         }
 919
 920         switch (pll_type) {
 921         case pll_rk3036:
 922                 if (!pll->rate_table || IS_ERR(ctx->grf))
 923                         init.ops = &rockchip_rk3036_pll_clk_norate_ops;
 924                 else
 925                         init.ops = &rockchip_rk3036_pll_clk_ops;
 926                 break;
 927         case pll_rk3066:
 928                 if (!pll->rate_table || IS_ERR(ctx->grf))
 929                         init.ops = &rockchip_rk3066_pll_clk_norate_ops;
 930                 else
 931                         init.ops = &rockchip_rk3066_pll_clk_ops;
 932                 break;
 933         case pll_rk3399:
 934                 if (!pll->rate_table)
 935                         init.ops = &rockchip_rk3399_pll_clk_norate_ops;
 936                 else
 937                         init.ops = &rockchip_rk3399_pll_clk_ops;
 938                 break;
 939         default:
 940                 pr_warn("%s: Unknown pll type for pll clk %s\n",
 941                         __func__, name);
 942         }
 943
 944         pll->hw.init = &init;
 945         pll->type = pll_type;
 946         pll->reg_base = ctx->reg_base + con_offset;
 947         pll->lock_offset = grf_lock_offset;
 948         pll->lock_shift = lock_shift;
 949         pll->flags = clk_pll_flags;
 950         pll->lock = &ctx->lock;
 951         pll->ctx = ctx;
 952
 953         pll_clk = clk_register(NULL, &pll->hw);
 954         if (IS_ERR(pll_clk)) {
 955                 pr_err("%s: failed to register pll clock %s : %ld\n",
 956                         __func__, name, PTR_ERR(pll_clk));
 957                 goto err_pll;
 958         }
 959
 960         return mux_clk;
 961
 962 err_pll:
 963         clk_unregister(mux_clk);
 964         mux_clk = pll_clk;
 965 err_mux:
 966         kfree(pll);
 967         return mux_clk;
 968 }