2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
8 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
9 * Copyright (c) 2013 Linaro Ltd.
10 * Author: Thomas Abraham <thomas.ab@samsung.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
23 #include <linux/slab.h>
24 #include <linux/clk.h>
25 #include <linux/clk-provider.h>
26 #include <linux/mfd/syscon.h>
27 #include <linux/regmap.h>
28 #include <linux/reboot.h>
32 * Register a clock branch.
33 * Most clock branches have a form like
39 * sometimes without one of those components.
41 static struct clk *rockchip_clk_register_branch(const char *name,
42 const char *const *parent_names, u8 num_parents, void __iomem *base,
43 int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
44 u8 div_shift, u8 div_width, u8 div_flags,
45 struct clk_div_table *div_table, int gate_offset,
46 u8 gate_shift, u8 gate_flags, unsigned long flags,
50 struct clk_mux *mux = NULL;
51 struct clk_gate *gate = NULL;
52 struct clk_divider *div = NULL;
53 const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
56 if (num_parents > 1) {
57 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
59 return ERR_PTR(-ENOMEM);
61 mux->reg = base + muxdiv_offset;
62 mux->shift = mux_shift;
63 mux->mask = BIT(mux_width) - 1;
64 mux->flags = mux_flags;
66 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
70 if (gate_offset >= 0) {
71 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
75 gate->flags = gate_flags;
76 gate->reg = base + gate_offset;
77 gate->bit_idx = gate_shift;
79 gate_ops = &clk_gate_ops;
83 div = kzalloc(sizeof(*div), GFP_KERNEL);
87 div->flags = div_flags;
88 div->reg = base + muxdiv_offset;
89 div->shift = div_shift;
90 div->width = div_width;
92 div->table = div_table;
93 div_ops = &clk_divider_ops;
96 clk = clk_register_composite(NULL, name, parent_names, num_parents,
97 mux ? &mux->hw : NULL, mux_ops,
98 div ? &div->hw : NULL, div_ops,
99 gate ? &gate->hw : NULL, gate_ops,
107 return ERR_PTR(-ENOMEM);
110 struct rockchip_clk_frac {
111 struct notifier_block clk_nb;
112 struct clk_fractional_divider div;
113 struct clk_gate gate;
116 const struct clk_ops *mux_ops;
119 bool rate_change_remuxed;
123 #define to_rockchip_clk_frac_nb(nb) \
124 container_of(nb, struct rockchip_clk_frac, clk_nb)
126 static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
127 unsigned long event, void *data)
129 struct clk_notifier_data *ndata = data;
130 struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb);
131 struct clk_mux *frac_mux = &frac->mux;
134 pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
135 __func__, event, ndata->old_rate, ndata->new_rate);
136 if (event == PRE_RATE_CHANGE) {
137 frac->rate_change_idx = frac->mux_ops->get_parent(&frac_mux->hw);
138 if (frac->rate_change_idx != frac->mux_frac_idx) {
139 frac->mux_ops->set_parent(&frac_mux->hw, frac->mux_frac_idx);
140 frac->rate_change_remuxed = 1;
142 } else if (event == POST_RATE_CHANGE) {
144 * The POST_RATE_CHANGE notifier runs directly after the
145 * divider clock is set in clk_change_rate, so we'll have
146 * remuxed back to the original parent before clk_change_rate
147 * reaches the mux itself.
149 if (frac->rate_change_remuxed) {
150 frac->mux_ops->set_parent(&frac_mux->hw, frac->rate_change_idx);
151 frac->rate_change_remuxed = 0;
155 return notifier_from_errno(ret);
158 static struct clk *rockchip_clk_register_frac_branch(const char *name,
159 const char *const *parent_names, u8 num_parents,
160 void __iomem *base, int muxdiv_offset, u8 div_flags,
161 int gate_offset, u8 gate_shift, u8 gate_flags,
162 unsigned long flags, struct rockchip_clk_branch *child,
165 struct rockchip_clk_frac *frac;
167 struct clk_gate *gate = NULL;
168 struct clk_fractional_divider *div = NULL;
169 const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
171 if (muxdiv_offset < 0)
172 return ERR_PTR(-EINVAL);
174 if (child && child->branch_type != branch_mux) {
175 pr_err("%s: fractional child clock for %s can only be a mux\n",
177 return ERR_PTR(-EINVAL);
180 frac = kzalloc(sizeof(*frac), GFP_KERNEL);
182 return ERR_PTR(-ENOMEM);
184 if (gate_offset >= 0) {
186 gate->flags = gate_flags;
187 gate->reg = base + gate_offset;
188 gate->bit_idx = gate_shift;
190 gate_ops = &clk_gate_ops;
194 div->flags = div_flags;
195 div->reg = base + muxdiv_offset;
198 div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift;
201 div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
203 div_ops = &clk_fractional_divider_ops;
205 clk = clk_register_composite(NULL, name, parent_names, num_parents,
208 gate ? &gate->hw : NULL, gate_ops,
209 flags | CLK_SET_RATE_UNGATE);
216 struct clk_mux *frac_mux = &frac->mux;
217 struct clk_init_data init;
221 frac->mux_frac_idx = -1;
222 for (i = 0; i < child->num_parents; i++) {
223 if (!strcmp(name, child->parent_names[i])) {
224 pr_debug("%s: found fractional parent in mux at pos %d\n",
226 frac->mux_frac_idx = i;
231 frac->mux_ops = &clk_mux_ops;
232 frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb;
234 frac_mux->reg = base + child->muxdiv_offset;
235 frac_mux->shift = child->mux_shift;
236 frac_mux->mask = BIT(child->mux_width) - 1;
237 frac_mux->flags = child->mux_flags;
238 frac_mux->lock = lock;
239 frac_mux->hw.init = &init;
241 init.name = child->name;
242 init.flags = child->flags | CLK_SET_RATE_PARENT;
243 init.ops = frac->mux_ops;
244 init.parent_names = child->parent_names;
245 init.num_parents = child->num_parents;
247 mux_clk = clk_register(NULL, &frac_mux->hw);
251 rockchip_clk_add_lookup(mux_clk, child->id);
253 /* notifier on the fraction divider to catch rate changes */
254 if (frac->mux_frac_idx >= 0) {
255 ret = clk_notifier_register(clk, &frac->clk_nb);
257 pr_err("%s: failed to register clock notifier for %s\n",
260 pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n",
261 __func__, name, child->name);
268 static struct clk *rockchip_clk_register_factor_branch(const char *name,
269 const char *const *parent_names, u8 num_parents,
270 void __iomem *base, unsigned int mult, unsigned int div,
271 int gate_offset, u8 gate_shift, u8 gate_flags,
272 unsigned long flags, spinlock_t *lock)
275 struct clk_gate *gate = NULL;
276 struct clk_fixed_factor *fix = NULL;
278 /* without gate, register a simple factor clock */
279 if (gate_offset == 0) {
280 return clk_register_fixed_factor(NULL, name,
281 parent_names[0], flags, mult,
285 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
287 return ERR_PTR(-ENOMEM);
289 gate->flags = gate_flags;
290 gate->reg = base + gate_offset;
291 gate->bit_idx = gate_shift;
294 fix = kzalloc(sizeof(*fix), GFP_KERNEL);
297 return ERR_PTR(-ENOMEM);
303 clk = clk_register_composite(NULL, name, parent_names, num_parents,
305 &fix->hw, &clk_fixed_factor_ops,
306 &gate->hw, &clk_gate_ops, flags);
315 static DEFINE_SPINLOCK(clk_lock);
316 static struct clk **clk_table;
317 static void __iomem *reg_base;
318 static struct clk_onecell_data clk_data;
319 static struct device_node *cru_node;
320 static struct regmap *grf;
322 void __init rockchip_clk_init(struct device_node *np, void __iomem *base,
323 unsigned long nr_clks)
327 grf = ERR_PTR(-EPROBE_DEFER);
329 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
331 pr_err("%s: could not allocate clock lookup table\n", __func__);
333 clk_data.clks = clk_table;
334 clk_data.clk_num = nr_clks;
335 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
338 struct regmap *rockchip_clk_get_grf(void)
341 grf = syscon_regmap_lookup_by_phandle(cru_node, "rockchip,grf");
345 void rockchip_clk_add_lookup(struct clk *clk, unsigned int id)
351 void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list,
352 unsigned int nr_pll, int grf_lock_offset)
357 for (idx = 0; idx < nr_pll; idx++, list++) {
358 clk = rockchip_clk_register_pll(list->type, list->name,
359 list->parent_names, list->num_parents,
360 reg_base, list->con_offset, grf_lock_offset,
361 list->lock_shift, list->mode_offset,
362 list->mode_shift, list->rate_table,
363 list->pll_flags, &clk_lock);
365 pr_err("%s: failed to register clock %s\n", __func__,
370 rockchip_clk_add_lookup(clk, list->id);
374 void __init rockchip_clk_register_branches(
375 struct rockchip_clk_branch *list,
378 struct clk *clk = NULL;
382 for (idx = 0; idx < nr_clk; idx++, list++) {
385 /* catch simple muxes */
386 switch (list->branch_type) {
388 clk = clk_register_mux(NULL, list->name,
389 list->parent_names, list->num_parents,
390 flags, reg_base + list->muxdiv_offset,
391 list->mux_shift, list->mux_width,
392 list->mux_flags, &clk_lock);
396 clk = clk_register_divider_table(NULL,
397 list->name, list->parent_names[0],
398 flags, reg_base + list->muxdiv_offset,
399 list->div_shift, list->div_width,
400 list->div_flags, list->div_table,
403 clk = clk_register_divider(NULL, list->name,
404 list->parent_names[0], flags,
405 reg_base + list->muxdiv_offset,
406 list->div_shift, list->div_width,
407 list->div_flags, &clk_lock);
409 case branch_fraction_divider:
410 clk = rockchip_clk_register_frac_branch(list->name,
411 list->parent_names, list->num_parents,
412 reg_base, list->muxdiv_offset, list->div_flags,
413 list->gate_offset, list->gate_shift,
414 list->gate_flags, flags, list->child,
418 flags |= CLK_SET_RATE_PARENT;
420 clk = clk_register_gate(NULL, list->name,
421 list->parent_names[0], flags,
422 reg_base + list->gate_offset,
423 list->gate_shift, list->gate_flags, &clk_lock);
425 case branch_composite:
426 clk = rockchip_clk_register_branch(list->name,
427 list->parent_names, list->num_parents,
428 reg_base, list->muxdiv_offset, list->mux_shift,
429 list->mux_width, list->mux_flags,
430 list->div_shift, list->div_width,
431 list->div_flags, list->div_table,
432 list->gate_offset, list->gate_shift,
433 list->gate_flags, flags, &clk_lock);
436 clk = rockchip_clk_register_mmc(
438 list->parent_names, list->num_parents,
439 reg_base + list->muxdiv_offset,
443 case branch_inverter:
444 clk = rockchip_clk_register_inverter(
445 list->name, list->parent_names,
447 reg_base + list->muxdiv_offset,
448 list->div_shift, list->div_flags, &clk_lock);
451 clk = rockchip_clk_register_factor_branch(
452 list->name, list->parent_names,
453 list->num_parents, reg_base,
454 list->div_shift, list->div_width,
455 list->gate_offset, list->gate_shift,
456 list->gate_flags, flags, &clk_lock);
460 /* none of the cases above matched */
462 pr_err("%s: unknown clock type %d\n",
463 __func__, list->branch_type);
468 pr_err("%s: failed to register clock %s: %ld\n",
469 __func__, list->name, PTR_ERR(clk));
473 rockchip_clk_add_lookup(clk, list->id);
477 void __init rockchip_clk_register_armclk(unsigned int lookup_id,
478 const char *name, const char *const *parent_names,
480 const struct rockchip_cpuclk_reg_data *reg_data,
481 const struct rockchip_cpuclk_rate_table *rates,
486 clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents,
487 reg_data, rates, nrates, reg_base,
490 pr_err("%s: failed to register clock %s: %ld\n",
491 __func__, name, PTR_ERR(clk));
495 rockchip_clk_add_lookup(clk, lookup_id);
498 void __init rockchip_clk_protect_critical(const char *const clocks[],
503 /* Protect the clocks that needs to stay on */
504 for (i = 0; i < nclocks; i++) {
505 struct clk *clk = __clk_lookup(clocks[i]);
508 clk_prepare_enable(clk);
512 static unsigned int reg_restart;
513 static void (*cb_restart)(void);
514 static int rockchip_restart_notify(struct notifier_block *this,
515 unsigned long mode, void *cmd)
520 writel(0xfdb9, reg_base + reg_restart);
524 static struct notifier_block rockchip_restart_handler = {
525 .notifier_call = rockchip_restart_notify,
529 void __init rockchip_register_restart_notifier(unsigned int reg, void (*cb)(void))
535 ret = register_restart_handler(&rockchip_restart_handler);
537 pr_err("%s: cannot register restart handler, %d\n",