2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
8 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
9 * Copyright (c) 2013 Linaro Ltd.
10 * Author: Thomas Abraham <thomas.ab@samsung.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
23 #include <linux/slab.h>
24 #include <linux/clk.h>
25 #include <linux/clk-provider.h>
26 #include <linux/mfd/syscon.h>
27 #include <linux/regmap.h>
28 #include <linux/reboot.h>
32 * Register a clock branch.
33 * Most clock branches have a form like
39 * sometimes without one of those components.
41 static struct clk *rockchip_clk_register_branch(const char *name,
42 const char *const *parent_names, u8 num_parents, void __iomem *base,
43 int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
44 u8 div_shift, u8 div_width, u8 div_flags,
45 struct clk_div_table *div_table, int gate_offset,
46 u8 gate_shift, u8 gate_flags, unsigned long flags,
50 struct clk_mux *mux = NULL;
51 struct clk_gate *gate = NULL;
52 struct clk_divider *div = NULL;
53 const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
56 if (num_parents > 1) {
57 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
59 return ERR_PTR(-ENOMEM);
61 mux->reg = base + muxdiv_offset;
62 mux->shift = mux_shift;
63 mux->mask = BIT(mux_width) - 1;
64 mux->flags = mux_flags;
66 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
70 if (gate_offset >= 0) {
71 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
75 gate->flags = gate_flags;
76 gate->reg = base + gate_offset;
77 gate->bit_idx = gate_shift;
79 gate_ops = &clk_gate_ops;
83 div = kzalloc(sizeof(*div), GFP_KERNEL);
87 div->flags = div_flags;
88 div->reg = base + muxdiv_offset;
89 div->shift = div_shift;
90 div->width = div_width;
92 div->table = div_table;
93 div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
98 clk = clk_register_composite(NULL, name, parent_names, num_parents,
99 mux ? &mux->hw : NULL, mux_ops,
100 div ? &div->hw : NULL, div_ops,
101 gate ? &gate->hw : NULL, gate_ops,
109 return ERR_PTR(-ENOMEM);
112 struct rockchip_clk_frac {
113 struct notifier_block clk_nb;
114 struct clk_fractional_divider div;
115 struct clk_gate gate;
118 const struct clk_ops *mux_ops;
121 bool rate_change_remuxed;
125 #define to_rockchip_clk_frac_nb(nb) \
126 container_of(nb, struct rockchip_clk_frac, clk_nb)
128 static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
129 unsigned long event, void *data)
131 struct clk_notifier_data *ndata = data;
132 struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb);
133 struct clk_mux *frac_mux = &frac->mux;
136 pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
137 __func__, event, ndata->old_rate, ndata->new_rate);
138 if (event == PRE_RATE_CHANGE) {
139 frac->rate_change_idx = frac->mux_ops->get_parent(&frac_mux->hw);
140 if (frac->rate_change_idx != frac->mux_frac_idx) {
141 frac->mux_ops->set_parent(&frac_mux->hw, frac->mux_frac_idx);
142 frac->rate_change_remuxed = 1;
144 } else if (event == POST_RATE_CHANGE) {
146 * The POST_RATE_CHANGE notifier runs directly after the
147 * divider clock is set in clk_change_rate, so we'll have
148 * remuxed back to the original parent before clk_change_rate
149 * reaches the mux itself.
151 if (frac->rate_change_remuxed) {
152 frac->mux_ops->set_parent(&frac_mux->hw, frac->rate_change_idx);
153 frac->rate_change_remuxed = 0;
157 return notifier_from_errno(ret);
160 static struct clk *rockchip_clk_register_frac_branch(const char *name,
161 const char *const *parent_names, u8 num_parents,
162 void __iomem *base, int muxdiv_offset, u8 div_flags,
163 int gate_offset, u8 gate_shift, u8 gate_flags,
164 unsigned long flags, struct rockchip_clk_branch *child,
167 struct rockchip_clk_frac *frac;
169 struct clk_gate *gate = NULL;
170 struct clk_fractional_divider *div = NULL;
171 const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
173 if (muxdiv_offset < 0)
174 return ERR_PTR(-EINVAL);
176 if (child && child->branch_type != branch_mux) {
177 pr_err("%s: fractional child clock for %s can only be a mux\n",
179 return ERR_PTR(-EINVAL);
182 frac = kzalloc(sizeof(*frac), GFP_KERNEL);
184 return ERR_PTR(-ENOMEM);
186 if (gate_offset >= 0) {
188 gate->flags = gate_flags;
189 gate->reg = base + gate_offset;
190 gate->bit_idx = gate_shift;
192 gate_ops = &clk_gate_ops;
196 div->flags = div_flags;
197 div->reg = base + muxdiv_offset;
200 div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift;
203 div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
205 div_ops = &clk_fractional_divider_ops;
207 clk = clk_register_composite(NULL, name, parent_names, num_parents,
210 gate ? &gate->hw : NULL, gate_ops,
211 flags | CLK_SET_RATE_UNGATE);
218 struct clk_mux *frac_mux = &frac->mux;
219 struct clk_init_data init;
223 frac->mux_frac_idx = -1;
224 for (i = 0; i < child->num_parents; i++) {
225 if (!strcmp(name, child->parent_names[i])) {
226 pr_debug("%s: found fractional parent in mux at pos %d\n",
228 frac->mux_frac_idx = i;
233 frac->mux_ops = &clk_mux_ops;
234 frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb;
236 frac_mux->reg = base + child->muxdiv_offset;
237 frac_mux->shift = child->mux_shift;
238 frac_mux->mask = BIT(child->mux_width) - 1;
239 frac_mux->flags = child->mux_flags;
240 frac_mux->lock = lock;
241 frac_mux->hw.init = &init;
243 init.name = child->name;
244 init.flags = child->flags | CLK_SET_RATE_PARENT;
245 init.ops = frac->mux_ops;
246 init.parent_names = child->parent_names;
247 init.num_parents = child->num_parents;
249 mux_clk = clk_register(NULL, &frac_mux->hw);
253 rockchip_clk_add_lookup(mux_clk, child->id);
255 /* notifier on the fraction divider to catch rate changes */
256 if (frac->mux_frac_idx >= 0) {
257 ret = clk_notifier_register(clk, &frac->clk_nb);
259 pr_err("%s: failed to register clock notifier for %s\n",
262 pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n",
263 __func__, name, child->name);
270 static struct clk *rockchip_clk_register_factor_branch(const char *name,
271 const char *const *parent_names, u8 num_parents,
272 void __iomem *base, unsigned int mult, unsigned int div,
273 int gate_offset, u8 gate_shift, u8 gate_flags,
274 unsigned long flags, spinlock_t *lock)
277 struct clk_gate *gate = NULL;
278 struct clk_fixed_factor *fix = NULL;
280 /* without gate, register a simple factor clock */
281 if (gate_offset == 0) {
282 return clk_register_fixed_factor(NULL, name,
283 parent_names[0], flags, mult,
287 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
289 return ERR_PTR(-ENOMEM);
291 gate->flags = gate_flags;
292 gate->reg = base + gate_offset;
293 gate->bit_idx = gate_shift;
296 fix = kzalloc(sizeof(*fix), GFP_KERNEL);
299 return ERR_PTR(-ENOMEM);
305 clk = clk_register_composite(NULL, name, parent_names, num_parents,
307 &fix->hw, &clk_fixed_factor_ops,
308 &gate->hw, &clk_gate_ops, flags);
317 static DEFINE_SPINLOCK(clk_lock);
318 static struct clk **clk_table;
319 static void __iomem *reg_base;
320 static struct clk_onecell_data clk_data;
321 static struct device_node *cru_node;
322 static struct regmap *grf;
324 void __init rockchip_clk_init(struct device_node *np, void __iomem *base,
325 unsigned long nr_clks)
329 grf = ERR_PTR(-EPROBE_DEFER);
331 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
333 pr_err("%s: could not allocate clock lookup table\n", __func__);
335 clk_data.clks = clk_table;
336 clk_data.clk_num = nr_clks;
337 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
340 struct regmap *rockchip_clk_get_grf(void)
343 grf = syscon_regmap_lookup_by_phandle(cru_node, "rockchip,grf");
347 void rockchip_clk_add_lookup(struct clk *clk, unsigned int id)
353 void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list,
354 unsigned int nr_pll, int grf_lock_offset)
359 for (idx = 0; idx < nr_pll; idx++, list++) {
360 clk = rockchip_clk_register_pll(list->type, list->name,
361 list->parent_names, list->num_parents,
362 reg_base, list->con_offset, grf_lock_offset,
363 list->lock_shift, list->mode_offset,
364 list->mode_shift, list->rate_table,
365 list->pll_flags, &clk_lock);
367 pr_err("%s: failed to register clock %s\n", __func__,
372 rockchip_clk_add_lookup(clk, list->id);
376 void __init rockchip_clk_register_branches(
377 struct rockchip_clk_branch *list,
380 struct clk *clk = NULL;
384 for (idx = 0; idx < nr_clk; idx++, list++) {
387 /* catch simple muxes */
388 switch (list->branch_type) {
390 clk = clk_register_mux(NULL, list->name,
391 list->parent_names, list->num_parents,
392 flags, reg_base + list->muxdiv_offset,
393 list->mux_shift, list->mux_width,
394 list->mux_flags, &clk_lock);
398 clk = clk_register_divider_table(NULL,
399 list->name, list->parent_names[0],
400 flags, reg_base + list->muxdiv_offset,
401 list->div_shift, list->div_width,
402 list->div_flags, list->div_table,
405 clk = clk_register_divider(NULL, list->name,
406 list->parent_names[0], flags,
407 reg_base + list->muxdiv_offset,
408 list->div_shift, list->div_width,
409 list->div_flags, &clk_lock);
411 case branch_fraction_divider:
412 clk = rockchip_clk_register_frac_branch(list->name,
413 list->parent_names, list->num_parents,
414 reg_base, list->muxdiv_offset, list->div_flags,
415 list->gate_offset, list->gate_shift,
416 list->gate_flags, flags, list->child,
420 flags |= CLK_SET_RATE_PARENT;
422 clk = clk_register_gate(NULL, list->name,
423 list->parent_names[0], flags,
424 reg_base + list->gate_offset,
425 list->gate_shift, list->gate_flags, &clk_lock);
427 case branch_composite:
428 clk = rockchip_clk_register_branch(list->name,
429 list->parent_names, list->num_parents,
430 reg_base, list->muxdiv_offset, list->mux_shift,
431 list->mux_width, list->mux_flags,
432 list->div_shift, list->div_width,
433 list->div_flags, list->div_table,
434 list->gate_offset, list->gate_shift,
435 list->gate_flags, flags, &clk_lock);
438 clk = rockchip_clk_register_mmc(
440 list->parent_names, list->num_parents,
441 reg_base + list->muxdiv_offset,
445 case branch_inverter:
446 clk = rockchip_clk_register_inverter(
447 list->name, list->parent_names,
449 reg_base + list->muxdiv_offset,
450 list->div_shift, list->div_flags, &clk_lock);
453 clk = rockchip_clk_register_factor_branch(
454 list->name, list->parent_names,
455 list->num_parents, reg_base,
456 list->div_shift, list->div_width,
457 list->gate_offset, list->gate_shift,
458 list->gate_flags, flags, &clk_lock);
462 /* none of the cases above matched */
464 pr_err("%s: unknown clock type %d\n",
465 __func__, list->branch_type);
470 pr_err("%s: failed to register clock %s: %ld\n",
471 __func__, list->name, PTR_ERR(clk));
475 rockchip_clk_add_lookup(clk, list->id);
479 void __init rockchip_clk_register_armclk(unsigned int lookup_id,
480 const char *name, const char *const *parent_names,
482 const struct rockchip_cpuclk_reg_data *reg_data,
483 const struct rockchip_cpuclk_rate_table *rates,
488 clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents,
489 reg_data, rates, nrates, reg_base,
492 pr_err("%s: failed to register clock %s: %ld\n",
493 __func__, name, PTR_ERR(clk));
497 rockchip_clk_add_lookup(clk, lookup_id);
500 void __init rockchip_clk_protect_critical(const char *const clocks[],
505 /* Protect the clocks that needs to stay on */
506 for (i = 0; i < nclocks; i++) {
507 struct clk *clk = __clk_lookup(clocks[i]);
510 clk_prepare_enable(clk);
514 static unsigned int reg_restart;
515 static void (*cb_restart)(void);
516 static int rockchip_restart_notify(struct notifier_block *this,
517 unsigned long mode, void *cmd)
522 writel(0xfdb9, reg_base + reg_restart);
526 static struct notifier_block rockchip_restart_handler = {
527 .notifier_call = rockchip_restart_notify,
531 void __init rockchip_register_restart_notifier(unsigned int reg, void (*cb)(void))
537 ret = register_restart_handler(&rockchip_restart_handler);
539 pr_err("%s: cannot register restart handler, %d\n",