2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
11 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
12 * Copyright (c) 2013 Linaro Ltd.
13 * Author: Thomas Abraham <thomas.ab@samsung.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #ifndef CLK_ROCKCHIP_CLK_H
27 #define CLK_ROCKCHIP_CLK_H
33 #define HIWORD_UPDATE(val, mask, shift) \
34 ((val) << (shift) | (mask) << ((shift) + 16))
36 /* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */
37 #define RK2928_PLL_CON(x) ((x) * 0x4)
38 #define RK2928_MODE_CON 0x40
39 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
40 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
41 #define RK2928_GLB_SRST_FST 0x100
42 #define RK2928_GLB_SRST_SND 0x104
43 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
44 #define RK2928_MISC_CON 0x134
46 #define RK3036_SDMMC_CON0 0x144
47 #define RK3036_SDMMC_CON1 0x148
48 #define RK3036_SDIO_CON0 0x14c
49 #define RK3036_SDIO_CON1 0x150
50 #define RK3036_EMMC_CON0 0x154
51 #define RK3036_EMMC_CON1 0x158
53 #define RK3228_GLB_SRST_FST 0x1f0
54 #define RK3228_GLB_SRST_SND 0x1f4
55 #define RK3228_SDMMC_CON0 0x1c0
56 #define RK3228_SDMMC_CON1 0x1c4
57 #define RK3228_SDIO_CON0 0x1c8
58 #define RK3228_SDIO_CON1 0x1cc
59 #define RK3228_EMMC_CON0 0x1d8
60 #define RK3228_EMMC_CON1 0x1dc
62 #define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
63 #define RK3288_MODE_CON 0x50
64 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
65 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
66 #define RK3288_GLB_SRST_FST 0x1b0
67 #define RK3288_GLB_SRST_SND 0x1b4
68 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
69 #define RK3288_MISC_CON 0x1e8
70 #define RK3288_SDMMC_CON0 0x200
71 #define RK3288_SDMMC_CON1 0x204
72 #define RK3288_SDIO0_CON0 0x208
73 #define RK3288_SDIO0_CON1 0x20c
74 #define RK3288_SDIO1_CON0 0x210
75 #define RK3288_SDIO1_CON1 0x214
76 #define RK3288_EMMC_CON0 0x218
77 #define RK3288_EMMC_CON1 0x21c
79 #define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
80 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
81 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
82 #define RK3368_GLB_SRST_FST 0x280
83 #define RK3368_GLB_SRST_SND 0x284
84 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
85 #define RK3368_MISC_CON 0x380
86 #define RK3368_SDMMC_CON0 0x400
87 #define RK3368_SDMMC_CON1 0x404
88 #define RK3368_SDIO0_CON0 0x408
89 #define RK3368_SDIO0_CON1 0x40c
90 #define RK3368_SDIO1_CON0 0x410
91 #define RK3368_SDIO1_CON1 0x414
92 #define RK3368_EMMC_CON0 0x418
93 #define RK3368_EMMC_CON1 0x41c
95 enum rockchip_pll_type {
100 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
101 _postdiv2, _dsmpd, _frac) \
105 .postdiv1 = _postdiv1, \
107 .postdiv2 = _postdiv2, \
112 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
118 .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
121 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
130 struct rockchip_pll_rate_table {
138 unsigned int postdiv1;
140 unsigned int postdiv2;
146 * struct rockchip_pll_clock: information about pll clock
147 * @id: platform specific id of the clock.
148 * @name: name of this pll clock.
149 * @parent_name: name of the parent clock.
150 * @flags: optional flags for basic clock.
151 * @con_offset: offset of the register for configuring the PLL.
152 * @mode_offset: offset of the register for configuring the PLL-mode.
153 * @mode_shift: offset inside the mode-register for the mode of this pll.
154 * @lock_shift: offset inside the lock register for the lock status.
155 * @type: Type of PLL to be registered.
156 * @pll_flags: hardware-specific flags
157 * @rate_table: Table of usable pll rates
160 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
161 * rate_table parameters and ajust them if necessary.
163 struct rockchip_pll_clock {
166 const char *const *parent_names;
173 enum rockchip_pll_type type;
175 struct rockchip_pll_rate_table *rate_table;
178 #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
180 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
181 _lshift, _pflags, _rtable) \
186 .parent_names = _pnames, \
187 .num_parents = ARRAY_SIZE(_pnames), \
188 .flags = CLK_GET_RATE_NOCACHE | _flags, \
189 .con_offset = _con, \
190 .mode_offset = _mode, \
191 .mode_shift = _mshift, \
192 .lock_shift = _lshift, \
193 .pll_flags = _pflags, \
194 .rate_table = _rtable, \
197 struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
198 const char *name, const char *const *parent_names,
199 u8 num_parents, void __iomem *base, int con_offset,
200 int grf_lock_offset, int lock_shift, int reg_mode,
201 int mode_shift, struct rockchip_pll_rate_table *rate_table,
202 u8 clk_pll_flags, spinlock_t *lock);
204 struct rockchip_cpuclk_clksel {
209 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2
210 struct rockchip_cpuclk_rate_table {
212 struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
216 * struct rockchip_cpuclk_reg_data: describes register offsets and masks of the cpuclock
217 * @core_reg: register offset of the core settings register
218 * @div_core_shift: core divider offset used to divide the pll value
219 * @div_core_mask: core divider mask
220 * @mux_core_shift: offset of the core multiplexer
222 struct rockchip_cpuclk_reg_data {
230 struct clk *rockchip_clk_register_cpuclk(const char *name,
231 const char *const *parent_names, u8 num_parents,
232 const struct rockchip_cpuclk_reg_data *reg_data,
233 const struct rockchip_cpuclk_rate_table *rates,
234 int nrates, void __iomem *reg_base, spinlock_t *lock);
236 struct clk *rockchip_clk_register_mmc(const char *name,
237 const char *const *parent_names, u8 num_parents,
238 void __iomem *reg, int shift);
240 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
242 struct clk *rockchip_clk_register_inverter(const char *name,
243 const char *const *parent_names, u8 num_parents,
244 void __iomem *reg, int shift, int flags,
247 #define PNAME(x) static const char *const x[] __initconst
249 enum rockchip_clk_branch_type {
253 branch_fraction_divider,
260 struct rockchip_clk_branch {
262 enum rockchip_clk_branch_type branch_type;
264 const char *const *parent_names;
274 struct clk_div_table *div_table;
278 struct rockchip_clk_branch *child;
281 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
285 .branch_type = branch_composite, \
287 .parent_names = pnames, \
288 .num_parents = ARRAY_SIZE(pnames), \
290 .muxdiv_offset = mo, \
302 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
306 .branch_type = branch_composite, \
308 .parent_names = (const char *[]){ pname }, \
311 .muxdiv_offset = mo, \
320 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
321 df, dt, go, gs, gf) \
324 .branch_type = branch_composite, \
326 .parent_names = (const char *[]){ pname }, \
329 .muxdiv_offset = mo, \
339 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
343 .branch_type = branch_composite, \
345 .parent_names = pnames, \
346 .num_parents = ARRAY_SIZE(pnames), \
348 .muxdiv_offset = mo, \
357 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
361 .branch_type = branch_composite, \
363 .parent_names = pnames, \
364 .num_parents = ARRAY_SIZE(pnames), \
366 .muxdiv_offset = mo, \
376 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
377 mw, mf, ds, dw, df, dt) \
380 .branch_type = branch_composite, \
382 .parent_names = pnames, \
383 .num_parents = ARRAY_SIZE(pnames), \
385 .muxdiv_offset = mo, \
396 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
399 .branch_type = branch_fraction_divider, \
401 .parent_names = (const char *[]){ pname }, \
404 .muxdiv_offset = mo, \
413 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
416 .branch_type = branch_fraction_divider, \
418 .parent_names = (const char *[]){ pname }, \
421 .muxdiv_offset = mo, \
431 #define MUX(_id, cname, pnames, f, o, s, w, mf) \
434 .branch_type = branch_mux, \
436 .parent_names = pnames, \
437 .num_parents = ARRAY_SIZE(pnames), \
439 .muxdiv_offset = o, \
446 #define DIV(_id, cname, pname, f, o, s, w, df) \
449 .branch_type = branch_divider, \
451 .parent_names = (const char *[]){ pname }, \
454 .muxdiv_offset = o, \
461 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
464 .branch_type = branch_divider, \
466 .parent_names = (const char *[]){ pname }, \
469 .muxdiv_offset = o, \
476 #define GATE(_id, cname, pname, f, o, b, gf) \
479 .branch_type = branch_gate, \
481 .parent_names = (const char *[]){ pname }, \
489 #define MMC(_id, cname, pname, offset, shift) \
492 .branch_type = branch_mmc, \
494 .parent_names = (const char *[]){ pname }, \
496 .muxdiv_offset = offset, \
497 .div_shift = shift, \
500 #define INVERTER(_id, cname, pname, io, is, if) \
503 .branch_type = branch_inverter, \
505 .parent_names = (const char *[]){ pname }, \
507 .muxdiv_offset = io, \
512 #define FACTOR(_id, cname, pname, f, fm, fd) \
515 .branch_type = branch_factor, \
517 .parent_names = (const char *[]){ pname }, \
524 #define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \
527 .branch_type = branch_factor, \
529 .parent_names = (const char *[]){ pname }, \
539 void rockchip_clk_init(struct device_node *np, void __iomem *base,
540 unsigned long nr_clks);
541 struct regmap *rockchip_clk_get_grf(void);
542 void rockchip_clk_add_lookup(struct clk *clk, unsigned int id);
543 void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list,
544 unsigned int nr_clk);
545 void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
546 unsigned int nr_pll, int grf_lock_offset);
547 void rockchip_clk_register_armclk(unsigned int lookup_id, const char *name,
548 const char *const *parent_names, u8 num_parents,
549 const struct rockchip_cpuclk_reg_data *reg_data,
550 const struct rockchip_cpuclk_rate_table *rates,
552 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
553 void rockchip_register_restart_notifier(unsigned int reg, void (*cb)(void));
555 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
557 #ifdef CONFIG_RESET_CONTROLLER
558 void rockchip_register_softrst(struct device_node *np,
559 unsigned int num_regs,
560 void __iomem *base, u8 flags);
562 static inline void rockchip_register_softrst(struct device_node *np,
563 unsigned int num_regs,
564 void __iomem *base, u8 flags)