drivers/clk/samsung/clk-exynos5420.c

   1 /*
   2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   3  * Authors: Thomas Abraham <thomas.ab@samsung.com>
   4  *          Chander Kashyap <k.chander@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Common Clock Framework support for Exynos5420 SoC.
  11 */
  12
  13 #include <dt-bindings/clock/exynos5420.h>
  14 #include <linux/clk.h>
  15 #include <linux/clkdev.h>
  16 #include <linux/clk-provider.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <linux/syscore_ops.h>
  20
  21 #include "clk.h"
  22
  23 #define APLL_LOCK               0x0
  24 #define APLL_CON0               0x100
  25 #define SRC_CPU                 0x200
  26 #define DIV_CPU0                0x500
  27 #define DIV_CPU1                0x504
  28 #define GATE_BUS_CPU            0x700
  29 #define GATE_SCLK_CPU           0x800
  30 #define GATE_IP_G2D             0x8800
  31 #define CPLL_LOCK               0x10020
  32 #define DPLL_LOCK               0x10030
  33 #define EPLL_LOCK               0x10040
  34 #define RPLL_LOCK               0x10050
  35 #define IPLL_LOCK               0x10060
  36 #define SPLL_LOCK               0x10070
  37 #define VPLL_LOCK               0x10080
  38 #define MPLL_LOCK               0x10090
  39 #define CPLL_CON0               0x10120
  40 #define DPLL_CON0               0x10128
  41 #define EPLL_CON0               0x10130
  42 #define RPLL_CON0               0x10140
  43 #define IPLL_CON0               0x10150
  44 #define SPLL_CON0               0x10160
  45 #define VPLL_CON0               0x10170
  46 #define MPLL_CON0               0x10180
  47 #define SRC_TOP0                0x10200
  48 #define SRC_TOP1                0x10204
  49 #define SRC_TOP2                0x10208
  50 #define SRC_TOP3                0x1020c
  51 #define SRC_TOP4                0x10210
  52 #define SRC_TOP5                0x10214
  53 #define SRC_TOP6                0x10218
  54 #define SRC_TOP7                0x1021c
  55 #define SRC_DISP10              0x1022c
  56 #define SRC_MAU                 0x10240
  57 #define SRC_FSYS                0x10244
  58 #define SRC_PERIC0              0x10250
  59 #define SRC_PERIC1              0x10254
  60 #define SRC_ISP                 0x10270
  61 #define SRC_TOP10               0x10280
  62 #define SRC_TOP11               0x10284
  63 #define SRC_TOP12               0x10288
  64 #define SRC_MASK_DISP10         0x1032c
  65 #define SRC_MASK_FSYS           0x10340
  66 #define SRC_MASK_PERIC0         0x10350
  67 #define SRC_MASK_PERIC1         0x10354
  68 #define DIV_TOP0                0x10500
  69 #define DIV_TOP1                0x10504
  70 #define DIV_TOP2                0x10508
  71 #define DIV_DISP10              0x1052c
  72 #define DIV_MAU                 0x10544
  73 #define DIV_FSYS0               0x10548
  74 #define DIV_FSYS1               0x1054c
  75 #define DIV_FSYS2               0x10550
  76 #define DIV_PERIC0              0x10558
  77 #define DIV_PERIC1              0x1055c
  78 #define DIV_PERIC2              0x10560
  79 #define DIV_PERIC3              0x10564
  80 #define DIV_PERIC4              0x10568
  81 #define SCLK_DIV_ISP0           0x10580
  82 #define SCLK_DIV_ISP1           0x10584
  83 #define DIV2_RATIO0             0x10590
  84 #define GATE_BUS_TOP            0x10700
  85 #define GATE_BUS_FSYS0          0x10740
  86 #define GATE_BUS_PERIC          0x10750
  87 #define GATE_BUS_PERIC1         0x10754
  88 #define GATE_BUS_PERIS0         0x10760
  89 #define GATE_BUS_PERIS1         0x10764
  90 #define GATE_TOP_SCLK_ISP       0x10870
  91 #define GATE_IP_GSCL0           0x10910
  92 #define GATE_IP_GSCL1           0x10920
  93 #define GATE_IP_MFC             0x1092c
  94 #define GATE_IP_DISP1           0x10928
  95 #define GATE_IP_G3D             0x10930
  96 #define GATE_IP_GEN             0x10934
  97 #define GATE_IP_MSCL            0x10970
  98 #define GATE_TOP_SCLK_GSCL      0x10820
  99 #define GATE_TOP_SCLK_DISP1     0x10828
 100 #define GATE_TOP_SCLK_MAU       0x1083c
 101 #define GATE_TOP_SCLK_FSYS      0x10840
 102 #define GATE_TOP_SCLK_PERIC     0x10850
 103 #define BPLL_LOCK               0x20010
 104 #define BPLL_CON0               0x20110
 105 #define SRC_CDREX               0x20200
 106 #define KPLL_LOCK               0x28000
 107 #define KPLL_CON0               0x28100
 108 #define SRC_KFC                 0x28200
 109 #define DIV_KFC0                0x28500
 110
 111 /* list of PLLs */
 112 enum exynos5420_plls {
 113         apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
 114         bpll, kpll,
 115         nr_plls                 /* number of PLLs */
 116 };
 117
 118 static void __iomem *reg_base;
 119
 120 #ifdef CONFIG_PM_SLEEP
 121 static struct samsung_clk_reg_dump *exynos5420_save;
 122
 123 /*
 124  * list of controller registers to be saved and restored during a
 125  * suspend/resume cycle.
 126  */
 127 static unsigned long exynos5420_clk_regs[] __initdata = {
 128         SRC_CPU,
 129         DIV_CPU0,
 130         DIV_CPU1,
 131         GATE_BUS_CPU,
 132         GATE_SCLK_CPU,
 133         SRC_TOP0,
 134         SRC_TOP1,
 135         SRC_TOP2,
 136         SRC_TOP3,
 137         SRC_TOP4,
 138         SRC_TOP5,
 139         SRC_TOP6,
 140         SRC_TOP7,
 141         SRC_DISP10,
 142         SRC_MAU,
 143         SRC_FSYS,
 144         SRC_PERIC0,
 145         SRC_PERIC1,
 146         SRC_TOP10,
 147         SRC_TOP11,
 148         SRC_TOP12,
 149         SRC_MASK_DISP10,
 150         SRC_MASK_FSYS,
 151         SRC_MASK_PERIC0,
 152         SRC_MASK_PERIC1,
 153         SRC_ISP,
 154         DIV_TOP0,
 155         DIV_TOP1,
 156         DIV_TOP2,
 157         DIV_DISP10,
 158         DIV_MAU,
 159         DIV_FSYS0,
 160         DIV_FSYS1,
 161         DIV_FSYS2,
 162         DIV_PERIC0,
 163         DIV_PERIC1,
 164         DIV_PERIC2,
 165         DIV_PERIC3,
 166         DIV_PERIC4,
 167         SCLK_DIV_ISP0,
 168         SCLK_DIV_ISP1,
 169         DIV2_RATIO0,
 170         GATE_BUS_TOP,
 171         GATE_BUS_FSYS0,
 172         GATE_BUS_PERIC,
 173         GATE_BUS_PERIC1,
 174         GATE_BUS_PERIS0,
 175         GATE_BUS_PERIS1,
 176         GATE_TOP_SCLK_ISP,
 177         GATE_IP_GSCL0,
 178         GATE_IP_GSCL1,
 179         GATE_IP_MFC,
 180         GATE_IP_DISP1,
 181         GATE_IP_G3D,
 182         GATE_IP_GEN,
 183         GATE_IP_MSCL,
 184         GATE_TOP_SCLK_GSCL,
 185         GATE_TOP_SCLK_DISP1,
 186         GATE_TOP_SCLK_MAU,
 187         GATE_TOP_SCLK_FSYS,
 188         GATE_TOP_SCLK_PERIC,
 189         SRC_CDREX,
 190         SRC_KFC,
 191         DIV_KFC0,
 192 };
 193
 194 static int exynos5420_clk_suspend(void)
 195 {
 196         samsung_clk_save(reg_base, exynos5420_save,
 197                                 ARRAY_SIZE(exynos5420_clk_regs));
 198
 199         return 0;
 200 }
 201
 202 static void exynos5420_clk_resume(void)
 203 {
 204         samsung_clk_restore(reg_base, exynos5420_save,
 205                                 ARRAY_SIZE(exynos5420_clk_regs));
 206 }
 207
 208 static struct syscore_ops exynos5420_clk_syscore_ops = {
 209         .suspend = exynos5420_clk_suspend,
 210         .resume = exynos5420_clk_resume,
 211 };
 212
 213 static void exynos5420_clk_sleep_init(void)
 214 {
 215         exynos5420_save = samsung_clk_alloc_reg_dump(exynos5420_clk_regs,
 216                                         ARRAY_SIZE(exynos5420_clk_regs));
 217         if (!exynos5420_save) {
 218                 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
 219                         __func__);
 220                 return;
 221         }
 222
 223         register_syscore_ops(&exynos5420_clk_syscore_ops);
 224 }
 225 #else
 226 static void exynos5420_clk_sleep_init(void) {}
 227 #endif
 228
 229 /* list of all parent clocks */
 230 PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
 231                                 "mout_sclk_mpll", "mout_sclk_spll"};
 232 PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
 233 PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
 234 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
 235 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
 236 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
 237 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
 238 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
 239 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
 240 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
 241 PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
 242 PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
 243 PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
 244 PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
 245
 246 PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
 247                                         "mout_sclk_mpll"};
 248 PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
 249                         "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
 250                         "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
 251 PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
 252 PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
 253 PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
 254
 255 PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
 256 PNAME(mout_aclk66_peric_p)      = { "fin_pll", "mout_sw_aclk66" };
 257
 258 PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
 259 PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};
 260
 261 PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
 262 PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
 263 PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
 264 PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
 265
 266 PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
 267                                         "mout_sclk_spll"};
 268 PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
 269
 270 PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
 271 PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
 272
 273 PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
 274 PNAME(mout_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
 275
 276 PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
 277 PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
 278
 279 PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
 280 PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
 281
 282 PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
 283 PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
 284
 285 PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
 286 PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
 287 PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
 288
 289 PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
 290 PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
 291
 292 PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
 293 PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
 294
 295 PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
 296 PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
 297
 298 PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
 299 PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
 300
 301 PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
 302 PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
 303
 304 PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
 305 PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
 306
 307 PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
 308 PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
 309
 310 PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
 311                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 312                         "mout_sclk_epll", "mout_sclk_rpll"};
 313 PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
 314                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 315                         "mout_sclk_epll", "mout_sclk_rpll"};
 316 PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
 317                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 318                         "mout_sclk_epll", "mout_sclk_rpll"};
 319 PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
 320                         "dout_audio2", "spdif_extclk", "mout_sclk_ipll",
 321                         "mout_sclk_epll", "mout_sclk_rpll"};
 322 PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
 323 PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
 324                          "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
 325                          "mout_sclk_epll", "mout_sclk_rpll"};
 326
 327 /* fixed rate clocks generated outside the soc */
 328 static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
 329         FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
 330 };
 331
 332 /* fixed rate clocks generated inside the soc */
 333 static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = {
 334         FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
 335         FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
 336         FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
 337         FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
 338         FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
 339 };
 340
 341 static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = {
 342         FFACTOR(0, "sclk_hsic_12m", "fin_pll", 1, 2, 0),
 343 };
 344
 345 static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
 346         MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
 347         MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
 348         MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
 349         MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
 350         MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
 351         MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
 352
 353         MUX(0, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
 354
 355         MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
 356         MUX_A(0, "mout_aclk400_mscl", mout_group1_p,
 357                         SRC_TOP0, 4, 2, "aclk400_mscl"),
 358         MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
 359         MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
 360         MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
 361
 362         MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
 363         MUX(0, "mout_aclk333_432_isp", mout_group4_p,
 364                         SRC_TOP1, 4, 2),
 365         MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
 366         MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
 367         MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
 368         MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
 369         MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
 370
 371         MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
 372         MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
 373         MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
 374         MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
 375         MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
 376         MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
 377
 378         MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
 379                         SRC_TOP3, 0, 1),
 380         MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
 381                         SRC_TOP3, 4, 1),
 382         MUX(0, "mout_aclk200_disp1", mout_aclk200_disp1_p, SRC_TOP3, 8, 1),
 383         MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
 384                         SRC_TOP3, 12, 1),
 385         MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
 386                         SRC_TOP3, 28, 1),
 387
 388         MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
 389                         SRC_TOP4, 0, 1),
 390         MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
 391                         SRC_TOP4, 4, 1),
 392         MUX(0, "mout_aclk66_peric", mout_aclk66_peric_p, SRC_TOP4, 8, 1),
 393         MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
 394                         SRC_TOP4, 12, 1),
 395         MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
 396                         SRC_TOP4, 16, 1),
 397         MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
 398         MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
 399         MUX(0, "mout_user_aclk333", mout_user_aclk333_p, SRC_TOP4, 28, 1),
 400
 401         MUX(0, "mout_aclk66_psgen", mout_aclk66_peric_p, SRC_TOP5, 4, 1),
 402         MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
 403                         SRC_TOP5, 8, 1),
 404         MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
 405                         SRC_TOP5, 12, 1),
 406         MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
 407                         SRC_TOP5, 16, 1),
 408         MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
 409                         SRC_TOP5, 20, 1),
 410         MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p,
 411                         SRC_TOP5, 24, 1),
 412         MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,
 413                         SRC_TOP5, 28, 1),
 414
 415         MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
 416         MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
 417         MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
 418         MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
 419         MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
 420         MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1),
 421         MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
 422         MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
 423
 424         MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
 425                         SRC_TOP10, 0, 1),
 426         MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
 427                         SRC_TOP10, 4, 1),
 428         MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1),
 429         MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
 430                         SRC_TOP10, 12, 1),
 431         MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
 432                         SRC_TOP10, 28, 1),
 433
 434         MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
 435                         SRC_TOP11, 0, 1),
 436         MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
 437                         SRC_TOP11, 4, 1),
 438         MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
 439         MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
 440                         SRC_TOP11, 12, 1),
 441         MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
 442         MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
 443         MUX(0, "mout_sw_aclk333", mout_sw_aclk333_p, SRC_TOP11, 28, 1),
 444
 445         MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
 446                         SRC_TOP12, 8, 1),
 447         MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
 448                         SRC_TOP12, 12, 1),
 449         MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
 450         MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
 451                         SRC_TOP12, 20, 1),
 452         MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p,
 453                         SRC_TOP12, 24, 1),
 454         MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,
 455                         SRC_TOP12, 28, 1),
 456
 457         /* DISP1 Block */
 458         MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
 459         MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
 460         MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
 461         MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
 462         MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
 463
 464         /* MAU Block */
 465         MUX(0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
 466
 467         /* FSYS Block */
 468         MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
 469         MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
 470         MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
 471         MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
 472         MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
 473         MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
 474
 475         /* PERIC Block */
 476         MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
 477         MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
 478         MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
 479         MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
 480         MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
 481         MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
 482         MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
 483         MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
 484         MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
 485         MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
 486         MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
 487         MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
 488
 489         /* ISP Block */
 490         MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
 491         MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
 492         MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
 493         MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
 494         MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
 495 };
 496
 497 static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
 498         DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
 499         DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
 500         DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
 501         DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
 502         DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
 503
 504         DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),
 505         DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
 506         DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
 507         DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
 508         DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
 509         DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
 510
 511         DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
 512                         DIV_TOP1, 0, 3),
 513         DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp",
 514                         DIV_TOP1, 4, 3),
 515         DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
 516         DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",
 517                         DIV_TOP1, 16, 3),
 518         DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
 519         DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
 520         DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
 521
 522         DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),
 523         DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
 524         DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
 525         DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
 526         DIV_A(0, "dout_aclk300_disp1", "mout_aclk300_disp1",
 527                         DIV_TOP2, 24, 3, "aclk300_disp1"),
 528         DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
 529
 530         /* DISP1 Block */
 531         DIV(0, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
 532         DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
 533         DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
 534         DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
 535
 536         /* Audio Block */
 537         DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
 538         DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
 539
 540         /* USB3.0 */
 541         DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
 542         DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
 543         DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
 544         DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
 545
 546         /* MMC */
 547         DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
 548         DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
 549         DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
 550
 551         DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
 552
 553         /* UART and PWM */
 554         DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
 555         DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
 556         DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
 557         DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
 558         DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
 559
 560         /* SPI */
 561         DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
 562         DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
 563         DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
 564
 565         /* PCM */
 566         DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
 567         DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
 568
 569         /* Audio - I2S */
 570         DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
 571         DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
 572         DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
 573         DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
 574         DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
 575
 576         /* SPI Pre-Ratio */
 577         DIV(0, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8),
 578         DIV(0, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8),
 579         DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8),
 580
 581         /* GSCL Block */
 582         DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
 583                         DIV2_RATIO0, 4, 2),
 584         DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
 585
 586         /* MSCL Block */
 587         DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
 588
 589         /* ISP Block */
 590         DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
 591         DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
 592         DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
 593         DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
 594         DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
 595         DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
 596         DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
 597         DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
 598                         CLK_SET_RATE_PARENT, 0),
 599         DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
 600                         CLK_SET_RATE_PARENT, 0),
 601 };
 602
 603 static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 604         /* G2D */
 605         GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
 606         GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
 607         GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
 608         GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
 609         GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
 610
 611         /* TODO: Re-verify the CG bits for all the gate clocks */
 612         GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0,
 613                 "mct"),
 614
 615         GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
 616                         GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
 617         GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
 618                         GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
 619
 620         GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
 621                         GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
 622         GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
 623                         GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0),
 624         GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
 625                         GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
 626         GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
 627                         GATE_BUS_TOP, 5, 0, 0),
 628         GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
 629                         GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0),
 630         GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
 631                         GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
 632         GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
 633                         GATE_BUS_TOP, 8, 0, 0),
 634         GATE(0, "pclk66_gpio", "mout_sw_aclk66",
 635                         GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
 636         GATE(0, "aclk66_psgen", "mout_aclk66_psgen",
 637                         GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
 638         GATE(0, "aclk66_peric", "mout_aclk66_peric",
 639                         GATE_BUS_TOP, 11, 0, 0),
 640         GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
 641                         GATE_BUS_TOP, 13, 0, 0),
 642         GATE(0, "aclk166", "mout_user_aclk166",
 643                         GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
 644         GATE(0, "aclk333", "mout_aclk333",
 645                         GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
 646         GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
 647                         GATE_BUS_TOP, 16, 0, 0),
 648         GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
 649                         GATE_BUS_TOP, 17, 0, 0),
 650
 651         /* sclk */
 652         GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
 653                 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
 654         GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
 655                 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
 656         GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
 657                 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
 658         GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
 659                 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
 660         GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_pre_spi0",
 661                 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
 662         GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_pre_spi1",
 663                 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
 664         GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_pre_spi2",
 665                 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
 666         GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
 667                 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
 668         GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
 669                 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
 670         GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
 671                 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
 672         GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
 673                 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
 674         GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
 675                 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
 676         GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
 677                 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
 678
 679         GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
 680                 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
 681         GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
 682                 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
 683         GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
 684                 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
 685         GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
 686                 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
 687         GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
 688                 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
 689         GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
 690                 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
 691         GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
 692                 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
 693
 694         GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro",
 695                 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
 696
 697         /* Display */
 698         GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
 699                 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
 700         GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
 701                 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
 702         GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
 703                 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0),
 704         GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
 705                 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
 706         GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
 707                 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
 708
 709         /* Maudio Block */
 710         GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
 711                 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
 712         GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
 713                 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
 714         /* FSYS */
 715         GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
 716         GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
 717         GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
 718         GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
 719         GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
 720         GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
 721         GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
 722         GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
 723         GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
 724                         GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
 725         GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0),
 726         GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0),
 727         GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0),
 728
 729         /* UART */
 730         GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
 731         GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
 732         GATE_A(CLK_UART2, "uart2", "aclk66_peric",
 733                 GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
 734         GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
 735         /* I2C */
 736         GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
 737         GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
 738         GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
 739         GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
 740         GATE(CLK_I2C4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
 741         GATE(CLK_I2C5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
 742         GATE(CLK_I2C6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
 743         GATE(CLK_I2C7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
 744         GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0,
 745                 0),
 746         GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
 747         /* SPI */
 748         GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
 749         GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
 750         GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
 751         GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
 752         /* I2S */
 753         GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
 754         GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
 755         /* PCM */
 756         GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
 757         GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
 758         /* PWM */
 759         GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
 760         /* SPDIF */
 761         GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
 762
 763         GATE(CLK_I2C8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0),
 764         GATE(CLK_I2C9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0),
 765         GATE(CLK_I2C10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0),
 766
 767         GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
 768                         GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0),
 769         GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
 770                         GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0),
 771         GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0),
 772         GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0),
 773         GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0),
 774         GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0),
 775         GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0),
 776         GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0),
 777         GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0),
 778         GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0),
 779         GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0),
 780         GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0),
 781
 782         GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0,
 783                 0),
 784         GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
 785         GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
 786         GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
 787         GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
 788         GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0),
 789
 790         /* GSCL Block */
 791         GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
 792                         GATE_TOP_SCLK_GSCL, 6, 0, 0),
 793         GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
 794                         GATE_TOP_SCLK_GSCL, 7, 0, 0),
 795
 796         GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
 797         GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
 798         GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
 799                         GATE_IP_GSCL0, 4, 0, 0),
 800         GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
 801                         GATE_IP_GSCL0, 5, 0, 0),
 802         GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
 803                         GATE_IP_GSCL0, 6, 0, 0),
 804
 805         GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
 806                         GATE_IP_GSCL1, 2, 0, 0),
 807         GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
 808                         GATE_IP_GSCL1, 3, 0, 0),
 809         GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
 810                         GATE_IP_GSCL1, 4, 0, 0),
 811         GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
 812                         GATE_IP_GSCL1, 6, 0, 0),
 813         GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
 814                         GATE_IP_GSCL1, 7, 0, 0),
 815         GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0),
 816         GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0),
 817         GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
 818                         GATE_IP_GSCL1, 16, 0, 0),
 819         GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
 820                         GATE_IP_GSCL1, 17, 0, 0),
 821
 822         /* MSCL Block */
 823         GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
 824         GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
 825         GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
 826         GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
 827                         GATE_IP_MSCL, 8, 0, 0),
 828         GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
 829                         GATE_IP_MSCL, 9, 0, 0),
 830         GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
 831                         GATE_IP_MSCL, 10, 0, 0),
 832
 833         GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
 834         GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
 835         GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
 836         GATE(CLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
 837         GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
 838         GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0,
 839                 0),
 840
 841         /* ISP */
 842         GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
 843                         GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
 844         GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
 845                         GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
 846         GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
 847                         GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
 848         GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
 849                         GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
 850         GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
 851                         GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
 852         GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
 853                         GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
 854         GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
 855                         GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
 856
 857         GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
 858         GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
 859         GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
 860
 861         GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
 862
 863         GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
 864         GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
 865         GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
 866         GATE(CLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
 867         GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
 868         GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
 869         GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
 870
 871         GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0,
 872                 0),
 873 };
 874
 875 static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
 876         [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
 877                 APLL_CON0, NULL),
 878         [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
 879                 CPLL_CON0, NULL),
 880         [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
 881                 DPLL_CON0, NULL),
 882         [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
 883                 EPLL_CON0, NULL),
 884         [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
 885                 RPLL_CON0, NULL),
 886         [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
 887                 IPLL_CON0, NULL),
 888         [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
 889                 SPLL_CON0, NULL),
 890         [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
 891                 VPLL_CON0, NULL),
 892         [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
 893                 MPLL_CON0, NULL),
 894         [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
 895                 BPLL_CON0, NULL),
 896         [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
 897                 KPLL_CON0, NULL),
 898 };
 899
 900 static struct of_device_id ext_clk_match[] __initdata = {
 901         { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
 902         { },
 903 };
 904
 905 /* register exynos5420 clocks */
 906 static void __init exynos5420_clk_init(struct device_node *np)
 907 {
 908         struct samsung_clk_provider *ctx;
 909
 910         if (np) {
 911                 reg_base = of_iomap(np, 0);
 912                 if (!reg_base)
 913                         panic("%s: failed to map registers\n", __func__);
 914         } else {
 915                 panic("%s: unable to determine soc\n", __func__);
 916         }
 917
 918         ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
 919         if (!ctx)
 920                 panic("%s: unable to allocate context.\n", __func__);
 921
 922         samsung_clk_of_register_fixed_ext(ctx, exynos5420_fixed_rate_ext_clks,
 923                         ARRAY_SIZE(exynos5420_fixed_rate_ext_clks),
 924                         ext_clk_match);
 925         samsung_clk_register_pll(ctx, exynos5420_plls,
 926                         ARRAY_SIZE(exynos5420_plls),
 927                         reg_base);
 928         samsung_clk_register_fixed_rate(ctx, exynos5420_fixed_rate_clks,
 929                         ARRAY_SIZE(exynos5420_fixed_rate_clks));
 930         samsung_clk_register_fixed_factor(ctx, exynos5420_fixed_factor_clks,
 931                         ARRAY_SIZE(exynos5420_fixed_factor_clks));
 932         samsung_clk_register_mux(ctx, exynos5420_mux_clks,
 933                         ARRAY_SIZE(exynos5420_mux_clks));
 934         samsung_clk_register_div(ctx, exynos5420_div_clks,
 935                         ARRAY_SIZE(exynos5420_div_clks));
 936         samsung_clk_register_gate(ctx, exynos5420_gate_clks,
 937                         ARRAY_SIZE(exynos5420_gate_clks));
 938
 939         exynos5420_clk_sleep_init();
 940 }
 941 CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init);