2 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Common Clock Framework support for S3C2410 and following SoCs.
11 #include <linux/clk.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk-provider.h>
15 #include <linux/of_address.h>
16 #include <linux/syscore_ops.h>
18 #include <dt-bindings/clock/s3c2410.h>
38 /* list of PLLs to be registered */
43 static void __iomem *reg_base;
45 #ifdef CONFIG_PM_SLEEP
46 static struct samsung_clk_reg_dump *s3c2410_save;
49 * list of controller registers to be saved and restored during a
50 * suspend/resume cycle.
52 static unsigned long s3c2410_clk_regs[] __initdata = {
62 static int s3c2410_clk_suspend(void)
64 samsung_clk_save(reg_base, s3c2410_save,
65 ARRAY_SIZE(s3c2410_clk_regs));
70 static void s3c2410_clk_resume(void)
72 samsung_clk_restore(reg_base, s3c2410_save,
73 ARRAY_SIZE(s3c2410_clk_regs));
76 static struct syscore_ops s3c2410_clk_syscore_ops = {
77 .suspend = s3c2410_clk_suspend,
78 .resume = s3c2410_clk_resume,
81 static void s3c2410_clk_sleep_init(void)
83 s3c2410_save = samsung_clk_alloc_reg_dump(s3c2410_clk_regs,
84 ARRAY_SIZE(s3c2410_clk_regs));
86 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
91 register_syscore_ops(&s3c2410_clk_syscore_ops);
95 static void s3c2410_clk_sleep_init(void) {}
98 PNAME(fclk_p) = { "mpll", "div_slow" };
100 struct samsung_mux_clock s3c2410_common_muxes[] __initdata = {
101 MUX(FCLK, "fclk", fclk_p, CLKSLOW, 4, 1),
104 static struct clk_div_table divslow_d[] = {
105 { .val = 0, .div = 1 },
106 { .val = 1, .div = 2 },
107 { .val = 2, .div = 4 },
108 { .val = 3, .div = 6 },
109 { .val = 4, .div = 8 },
110 { .val = 5, .div = 10 },
111 { .val = 6, .div = 12 },
112 { .val = 7, .div = 14 },
116 struct samsung_div_clock s3c2410_common_dividers[] __initdata = {
117 DIV_T(0, "div_slow", "xti", CLKSLOW, 0, 3, divslow_d),
118 DIV(PCLK, "pclk", "hclk", CLKDIVN, 0, 1),
121 struct samsung_gate_clock s3c2410_common_gates[] __initdata = {
122 GATE(PCLK_SPI, "spi", "pclk", CLKCON, 18, 0, 0),
123 GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 17, 0, 0),
124 GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 16, 0, 0),
125 GATE(PCLK_ADC, "adc", "pclk", CLKCON, 15, 0, 0),
126 GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 14, 0, 0),
127 GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 13, CLK_IGNORE_UNUSED, 0),
128 GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 12, 0, 0),
129 GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 11, 0, 0),
130 GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 10, 0, 0),
131 GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 9, 0, 0),
132 GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 8, 0, 0),
133 GATE(HCLK_USBD, "usb-device", "hclk", CLKCON, 7, 0, 0),
134 GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
135 GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
136 GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
139 /* should be added _after_ the soc-specific clocks are created */
140 struct samsung_clock_alias s3c2410_common_aliases[] __initdata = {
141 ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
142 ALIAS(PCLK_ADC, NULL, "adc"),
143 ALIAS(PCLK_RTC, NULL, "rtc"),
144 ALIAS(PCLK_PWM, NULL, "timers"),
145 ALIAS(HCLK_LCD, NULL, "lcd"),
146 ALIAS(HCLK_USBD, NULL, "usb-device"),
147 ALIAS(HCLK_USBH, NULL, "usb-host"),
148 ALIAS(UCLK, NULL, "usb-bus-host"),
149 ALIAS(UCLK, NULL, "usb-bus-gadget"),
150 ALIAS(ARMCLK, NULL, "armclk"),
151 ALIAS(UCLK, NULL, "uclk"),
152 ALIAS(HCLK, NULL, "hclk"),
153 ALIAS(MPLL, NULL, "mpll"),
154 ALIAS(FCLK, NULL, "fclk"),
157 /* S3C2410 specific clocks */
159 static struct samsung_pll_rate_table pll_s3c2410_12mhz_tbl[] __initdata = {
160 /* sorted in descending order */
162 PLL_35XX_RATE(270000000, 127, 1, 1),
163 PLL_35XX_RATE(268000000, 126, 1, 1),
164 PLL_35XX_RATE(266000000, 125, 1, 1),
165 PLL_35XX_RATE(226000000, 105, 1, 1),
166 PLL_35XX_RATE(210000000, 132, 2, 1),
168 PLL_35XX_RATE(203000000, 161, 3, 1),
169 PLL_35XX_RATE(192000000, 88, 1, 1),
170 PLL_35XX_RATE(186000000, 85, 1, 1),
171 PLL_35XX_RATE(180000000, 82, 1, 1),
172 PLL_35XX_RATE(170000000, 77, 1, 1),
173 PLL_35XX_RATE(158000000, 71, 1, 1),
174 PLL_35XX_RATE(152000000, 68, 1, 1),
175 PLL_35XX_RATE(147000000, 90, 2, 1),
176 PLL_35XX_RATE(135000000, 82, 2, 1),
177 PLL_35XX_RATE(124000000, 116, 1, 2),
178 PLL_35XX_RATE(118000000, 150, 2, 2),
179 PLL_35XX_RATE(113000000, 105, 1, 2),
180 PLL_35XX_RATE(101000000, 127, 2, 2),
181 PLL_35XX_RATE(90000000, 112, 2, 2),
182 PLL_35XX_RATE(85000000, 105, 2, 2),
183 PLL_35XX_RATE(79000000, 71, 1, 2),
184 PLL_35XX_RATE(68000000, 82, 2, 2),
185 PLL_35XX_RATE(56000000, 142, 2, 3),
186 PLL_35XX_RATE(48000000, 120, 2, 3),
187 PLL_35XX_RATE(51000000, 161, 3, 3),
188 PLL_35XX_RATE(45000000, 82, 1, 3),
189 PLL_35XX_RATE(34000000, 82, 2, 3),
193 static struct samsung_pll_clock s3c2410_plls[] __initdata = {
194 [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
195 LOCKTIME, MPLLCON, NULL),
196 [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
197 LOCKTIME, UPLLCON, NULL),
200 struct samsung_div_clock s3c2410_dividers[] __initdata = {
201 DIV(HCLK, "hclk", "mpll", CLKDIVN, 1, 1),
204 struct samsung_fixed_factor_clock s3c2410_ffactor[] __initdata = {
206 * armclk is directly supplied by the fclk, without
207 * switching possibility like on the s3c244x below.
209 FFACTOR(ARMCLK, "armclk", "fclk", 1, 1, 0),
211 /* uclk is fed from the unmodified upll */
212 FFACTOR(UCLK, "uclk", "upll", 1, 1, 0),
215 struct samsung_clock_alias s3c2410_aliases[] __initdata = {
216 ALIAS(PCLK_UART0, "s3c2410-uart.0", "uart"),
217 ALIAS(PCLK_UART1, "s3c2410-uart.1", "uart"),
218 ALIAS(PCLK_UART2, "s3c2410-uart.2", "uart"),
219 ALIAS(PCLK_UART0, "s3c2410-uart.0", "clk_uart_baud0"),
220 ALIAS(PCLK_UART1, "s3c2410-uart.1", "clk_uart_baud0"),
221 ALIAS(PCLK_UART2, "s3c2410-uart.2", "clk_uart_baud0"),
222 ALIAS(UCLK, NULL, "clk_uart_baud1"),
225 /* S3C244x specific clocks */
227 static struct samsung_pll_rate_table pll_s3c244x_12mhz_tbl[] __initdata = {
228 /* sorted in descending order */
229 PLL_35XX_RATE(400000000, 0x5c, 1, 1),
230 PLL_35XX_RATE(390000000, 0x7a, 2, 1),
231 PLL_35XX_RATE(380000000, 0x57, 1, 1),
232 PLL_35XX_RATE(370000000, 0xb1, 4, 1),
233 PLL_35XX_RATE(360000000, 0x70, 2, 1),
234 PLL_35XX_RATE(350000000, 0xa7, 4, 1),
235 PLL_35XX_RATE(340000000, 0x4d, 1, 1),
236 PLL_35XX_RATE(330000000, 0x66, 2, 1),
237 PLL_35XX_RATE(320000000, 0x98, 4, 1),
238 PLL_35XX_RATE(310000000, 0x93, 4, 1),
239 PLL_35XX_RATE(300000000, 0x75, 3, 1),
240 PLL_35XX_RATE(240000000, 0x70, 1, 2),
241 PLL_35XX_RATE(230000000, 0x6b, 1, 2),
242 PLL_35XX_RATE(220000000, 0x66, 1, 2),
243 PLL_35XX_RATE(210000000, 0x84, 2, 2),
244 PLL_35XX_RATE(200000000, 0x5c, 1, 2),
245 PLL_35XX_RATE(190000000, 0x57, 1, 2),
246 PLL_35XX_RATE(180000000, 0x70, 2, 2),
247 PLL_35XX_RATE(170000000, 0x4d, 1, 2),
248 PLL_35XX_RATE(160000000, 0x98, 4, 2),
249 PLL_35XX_RATE(150000000, 0x75, 3, 2),
250 PLL_35XX_RATE(120000000, 0x70, 1, 3),
251 PLL_35XX_RATE(110000000, 0x66, 1, 3),
252 PLL_35XX_RATE(100000000, 0x5c, 1, 3),
253 PLL_35XX_RATE(90000000, 0x70, 2, 3),
254 PLL_35XX_RATE(80000000, 0x98, 4, 3),
255 PLL_35XX_RATE(75000000, 0x75, 3, 3),
259 static struct samsung_pll_clock s3c244x_common_plls[] __initdata = {
260 [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
261 LOCKTIME, MPLLCON, NULL),
262 [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
263 LOCKTIME, UPLLCON, NULL),
266 PNAME(hclk_p) = { "fclk", "div_hclk_2", "div_hclk_4", "div_hclk_3" };
267 PNAME(armclk_p) = { "fclk", "hclk" };
269 struct samsung_mux_clock s3c244x_common_muxes[] __initdata = {
270 MUX(HCLK, "hclk", hclk_p, CLKDIVN, 1, 2),
271 MUX(ARMCLK, "armclk", armclk_p, CAMDIVN, 12, 1),
274 struct samsung_fixed_factor_clock s3c244x_common_ffactor[] __initdata = {
275 FFACTOR(0, "div_hclk_2", "fclk", 1, 2, 0),
276 FFACTOR(0, "ff_cam", "div_cam", 2, 1, CLK_SET_RATE_PARENT),
279 static struct clk_div_table div_hclk_4_d[] = {
280 { .val = 0, .div = 4 },
281 { .val = 1, .div = 8 },
285 static struct clk_div_table div_hclk_3_d[] = {
286 { .val = 0, .div = 3 },
287 { .val = 1, .div = 6 },
291 struct samsung_div_clock s3c244x_common_dividers[] __initdata = {
292 DIV(UCLK, "uclk", "upll", CLKDIVN, 3, 1),
293 DIV(0, "div_hclk", "fclk", CLKDIVN, 1, 1),
294 DIV_T(0, "div_hclk_4", "fclk", CAMDIVN, 9, 1, div_hclk_4_d),
295 DIV_T(0, "div_hclk_3", "fclk", CAMDIVN, 8, 1, div_hclk_3_d),
296 DIV(0, "div_cam", "upll", CAMDIVN, 0, 3),
299 struct samsung_gate_clock s3c244x_common_gates[] __initdata = {
300 GATE(HCLK_CAM, "cam", "hclk", CLKCON, 19, 0, 0),
303 struct samsung_clock_alias s3c244x_common_aliases[] __initdata = {
304 ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
305 ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
306 ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
307 ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
308 ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
309 ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
310 ALIAS(HCLK_CAM, NULL, "camif"),
311 ALIAS(CAMIF, NULL, "camif-upll"),
314 /* S3C2440 specific clocks */
316 PNAME(s3c2440_camif_p) = { "upll", "ff_cam" };
318 struct samsung_mux_clock s3c2440_muxes[] __initdata = {
319 MUX(CAMIF, "camif", s3c2440_camif_p, CAMDIVN, 4, 1),
322 struct samsung_gate_clock s3c2440_gates[] __initdata = {
323 GATE(PCLK_AC97, "ac97", "pclk", CLKCON, 20, 0, 0),
326 /* S3C2442 specific clocks */
328 struct samsung_fixed_factor_clock s3c2442_ffactor[] __initdata = {
329 FFACTOR(0, "upll_3", "upll", 1, 3, 0),
332 PNAME(s3c2442_camif_p) = { "upll", "ff_cam", "upll", "upll_3" };
334 struct samsung_mux_clock s3c2442_muxes[] __initdata = {
335 MUX(CAMIF, "camif", s3c2442_camif_p, CAMDIVN, 4, 2),
339 * fixed rate clocks generated outside the soc
340 * Only necessary until the devicetree-move is complete
343 struct samsung_fixed_rate_clock s3c2410_common_frate_clks[] __initdata = {
344 FRATE(XTI, "xti", NULL, CLK_IS_ROOT, 0),
347 static void __init s3c2410_common_clk_register_fixed_ext(
348 struct samsung_clk_provider *ctx,
351 struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
353 s3c2410_common_frate_clks[0].fixed_rate = xti_f;
354 samsung_clk_register_fixed_rate(ctx, s3c2410_common_frate_clks,
355 ARRAY_SIZE(s3c2410_common_frate_clks));
357 samsung_clk_register_alias(ctx, &xti_alias, 1);
360 void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
364 struct samsung_clk_provider *ctx;
368 reg_base = of_iomap(np, 0);
370 panic("%s: failed to map registers\n", __func__);
373 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
375 panic("%s: unable to allocate context.\n", __func__);
377 /* Register external clocks only in non-dt cases */
379 s3c2410_common_clk_register_fixed_ext(ctx, xti_f);
381 if (current_soc == 2410) {
382 if (_get_rate("xti") == 12 * MHZ) {
383 s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;
384 s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;
388 samsung_clk_register_pll(ctx, s3c2410_plls,
389 ARRAY_SIZE(s3c2410_plls), reg_base);
391 } else { /* S3C2440, S3C2442 */
392 if (_get_rate("xti") == 12 * MHZ) {
394 * plls follow different calculation schemes, with the
395 * upll following the same scheme as the s3c2410 plls
397 s3c244x_common_plls[mpll].rate_table =
398 pll_s3c244x_12mhz_tbl;
399 s3c244x_common_plls[upll].rate_table =
400 pll_s3c2410_12mhz_tbl;
404 samsung_clk_register_pll(ctx, s3c244x_common_plls,
405 ARRAY_SIZE(s3c244x_common_plls), reg_base);
408 /* Register common internal clocks. */
409 samsung_clk_register_mux(ctx, s3c2410_common_muxes,
410 ARRAY_SIZE(s3c2410_common_muxes));
411 samsung_clk_register_div(ctx, s3c2410_common_dividers,
412 ARRAY_SIZE(s3c2410_common_dividers));
413 samsung_clk_register_gate(ctx, s3c2410_common_gates,
414 ARRAY_SIZE(s3c2410_common_gates));
416 if (current_soc == S3C2440 || current_soc == S3C2442) {
417 samsung_clk_register_div(ctx, s3c244x_common_dividers,
418 ARRAY_SIZE(s3c244x_common_dividers));
419 samsung_clk_register_gate(ctx, s3c244x_common_gates,
420 ARRAY_SIZE(s3c244x_common_gates));
421 samsung_clk_register_mux(ctx, s3c244x_common_muxes,
422 ARRAY_SIZE(s3c244x_common_muxes));
423 samsung_clk_register_fixed_factor(ctx, s3c244x_common_ffactor,
424 ARRAY_SIZE(s3c244x_common_ffactor));
427 /* Register SoC-specific clocks. */
428 switch (current_soc) {
430 samsung_clk_register_div(ctx, s3c2410_dividers,
431 ARRAY_SIZE(s3c2410_dividers));
432 samsung_clk_register_fixed_factor(ctx, s3c2410_ffactor,
433 ARRAY_SIZE(s3c2410_ffactor));
434 samsung_clk_register_alias(ctx, s3c2410_aliases,
435 ARRAY_SIZE(s3c2410_common_aliases));
438 samsung_clk_register_mux(ctx, s3c2440_muxes,
439 ARRAY_SIZE(s3c2440_muxes));
440 samsung_clk_register_gate(ctx, s3c2440_gates,
441 ARRAY_SIZE(s3c2440_gates));
444 samsung_clk_register_mux(ctx, s3c2442_muxes,
445 ARRAY_SIZE(s3c2442_muxes));
446 samsung_clk_register_fixed_factor(ctx, s3c2442_ffactor,
447 ARRAY_SIZE(s3c2442_ffactor));
452 * Register common aliases at the end, as some of the aliased clocks
455 samsung_clk_register_alias(ctx, s3c2410_common_aliases,
456 ARRAY_SIZE(s3c2410_common_aliases));
458 if (current_soc == S3C2440 || current_soc == S3C2442) {
459 samsung_clk_register_alias(ctx, s3c244x_common_aliases,
460 ARRAY_SIZE(s3c244x_common_aliases));
463 s3c2410_clk_sleep_init();
466 static void __init s3c2410_clk_init(struct device_node *np)
468 s3c2410_common_clk_init(np, 0, S3C2410, 0);
470 CLK_OF_DECLARE(s3c2410_clk, "samsung,s3c2410-clock", s3c2410_clk_init);
472 static void __init s3c2440_clk_init(struct device_node *np)
474 s3c2410_common_clk_init(np, 0, S3C2440, 0);
476 CLK_OF_DECLARE(s3c2440_clk, "samsung,s3c2440-clock", s3c2440_clk_init);
478 static void __init s3c2442_clk_init(struct device_node *np)
480 s3c2410_common_clk_init(np, 0, S3C2442, 0);
482 CLK_OF_DECLARE(s3c2442_clk, "samsung,s3c2442-clock", s3c2442_clk_init);