2 * arch/arm/mach-spear13xx/spear1310_clock.c
4 * SPEAr1310 machine clock framework source file
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <viresh.linux@gmail.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/clkdev.h>
16 #include <linux/err.h>
18 #include <linux/of_platform.h>
19 #include <linux/spinlock_types.h>
22 /* PLL related registers and bit values */
23 #define SPEAR1310_PLL_CFG (misc_base + 0x210)
24 /* PLL_CFG bit values */
25 #define SPEAR1310_CLCD_SYNT_CLK_MASK 1
26 #define SPEAR1310_CLCD_SYNT_CLK_SHIFT 31
27 #define SPEAR1310_RAS_SYNT2_3_CLK_MASK 2
28 #define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT 29
29 #define SPEAR1310_RAS_SYNT_CLK_MASK 2
30 #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT 27
31 #define SPEAR1310_PLL_CLK_MASK 2
32 #define SPEAR1310_PLL3_CLK_SHIFT 24
33 #define SPEAR1310_PLL2_CLK_SHIFT 22
34 #define SPEAR1310_PLL1_CLK_SHIFT 20
36 #define SPEAR1310_PLL1_CTR (misc_base + 0x214)
37 #define SPEAR1310_PLL1_FRQ (misc_base + 0x218)
38 #define SPEAR1310_PLL2_CTR (misc_base + 0x220)
39 #define SPEAR1310_PLL2_FRQ (misc_base + 0x224)
40 #define SPEAR1310_PLL3_CTR (misc_base + 0x22C)
41 #define SPEAR1310_PLL3_FRQ (misc_base + 0x230)
42 #define SPEAR1310_PLL4_CTR (misc_base + 0x238)
43 #define SPEAR1310_PLL4_FRQ (misc_base + 0x23C)
44 #define SPEAR1310_PERIP_CLK_CFG (misc_base + 0x244)
45 /* PERIP_CLK_CFG bit values */
46 #define SPEAR1310_GPT_OSC24_VAL 0
47 #define SPEAR1310_GPT_APB_VAL 1
48 #define SPEAR1310_GPT_CLK_MASK 1
49 #define SPEAR1310_GPT3_CLK_SHIFT 11
50 #define SPEAR1310_GPT2_CLK_SHIFT 10
51 #define SPEAR1310_GPT1_CLK_SHIFT 9
52 #define SPEAR1310_GPT0_CLK_SHIFT 8
53 #define SPEAR1310_UART_CLK_PLL5_VAL 0
54 #define SPEAR1310_UART_CLK_OSC24_VAL 1
55 #define SPEAR1310_UART_CLK_SYNT_VAL 2
56 #define SPEAR1310_UART_CLK_MASK 2
57 #define SPEAR1310_UART_CLK_SHIFT 4
59 #define SPEAR1310_AUX_CLK_PLL5_VAL 0
60 #define SPEAR1310_AUX_CLK_SYNT_VAL 1
61 #define SPEAR1310_CLCD_CLK_MASK 2
62 #define SPEAR1310_CLCD_CLK_SHIFT 2
63 #define SPEAR1310_C3_CLK_MASK 1
64 #define SPEAR1310_C3_CLK_SHIFT 1
66 #define SPEAR1310_GMAC_CLK_CFG (misc_base + 0x248)
67 #define SPEAR1310_GMAC_PHY_IF_SEL_MASK 3
68 #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT 4
69 #define SPEAR1310_GMAC_PHY_CLK_MASK 1
70 #define SPEAR1310_GMAC_PHY_CLK_SHIFT 3
71 #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2
72 #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1
74 #define SPEAR1310_I2S_CLK_CFG (misc_base + 0x24C)
75 /* I2S_CLK_CFG register mask */
76 #define SPEAR1310_I2S_SCLK_X_MASK 0x1F
77 #define SPEAR1310_I2S_SCLK_X_SHIFT 27
78 #define SPEAR1310_I2S_SCLK_Y_MASK 0x1F
79 #define SPEAR1310_I2S_SCLK_Y_SHIFT 22
80 #define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT 21
81 #define SPEAR1310_I2S_SCLK_SYNTH_ENB 20
82 #define SPEAR1310_I2S_PRS1_CLK_X_MASK 0xFF
83 #define SPEAR1310_I2S_PRS1_CLK_X_SHIFT 12
84 #define SPEAR1310_I2S_PRS1_CLK_Y_MASK 0xFF
85 #define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT 4
86 #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT 3
87 #define SPEAR1310_I2S_REF_SEL_MASK 1
88 #define SPEAR1310_I2S_REF_SHIFT 2
89 #define SPEAR1310_I2S_SRC_CLK_MASK 2
90 #define SPEAR1310_I2S_SRC_CLK_SHIFT 0
92 #define SPEAR1310_C3_CLK_SYNT (misc_base + 0x250)
93 #define SPEAR1310_UART_CLK_SYNT (misc_base + 0x254)
94 #define SPEAR1310_GMAC_CLK_SYNT (misc_base + 0x258)
95 #define SPEAR1310_SDHCI_CLK_SYNT (misc_base + 0x25C)
96 #define SPEAR1310_CFXD_CLK_SYNT (misc_base + 0x260)
97 #define SPEAR1310_ADC_CLK_SYNT (misc_base + 0x264)
98 #define SPEAR1310_AMBA_CLK_SYNT (misc_base + 0x268)
99 #define SPEAR1310_CLCD_CLK_SYNT (misc_base + 0x270)
100 #define SPEAR1310_RAS_CLK_SYNT0 (misc_base + 0x280)
101 #define SPEAR1310_RAS_CLK_SYNT1 (misc_base + 0x288)
102 #define SPEAR1310_RAS_CLK_SYNT2 (misc_base + 0x290)
103 #define SPEAR1310_RAS_CLK_SYNT3 (misc_base + 0x298)
104 /* Check Fractional synthesizer reg masks */
106 #define SPEAR1310_PERIP1_CLK_ENB (misc_base + 0x300)
107 /* PERIP1_CLK_ENB register masks */
108 #define SPEAR1310_RTC_CLK_ENB 31
109 #define SPEAR1310_ADC_CLK_ENB 30
110 #define SPEAR1310_C3_CLK_ENB 29
111 #define SPEAR1310_JPEG_CLK_ENB 28
112 #define SPEAR1310_CLCD_CLK_ENB 27
113 #define SPEAR1310_DMA_CLK_ENB 25
114 #define SPEAR1310_GPIO1_CLK_ENB 24
115 #define SPEAR1310_GPIO0_CLK_ENB 23
116 #define SPEAR1310_GPT1_CLK_ENB 22
117 #define SPEAR1310_GPT0_CLK_ENB 21
118 #define SPEAR1310_I2S0_CLK_ENB 20
119 #define SPEAR1310_I2S1_CLK_ENB 19
120 #define SPEAR1310_I2C0_CLK_ENB 18
121 #define SPEAR1310_SSP_CLK_ENB 17
122 #define SPEAR1310_UART_CLK_ENB 15
123 #define SPEAR1310_PCIE_SATA_2_CLK_ENB 14
124 #define SPEAR1310_PCIE_SATA_1_CLK_ENB 13
125 #define SPEAR1310_PCIE_SATA_0_CLK_ENB 12
126 #define SPEAR1310_UOC_CLK_ENB 11
127 #define SPEAR1310_UHC1_CLK_ENB 10
128 #define SPEAR1310_UHC0_CLK_ENB 9
129 #define SPEAR1310_GMAC_CLK_ENB 8
130 #define SPEAR1310_CFXD_CLK_ENB 7
131 #define SPEAR1310_SDHCI_CLK_ENB 6
132 #define SPEAR1310_SMI_CLK_ENB 5
133 #define SPEAR1310_FSMC_CLK_ENB 4
134 #define SPEAR1310_SYSRAM0_CLK_ENB 3
135 #define SPEAR1310_SYSRAM1_CLK_ENB 2
136 #define SPEAR1310_SYSROM_CLK_ENB 1
137 #define SPEAR1310_BUS_CLK_ENB 0
139 #define SPEAR1310_PERIP2_CLK_ENB (misc_base + 0x304)
140 /* PERIP2_CLK_ENB register masks */
141 #define SPEAR1310_THSENS_CLK_ENB 8
142 #define SPEAR1310_I2S_REF_PAD_CLK_ENB 7
143 #define SPEAR1310_ACP_CLK_ENB 6
144 #define SPEAR1310_GPT3_CLK_ENB 5
145 #define SPEAR1310_GPT2_CLK_ENB 4
146 #define SPEAR1310_KBD_CLK_ENB 3
147 #define SPEAR1310_CPU_DBG_CLK_ENB 2
148 #define SPEAR1310_DDR_CORE_CLK_ENB 1
149 #define SPEAR1310_DDR_CTRL_CLK_ENB 0
151 #define SPEAR1310_RAS_CLK_ENB (misc_base + 0x310)
152 /* RAS_CLK_ENB register masks */
153 #define SPEAR1310_SYNT3_CLK_ENB 17
154 #define SPEAR1310_SYNT2_CLK_ENB 16
155 #define SPEAR1310_SYNT1_CLK_ENB 15
156 #define SPEAR1310_SYNT0_CLK_ENB 14
157 #define SPEAR1310_PCLK3_CLK_ENB 13
158 #define SPEAR1310_PCLK2_CLK_ENB 12
159 #define SPEAR1310_PCLK1_CLK_ENB 11
160 #define SPEAR1310_PCLK0_CLK_ENB 10
161 #define SPEAR1310_PLL3_CLK_ENB 9
162 #define SPEAR1310_PLL2_CLK_ENB 8
163 #define SPEAR1310_C125M_PAD_CLK_ENB 7
164 #define SPEAR1310_C30M_CLK_ENB 6
165 #define SPEAR1310_C48M_CLK_ENB 5
166 #define SPEAR1310_OSC_25M_CLK_ENB 4
167 #define SPEAR1310_OSC_32K_CLK_ENB 3
168 #define SPEAR1310_OSC_24M_CLK_ENB 2
169 #define SPEAR1310_PCLK_CLK_ENB 1
170 #define SPEAR1310_ACLK_CLK_ENB 0
172 /* RAS Area Control Register */
173 #define SPEAR1310_RAS_CTRL_REG0 (ras_base + 0x000)
174 #define SPEAR1310_SSP1_CLK_MASK 3
175 #define SPEAR1310_SSP1_CLK_SHIFT 26
176 #define SPEAR1310_TDM_CLK_MASK 1
177 #define SPEAR1310_TDM2_CLK_SHIFT 24
178 #define SPEAR1310_TDM1_CLK_SHIFT 23
179 #define SPEAR1310_I2C_CLK_MASK 1
180 #define SPEAR1310_I2C7_CLK_SHIFT 22
181 #define SPEAR1310_I2C6_CLK_SHIFT 21
182 #define SPEAR1310_I2C5_CLK_SHIFT 20
183 #define SPEAR1310_I2C4_CLK_SHIFT 19
184 #define SPEAR1310_I2C3_CLK_SHIFT 18
185 #define SPEAR1310_I2C2_CLK_SHIFT 17
186 #define SPEAR1310_I2C1_CLK_SHIFT 16
187 #define SPEAR1310_GPT64_CLK_MASK 1
188 #define SPEAR1310_GPT64_CLK_SHIFT 15
189 #define SPEAR1310_RAS_UART_CLK_MASK 1
190 #define SPEAR1310_UART5_CLK_SHIFT 14
191 #define SPEAR1310_UART4_CLK_SHIFT 13
192 #define SPEAR1310_UART3_CLK_SHIFT 12
193 #define SPEAR1310_UART2_CLK_SHIFT 11
194 #define SPEAR1310_UART1_CLK_SHIFT 10
195 #define SPEAR1310_PCI_CLK_MASK 1
196 #define SPEAR1310_PCI_CLK_SHIFT 0
198 #define SPEAR1310_RAS_CTRL_REG1 (ras_base + 0x004)
199 #define SPEAR1310_PHY_CLK_MASK 0x3
200 #define SPEAR1310_RMII_PHY_CLK_SHIFT 0
201 #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2
203 #define SPEAR1310_RAS_SW_CLK_CTRL (ras_base + 0x0148)
204 #define SPEAR1310_CAN1_CLK_ENB 25
205 #define SPEAR1310_CAN0_CLK_ENB 24
206 #define SPEAR1310_GPT64_CLK_ENB 23
207 #define SPEAR1310_SSP1_CLK_ENB 22
208 #define SPEAR1310_I2C7_CLK_ENB 21
209 #define SPEAR1310_I2C6_CLK_ENB 20
210 #define SPEAR1310_I2C5_CLK_ENB 19
211 #define SPEAR1310_I2C4_CLK_ENB 18
212 #define SPEAR1310_I2C3_CLK_ENB 17
213 #define SPEAR1310_I2C2_CLK_ENB 16
214 #define SPEAR1310_I2C1_CLK_ENB 15
215 #define SPEAR1310_UART5_CLK_ENB 14
216 #define SPEAR1310_UART4_CLK_ENB 13
217 #define SPEAR1310_UART3_CLK_ENB 12
218 #define SPEAR1310_UART2_CLK_ENB 11
219 #define SPEAR1310_UART1_CLK_ENB 10
220 #define SPEAR1310_RS485_1_CLK_ENB 9
221 #define SPEAR1310_RS485_0_CLK_ENB 8
222 #define SPEAR1310_TDM2_CLK_ENB 7
223 #define SPEAR1310_TDM1_CLK_ENB 6
224 #define SPEAR1310_PCI_CLK_ENB 5
225 #define SPEAR1310_GMII_CLK_ENB 4
226 #define SPEAR1310_MII2_CLK_ENB 3
227 #define SPEAR1310_MII1_CLK_ENB 2
228 #define SPEAR1310_MII0_CLK_ENB 1
229 #define SPEAR1310_ESRAM_CLK_ENB 0
231 static DEFINE_SPINLOCK(_lock);
233 /* pll rate configuration table, in ascending order of rates */
234 static struct pll_rate_tbl pll_rtbl[] = {
236 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
237 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
238 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
239 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
240 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
241 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
242 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
245 /* vco-pll4 rate configuration table, in ascending order of rates */
246 static struct pll_rate_tbl pll4_rtbl[] = {
247 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
248 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
249 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
250 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
253 /* aux rate configuration table, in ascending order of rates */
254 static struct aux_rate_tbl aux_rtbl[] = {
255 /* For VCO1div2 = 500 MHz */
256 {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
257 {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
258 {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
259 {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
260 {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
261 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
264 /* gmac rate configuration table, in ascending order of rates */
265 static struct aux_rate_tbl gmac_rtbl[] = {
266 /* For gmac phy input clk */
267 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
268 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
269 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
270 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
273 /* clcd rate configuration table, in ascending order of rates */
274 static struct frac_rate_tbl clcd_rtbl[] = {
275 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
276 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
277 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
278 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
279 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
280 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
281 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
282 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
283 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
284 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
287 /* i2s prescaler1 masks */
288 static struct aux_clk_masks i2s_prs1_masks = {
289 .eq_sel_mask = AUX_EQ_SEL_MASK,
290 .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT,
291 .eq1_mask = AUX_EQ1_SEL,
292 .eq2_mask = AUX_EQ2_SEL,
293 .xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK,
294 .xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT,
295 .yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK,
296 .yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT,
299 /* i2s sclk (bit clock) syynthesizers masks */
300 static struct aux_clk_masks i2s_sclk_masks = {
301 .eq_sel_mask = AUX_EQ_SEL_MASK,
302 .eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT,
303 .eq1_mask = AUX_EQ1_SEL,
304 .eq2_mask = AUX_EQ2_SEL,
305 .xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK,
306 .xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT,
307 .yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK,
308 .yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT,
309 .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB,
312 /* i2s prs1 aux rate configuration table, in ascending order of rates */
313 static struct aux_rate_tbl i2s_prs1_rtbl[] = {
314 /* For parent clk = 49.152 MHz */
315 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
316 {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
317 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
318 {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
321 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
322 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
324 {.xscale = 1, .yscale = 3, .eq = 0},
326 /* For parent clk = 49.152 MHz */
327 {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
329 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
332 /* i2s sclk aux rate configuration table, in ascending order of rates */
333 static struct aux_rate_tbl i2s_sclk_rtbl[] = {
334 /* For i2s_ref_clk = 12.288MHz */
335 {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */
336 {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
339 /* adc rate configuration table, in ascending order of rates */
340 /* possible adc range is 2.5 MHz to 20 MHz. */
341 static struct aux_rate_tbl adc_rtbl[] = {
342 /* For ahb = 166.67 MHz */
343 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
344 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
345 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
346 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
349 /* General synth rate configuration table, in ascending order of rates */
350 static struct frac_rate_tbl gen_rtbl[] = {
351 /* For vco1div4 = 250 MHz */
352 {.div = 0x14000}, /* 25 MHz */
353 {.div = 0x0A000}, /* 50 MHz */
354 {.div = 0x05000}, /* 100 MHz */
355 {.div = 0x02000}, /* 250 MHz */
359 static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
360 static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
361 static const char *uart0_parents[] = { "pll5_clk", "uart_syn_gclk", };
362 static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", };
363 static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk",
365 static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", };
366 static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
367 static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", };
368 static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk",
369 "i2s_src_pad_clk", };
370 static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", };
371 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
373 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
375 static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none",
376 "ras_pll2_clk", "ras_syn0_clk", };
377 static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk",
378 "ras_pll2_clk", "ras_syn0_clk", };
379 static const char *uart_parents[] = { "ras_apb_clk", "gen_syn3_clk", };
380 static const char *i2c_parents[] = { "ras_apb_clk", "gen_syn1_clk", };
381 static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk",
383 static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", };
384 static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", };
386 void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
388 struct clk *clk, *clk1;
390 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
392 clk_register_clkdev(clk, "osc_32k_clk", NULL);
394 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
396 clk_register_clkdev(clk, "osc_24m_clk", NULL);
398 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
400 clk_register_clkdev(clk, "osc_25m_clk", NULL);
402 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT,
404 clk_register_clkdev(clk, "gmii_pad_clk", NULL);
406 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
407 CLK_IS_ROOT, 12288000);
408 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
410 /* clock derived from 32 KHz osc clk */
411 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
412 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0,
414 clk_register_clkdev(clk, NULL, "e0580000.rtc");
416 /* clock derived from 24 or 25 MHz osc clk */
418 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
419 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
420 SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
422 clk_register_clkdev(clk, "vco1_mclk", NULL);
423 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk",
424 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
425 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
426 clk_register_clkdev(clk, "vco1_clk", NULL);
427 clk_register_clkdev(clk1, "pll1_clk", NULL);
429 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
430 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
431 SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
433 clk_register_clkdev(clk, "vco2_mclk", NULL);
434 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk",
435 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
436 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
437 clk_register_clkdev(clk, "vco2_clk", NULL);
438 clk_register_clkdev(clk1, "pll2_clk", NULL);
440 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
441 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
442 SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
444 clk_register_clkdev(clk, "vco3_mclk", NULL);
445 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk",
446 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
447 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
448 clk_register_clkdev(clk, "vco3_clk", NULL);
449 clk_register_clkdev(clk1, "pll3_clk", NULL);
451 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
452 0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl,
453 ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
454 clk_register_clkdev(clk, "vco4_clk", NULL);
455 clk_register_clkdev(clk1, "pll4_clk", NULL);
457 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
459 clk_register_clkdev(clk, "pll5_clk", NULL);
461 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
463 clk_register_clkdev(clk, "pll6_clk", NULL);
465 /* vco div n clocks */
466 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
468 clk_register_clkdev(clk, "vco1div2_clk", NULL);
470 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
472 clk_register_clkdev(clk, "vco1div4_clk", NULL);
474 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
476 clk_register_clkdev(clk, "vco2div2_clk", NULL);
478 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
480 clk_register_clkdev(clk, "vco3div2_clk", NULL);
483 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
485 clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0,
486 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0,
488 clk_register_clkdev(clk, NULL, "spear_thermal");
490 /* clock derived from pll4 clk */
491 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
493 clk_register_clkdev(clk, "ddr_clk", NULL);
495 /* clock derived from pll1 clk */
496 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
497 CLK_SET_RATE_PARENT, 1, 2);
498 clk_register_clkdev(clk, "cpu_clk", NULL);
500 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
502 clk_register_clkdev(clk, NULL, "ec800620.wdt");
504 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
506 clk_register_clkdev(clk, NULL, "smp_twd");
508 clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
510 clk_register_clkdev(clk, "ahb_clk", NULL);
512 clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1,
514 clk_register_clkdev(clk, "apb_clk", NULL);
517 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
518 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
519 SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
521 clk_register_clkdev(clk, "gpt0_mclk", NULL);
522 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
523 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
525 clk_register_clkdev(clk, NULL, "gpt0");
527 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
528 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
529 SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
531 clk_register_clkdev(clk, "gpt1_mclk", NULL);
532 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
533 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
535 clk_register_clkdev(clk, NULL, "gpt1");
537 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
538 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
539 SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
541 clk_register_clkdev(clk, "gpt2_mclk", NULL);
542 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
543 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
545 clk_register_clkdev(clk, NULL, "gpt2");
547 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
548 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
549 SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
551 clk_register_clkdev(clk, "gpt3_mclk", NULL);
552 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
553 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
555 clk_register_clkdev(clk, NULL, "gpt3");
558 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk",
559 0, SPEAR1310_UART_CLK_SYNT, NULL, aux_rtbl,
560 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
561 clk_register_clkdev(clk, "uart_syn_clk", NULL);
562 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
564 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
565 ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT,
566 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT,
567 SPEAR1310_UART_CLK_MASK, 0, &_lock);
568 clk_register_clkdev(clk, "uart0_mclk", NULL);
570 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk",
571 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
572 SPEAR1310_UART_CLK_ENB, 0, &_lock);
573 clk_register_clkdev(clk, NULL, "e0000000.serial");
575 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
576 "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL,
577 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
578 clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
579 clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
581 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk",
582 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
583 SPEAR1310_SDHCI_CLK_ENB, 0, &_lock);
584 clk_register_clkdev(clk, NULL, "b3000000.sdhci");
586 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
587 0, SPEAR1310_CFXD_CLK_SYNT, NULL, aux_rtbl,
588 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
589 clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
590 clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
592 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk",
593 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
594 SPEAR1310_CFXD_CLK_ENB, 0, &_lock);
595 clk_register_clkdev(clk, NULL, "b2800000.cf");
596 clk_register_clkdev(clk, NULL, "arasan_xd");
598 clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk",
599 0, SPEAR1310_C3_CLK_SYNT, NULL, aux_rtbl,
600 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
601 clk_register_clkdev(clk, "c3_syn_clk", NULL);
602 clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
604 clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
605 ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT,
606 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT,
607 SPEAR1310_C3_CLK_MASK, 0, &_lock);
608 clk_register_clkdev(clk, "c3_mclk", NULL);
610 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0,
611 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0,
613 clk_register_clkdev(clk, NULL, "c3");
616 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
617 ARRAY_SIZE(gmac_phy_input_parents), 0,
618 SPEAR1310_GMAC_CLK_CFG,
619 SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
620 SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
621 clk_register_clkdev(clk, "phy_input_mclk", NULL);
623 clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk",
624 0, SPEAR1310_GMAC_CLK_SYNT, NULL, gmac_rtbl,
625 ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
626 clk_register_clkdev(clk, "phy_syn_clk", NULL);
627 clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
629 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
630 ARRAY_SIZE(gmac_phy_parents), 0,
631 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
632 SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
633 clk_register_clkdev(clk, "stmmacphy.0", NULL);
636 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
637 ARRAY_SIZE(clcd_synth_parents), 0,
638 SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT,
639 SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
640 clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
642 clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
643 SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl,
644 ARRAY_SIZE(clcd_rtbl), &_lock);
645 clk_register_clkdev(clk, "clcd_syn_clk", NULL);
647 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
648 ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT,
649 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
650 SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
651 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
653 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
654 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
656 clk_register_clkdev(clk, NULL, "e1000000.clcd");
659 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
660 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG,
661 SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK,
663 clk_register_clkdev(clk, "i2s_src_mclk", NULL);
665 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
666 SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
667 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
668 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
670 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
671 ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT,
672 SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT,
673 SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock);
674 clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
676 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
677 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB,
679 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
681 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk",
682 "i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG,
683 &i2s_sclk_masks, i2s_sclk_rtbl,
684 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
685 clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
686 clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL);
688 /* clock derived from ahb clk */
689 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
690 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0,
692 clk_register_clkdev(clk, NULL, "e0280000.i2c");
694 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
695 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0,
697 clk_register_clkdev(clk, NULL, "ea800000.dma");
698 clk_register_clkdev(clk, NULL, "eb000000.dma");
700 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0,
701 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0,
703 clk_register_clkdev(clk, NULL, "b2000000.jpeg");
705 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
706 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0,
708 clk_register_clkdev(clk, NULL, "e2000000.eth");
710 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
711 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0,
713 clk_register_clkdev(clk, NULL, "b0000000.flash");
715 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
716 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0,
718 clk_register_clkdev(clk, NULL, "ea000000.flash");
720 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
721 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0,
723 clk_register_clkdev(clk, NULL, "e4000000.ohci");
724 clk_register_clkdev(clk, NULL, "e4800000.ehci");
726 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
727 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0,
729 clk_register_clkdev(clk, NULL, "e5000000.ohci");
730 clk_register_clkdev(clk, NULL, "e5800000.ehci");
732 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
733 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0,
735 clk_register_clkdev(clk, NULL, "e3800000.otg");
737 clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
738 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
740 clk_register_clkdev(clk, NULL, "dw_pcie.0");
741 clk_register_clkdev(clk, NULL, "b1000000.ahci");
743 clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
744 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
746 clk_register_clkdev(clk, NULL, "dw_pcie.1");
747 clk_register_clkdev(clk, NULL, "b1800000.ahci");
749 clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
750 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
752 clk_register_clkdev(clk, NULL, "dw_pcie.2");
753 clk_register_clkdev(clk, NULL, "b4000000.ahci");
755 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
756 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0,
758 clk_register_clkdev(clk, "sysram0_clk", NULL);
760 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
761 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0,
763 clk_register_clkdev(clk, "sysram1_clk", NULL);
765 clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
766 0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl,
767 ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
768 clk_register_clkdev(clk, "adc_syn_clk", NULL);
769 clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
771 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk",
772 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
773 SPEAR1310_ADC_CLK_ENB, 0, &_lock);
774 clk_register_clkdev(clk, NULL, "e0080000.adc");
776 /* clock derived from apb clk */
777 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0,
778 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0,
780 clk_register_clkdev(clk, NULL, "e0100000.spi");
782 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
783 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0,
785 clk_register_clkdev(clk, NULL, "e0600000.gpio");
787 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
788 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0,
790 clk_register_clkdev(clk, NULL, "e0680000.gpio");
792 clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0,
793 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0,
795 clk_register_clkdev(clk, NULL, "e0180000.i2s");
797 clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0,
798 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0,
800 clk_register_clkdev(clk, NULL, "e0200000.i2s");
802 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
803 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0,
805 clk_register_clkdev(clk, NULL, "e0300000.kbd");
808 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
809 ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1310_PLL_CFG,
810 SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
811 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
812 clk_register_clkdev(clk, "gen_syn0_1_clk", NULL);
814 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
815 ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1310_PLL_CFG,
816 SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
817 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
818 clk_register_clkdev(clk, "gen_syn2_3_clk", NULL);
820 clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0,
821 SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
823 clk_register_clkdev(clk, "gen_syn0_clk", NULL);
825 clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0,
826 SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
828 clk_register_clkdev(clk, "gen_syn1_clk", NULL);
830 clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0,
831 SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
833 clk_register_clkdev(clk, "gen_syn2_clk", NULL);
835 clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0,
836 SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
838 clk_register_clkdev(clk, "gen_syn3_clk", NULL);
840 clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0,
841 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0,
843 clk_register_clkdev(clk, "ras_osc_24m_clk", NULL);
845 clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0,
846 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0,
848 clk_register_clkdev(clk, "ras_osc_25m_clk", NULL);
850 clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0,
851 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0,
853 clk_register_clkdev(clk, "ras_osc_32k_clk", NULL);
855 clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
856 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0,
858 clk_register_clkdev(clk, "ras_pll2_clk", NULL);
860 clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
861 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0,
863 clk_register_clkdev(clk, "ras_pll3_clk", NULL);
865 clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_pad_clk", 0,
866 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0,
868 clk_register_clkdev(clk, "ras_tx125_clk", NULL);
870 clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0,
872 clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0,
873 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0,
875 clk_register_clkdev(clk, "ras_30m_clk", NULL);
877 clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0,
879 clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0,
880 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0,
882 clk_register_clkdev(clk, "ras_48m_clk", NULL);
884 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0,
885 SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0,
887 clk_register_clkdev(clk, "ras_ahb_clk", NULL);
889 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0,
890 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0,
892 clk_register_clkdev(clk, "ras_apb_clk", NULL);
894 clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, CLK_IS_ROOT,
897 clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, CLK_IS_ROOT,
900 clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0,
901 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0,
903 clk_register_clkdev(clk, NULL, "c_can_platform.0");
905 clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0,
906 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0,
908 clk_register_clkdev(clk, NULL, "c_can_platform.1");
910 clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0,
911 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0,
913 clk_register_clkdev(clk, NULL, "5c400000.eth");
915 clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0,
916 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0,
918 clk_register_clkdev(clk, NULL, "5c500000.eth");
920 clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0,
921 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0,
923 clk_register_clkdev(clk, NULL, "5c600000.eth");
925 clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0,
926 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0,
928 clk_register_clkdev(clk, NULL, "5c700000.eth");
930 clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk",
931 smii_rgmii_phy_parents,
932 ARRAY_SIZE(smii_rgmii_phy_parents), 0,
933 SPEAR1310_RAS_CTRL_REG1,
934 SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
935 SPEAR1310_PHY_CLK_MASK, 0, &_lock);
936 clk_register_clkdev(clk, "stmmacphy.1", NULL);
937 clk_register_clkdev(clk, "stmmacphy.2", NULL);
938 clk_register_clkdev(clk, "stmmacphy.4", NULL);
940 clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents,
941 ARRAY_SIZE(rmii_phy_parents), 0,
942 SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
943 SPEAR1310_PHY_CLK_MASK, 0, &_lock);
944 clk_register_clkdev(clk, "stmmacphy.3", NULL);
946 clk = clk_register_mux(NULL, "uart1_mclk", uart_parents,
947 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
948 SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
950 clk_register_clkdev(clk, "uart1_mclk", NULL);
952 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
953 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0,
955 clk_register_clkdev(clk, NULL, "5c800000.serial");
957 clk = clk_register_mux(NULL, "uart2_mclk", uart_parents,
958 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
959 SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
961 clk_register_clkdev(clk, "uart2_mclk", NULL);
963 clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0,
964 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0,
966 clk_register_clkdev(clk, NULL, "5c900000.serial");
968 clk = clk_register_mux(NULL, "uart3_mclk", uart_parents,
969 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
970 SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
972 clk_register_clkdev(clk, "uart3_mclk", NULL);
974 clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0,
975 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0,
977 clk_register_clkdev(clk, NULL, "5ca00000.serial");
979 clk = clk_register_mux(NULL, "uart4_mclk", uart_parents,
980 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
981 SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
983 clk_register_clkdev(clk, "uart4_mclk", NULL);
985 clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0,
986 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0,
988 clk_register_clkdev(clk, NULL, "5cb00000.serial");
990 clk = clk_register_mux(NULL, "uart5_mclk", uart_parents,
991 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
992 SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
994 clk_register_clkdev(clk, "uart5_mclk", NULL);
996 clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0,
997 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0,
999 clk_register_clkdev(clk, NULL, "5cc00000.serial");
1001 clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents,
1002 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1003 SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1005 clk_register_clkdev(clk, "i2c1_mclk", NULL);
1007 clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0,
1008 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0,
1010 clk_register_clkdev(clk, NULL, "5cd00000.i2c");
1012 clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents,
1013 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1014 SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1016 clk_register_clkdev(clk, "i2c2_mclk", NULL);
1018 clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0,
1019 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0,
1021 clk_register_clkdev(clk, NULL, "5ce00000.i2c");
1023 clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents,
1024 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1025 SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1027 clk_register_clkdev(clk, "i2c3_mclk", NULL);
1029 clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0,
1030 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0,
1032 clk_register_clkdev(clk, NULL, "5cf00000.i2c");
1034 clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents,
1035 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1036 SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1038 clk_register_clkdev(clk, "i2c4_mclk", NULL);
1040 clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0,
1041 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0,
1043 clk_register_clkdev(clk, NULL, "5d000000.i2c");
1045 clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents,
1046 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1047 SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1049 clk_register_clkdev(clk, "i2c5_mclk", NULL);
1051 clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0,
1052 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0,
1054 clk_register_clkdev(clk, NULL, "5d100000.i2c");
1056 clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents,
1057 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1058 SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1060 clk_register_clkdev(clk, "i2c6_mclk", NULL);
1062 clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0,
1063 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0,
1065 clk_register_clkdev(clk, NULL, "5d200000.i2c");
1067 clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents,
1068 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1069 SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1071 clk_register_clkdev(clk, "i2c7_mclk", NULL);
1073 clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0,
1074 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0,
1076 clk_register_clkdev(clk, NULL, "5d300000.i2c");
1078 clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents,
1079 ARRAY_SIZE(ssp1_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1080 SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0,
1082 clk_register_clkdev(clk, "ssp1_mclk", NULL);
1084 clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0,
1085 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0,
1087 clk_register_clkdev(clk, NULL, "5d400000.spi");
1089 clk = clk_register_mux(NULL, "pci_mclk", pci_parents,
1090 ARRAY_SIZE(pci_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1091 SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0,
1093 clk_register_clkdev(clk, "pci_mclk", NULL);
1095 clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0,
1096 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0,
1098 clk_register_clkdev(clk, NULL, "pci");
1100 clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents,
1101 ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1102 SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
1104 clk_register_clkdev(clk, "tdm1_mclk", NULL);
1106 clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0,
1107 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0,
1109 clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
1111 clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents,
1112 ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1113 SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
1115 clk_register_clkdev(clk, "tdm2_mclk", NULL);
1117 clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0,
1118 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0,
1120 clk_register_clkdev(clk, NULL, "tdm_hdlc.1");