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1 /*
2  * SPEAr3xx machines clock framework source file
3  *
4  * Copyright (C) 2012 ST Microelectronics
5  * Viresh Kumar <viresh.linux@gmail.com>
6  *
7  * This file is licensed under the terms of the GNU General Public
8  * License version 2. This program is licensed "as is" without any
9  * warranty of any kind, whether express or implied.
10  */
11
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/err.h>
15 #include <linux/io.h>
16 #include <linux/of_platform.h>
17 #include <linux/spinlock_types.h>
18 #include <mach/misc_regs.h>
19 #include "clk.h"
20
21 static DEFINE_SPINLOCK(_lock);
22
23 #define PLL1_CTR                        (MISC_BASE + 0x008)
24 #define PLL1_FRQ                        (MISC_BASE + 0x00C)
25 #define PLL2_CTR                        (MISC_BASE + 0x014)
26 #define PLL2_FRQ                        (MISC_BASE + 0x018)
27 #define PLL_CLK_CFG                     (MISC_BASE + 0x020)
28         /* PLL_CLK_CFG register masks */
29         #define MCTR_CLK_SHIFT          28
30         #define MCTR_CLK_MASK           3
31
32 #define CORE_CLK_CFG                    (MISC_BASE + 0x024)
33         /* CORE CLK CFG register masks */
34         #define GEN_SYNTH2_3_CLK_SHIFT  18
35         #define GEN_SYNTH2_3_CLK_MASK   1
36
37         #define HCLK_RATIO_SHIFT        10
38         #define HCLK_RATIO_MASK         2
39         #define PCLK_RATIO_SHIFT        8
40         #define PCLK_RATIO_MASK         2
41
42 #define PERIP_CLK_CFG                   (MISC_BASE + 0x028)
43         /* PERIP_CLK_CFG register masks */
44         #define UART_CLK_SHIFT          4
45         #define UART_CLK_MASK           1
46         #define FIRDA_CLK_SHIFT         5
47         #define FIRDA_CLK_MASK          2
48         #define GPT0_CLK_SHIFT          8
49         #define GPT1_CLK_SHIFT          11
50         #define GPT2_CLK_SHIFT          12
51         #define GPT_CLK_MASK            1
52
53 #define PERIP1_CLK_ENB                  (MISC_BASE + 0x02C)
54         /* PERIP1_CLK_ENB register masks */
55         #define UART_CLK_ENB            3
56         #define SSP_CLK_ENB             5
57         #define I2C_CLK_ENB             7
58         #define JPEG_CLK_ENB            8
59         #define FIRDA_CLK_ENB           10
60         #define GPT1_CLK_ENB            11
61         #define GPT2_CLK_ENB            12
62         #define ADC_CLK_ENB             15
63         #define RTC_CLK_ENB             17
64         #define GPIO_CLK_ENB            18
65         #define DMA_CLK_ENB             19
66         #define SMI_CLK_ENB             21
67         #define GMAC_CLK_ENB            23
68         #define USBD_CLK_ENB            24
69         #define USBH_CLK_ENB            25
70         #define C3_CLK_ENB              31
71
72 #define RAS_CLK_ENB                     (MISC_BASE + 0x034)
73         #define RAS_AHB_CLK_ENB         0
74         #define RAS_PLL1_CLK_ENB        1
75         #define RAS_APB_CLK_ENB         2
76         #define RAS_32K_CLK_ENB         3
77         #define RAS_24M_CLK_ENB         4
78         #define RAS_48M_CLK_ENB         5
79         #define RAS_PLL2_CLK_ENB        7
80         #define RAS_SYNT0_CLK_ENB       8
81         #define RAS_SYNT1_CLK_ENB       9
82         #define RAS_SYNT2_CLK_ENB       10
83         #define RAS_SYNT3_CLK_ENB       11
84
85 #define PRSC0_CLK_CFG                   (MISC_BASE + 0x044)
86 #define PRSC1_CLK_CFG                   (MISC_BASE + 0x048)
87 #define PRSC2_CLK_CFG                   (MISC_BASE + 0x04C)
88 #define AMEM_CLK_CFG                    (MISC_BASE + 0x050)
89         #define AMEM_CLK_ENB            0
90
91 #define CLCD_CLK_SYNT                   (MISC_BASE + 0x05C)
92 #define FIRDA_CLK_SYNT                  (MISC_BASE + 0x060)
93 #define UART_CLK_SYNT                   (MISC_BASE + 0x064)
94 #define GMAC_CLK_SYNT                   (MISC_BASE + 0x068)
95 #define GEN0_CLK_SYNT                   (MISC_BASE + 0x06C)
96 #define GEN1_CLK_SYNT                   (MISC_BASE + 0x070)
97 #define GEN2_CLK_SYNT                   (MISC_BASE + 0x074)
98 #define GEN3_CLK_SYNT                   (MISC_BASE + 0x078)
99
100 /* pll rate configuration table, in ascending order of rates */
101 static struct pll_rate_tbl pll_rtbl[] = {
102         {.mode = 0, .m = 0x53, .n = 0x0C, .p = 0x1}, /* vco 332 & pll 166 MHz */
103         {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* vco 532 & pll 266 MHz */
104         {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* vco 664 & pll 332 MHz */
105 };
106
107 /* aux rate configuration table, in ascending order of rates */
108 static struct aux_rate_tbl aux_rtbl[] = {
109         /* For PLL1 = 332 MHz */
110         {.xscale = 1, .yscale = 81, .eq = 0}, /* 2.049 MHz */
111         {.xscale = 1, .yscale = 59, .eq = 0}, /* 2.822 MHz */
112         {.xscale = 2, .yscale = 81, .eq = 0}, /* 4.098 MHz */
113         {.xscale = 3, .yscale = 89, .eq = 0}, /* 5.644 MHz */
114         {.xscale = 4, .yscale = 81, .eq = 0}, /* 8.197 MHz */
115         {.xscale = 4, .yscale = 59, .eq = 0}, /* 11.254 MHz */
116         {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
117         {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
118         {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
119         {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
120 };
121
122 /* gpt rate configuration table, in ascending order of rates */
123 static struct gpt_rate_tbl gpt_rtbl[] = {
124         /* For pll1 = 332 MHz */
125         {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
126         {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
127         {.mscale = 1, .nscale = 0}, /* 83 MHz */
128 };
129
130 /* clock parents */
131 static const char *uart0_parents[] = { "pll3_clk", "uart_syn_gclk", };
132 static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk",
133 };
134 static const char *gpt0_parents[] = { "pll3_clk", "gpt0_syn_clk", };
135 static const char *gpt1_parents[] = { "pll3_clk", "gpt1_syn_clk", };
136 static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
137 static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", };
138 static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
139         "pll2_clk", };
140
141 #ifdef CONFIG_MACH_SPEAR300
142 static void __init spear300_clk_init(void)
143 {
144         struct clk *clk;
145
146         clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
147                         1, 1);
148         clk_register_clkdev(clk, NULL, "60000000.clcd");
149
150         clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
151                         1);
152         clk_register_clkdev(clk, NULL, "94000000.flash");
153
154         clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1,
155                         1);
156         clk_register_clkdev(clk, NULL, "70000000.sdhci");
157
158         clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1,
159                         1);
160         clk_register_clkdev(clk, NULL, "a9000000.gpio");
161
162         clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1,
163                         1);
164         clk_register_clkdev(clk, NULL, "a0000000.kbd");
165 }
166 #else
167 static inline void spear300_clk_init(void) { }
168 #endif
169
170 /* array of all spear 310 clock lookups */
171 #ifdef CONFIG_MACH_SPEAR310
172 static void __init spear310_clk_init(void)
173 {
174         struct clk *clk;
175
176         clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
177                         1);
178         clk_register_clkdev(clk, "emi", NULL);
179
180         clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
181                         1);
182         clk_register_clkdev(clk, NULL, "44000000.flash");
183
184         clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1,
185                         1);
186         clk_register_clkdev(clk, NULL, "tdm");
187
188         clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1,
189                         1);
190         clk_register_clkdev(clk, NULL, "b2000000.serial");
191
192         clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1,
193                         1);
194         clk_register_clkdev(clk, NULL, "b2080000.serial");
195
196         clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1,
197                         1);
198         clk_register_clkdev(clk, NULL, "b2100000.serial");
199
200         clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1,
201                         1);
202         clk_register_clkdev(clk, NULL, "b2180000.serial");
203
204         clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1,
205                         1);
206         clk_register_clkdev(clk, NULL, "b2200000.serial");
207 }
208 #else
209 static inline void spear310_clk_init(void) { }
210 #endif
211
212 /* array of all spear 320 clock lookups */
213 #ifdef CONFIG_MACH_SPEAR320
214         #define SMII_PCLK_SHIFT                         18
215         #define SMII_PCLK_MASK                          2
216         #define SMII_PCLK_VAL_PAD                       0x0
217         #define SMII_PCLK_VAL_PLL2                      0x1
218         #define SMII_PCLK_VAL_SYNTH0                    0x2
219         #define SDHCI_PCLK_SHIFT                        15
220         #define SDHCI_PCLK_MASK                         1
221         #define SDHCI_PCLK_VAL_48M                      0x0
222         #define SDHCI_PCLK_VAL_SYNTH3                   0x1
223         #define I2S_REF_PCLK_SHIFT                      8
224         #define I2S_REF_PCLK_MASK                       1
225         #define I2S_REF_PCLK_SYNTH_VAL                  0x1
226         #define I2S_REF_PCLK_PLL2_VAL                   0x0
227         #define UART1_PCLK_SHIFT                        6
228         #define UART1_PCLK_MASK                         1
229         #define SPEAR320_UARTX_PCLK_VAL_SYNTH1          0x0
230         #define SPEAR320_UARTX_PCLK_VAL_APB             0x1
231
232 static const char *i2s_ref_parents[] = { "ras_pll2_clk", "ras_syn2_gclk", };
233 static const char *sdhci_parents[] = { "ras_pll3_clk", "ras_syn3_gclk", };
234 static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
235         "ras_syn0_gclk", };
236 static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", };
237
238 static void __init spear320_clk_init(void)
239 {
240         struct clk *clk;
241
242         clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL,
243                         CLK_IS_ROOT, 125000000);
244         clk_register_clkdev(clk, "smii_125m_pad", NULL);
245
246         clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
247                         1, 1);
248         clk_register_clkdev(clk, NULL, "90000000.clcd");
249
250         clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
251                         1);
252         clk_register_clkdev(clk, "emi", NULL);
253
254         clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
255                         1);
256         clk_register_clkdev(clk, NULL, "4c000000.flash");
257
258         clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1,
259                         1);
260         clk_register_clkdev(clk, NULL, "a7000000.i2c");
261
262         clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1,
263                         1);
264         clk_register_clkdev(clk, NULL, "a8000000.pwm");
265
266         clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1,
267                         1);
268         clk_register_clkdev(clk, NULL, "a5000000.spi");
269
270         clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1,
271                         1);
272         clk_register_clkdev(clk, NULL, "a6000000.spi");
273
274         clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1,
275                         1);
276         clk_register_clkdev(clk, NULL, "c_can_platform.0");
277
278         clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1,
279                         1);
280         clk_register_clkdev(clk, NULL, "c_can_platform.1");
281
282         clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1,
283                         1);
284         clk_register_clkdev(clk, NULL, "a9400000.i2s");
285
286         clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
287                         ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT,
288                         SPEAR320_CONTROL_REG, I2S_REF_PCLK_SHIFT,
289                         I2S_REF_PCLK_MASK, 0, &_lock);
290         clk_register_clkdev(clk, "i2s_ref_clk", NULL);
291
292         clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk",
293                         CLK_SET_RATE_PARENT, 1,
294                         4);
295         clk_register_clkdev(clk, "i2s_sclk", NULL);
296
297         clk = clk_register_fixed_factor(NULL, "macb1_clk", "ras_apb_clk", 0, 1,
298                         1);
299         clk_register_clkdev(clk, "hclk", "aa000000.eth");
300
301         clk = clk_register_fixed_factor(NULL, "macb2_clk", "ras_apb_clk", 0, 1,
302                         1);
303         clk_register_clkdev(clk, "hclk", "ab000000.eth");
304
305         clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
306                         ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
307                         SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT,
308                         SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
309         clk_register_clkdev(clk, NULL, "a9300000.serial");
310
311         clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
312                         ARRAY_SIZE(sdhci_parents), CLK_SET_RATE_PARENT,
313                         SPEAR320_CONTROL_REG, SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK,
314                         0, &_lock);
315         clk_register_clkdev(clk, NULL, "70000000.sdhci");
316
317         clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
318                         ARRAY_SIZE(smii0_parents), 0, SPEAR320_CONTROL_REG,
319                         SMII_PCLK_SHIFT, SMII_PCLK_MASK, 0, &_lock);
320         clk_register_clkdev(clk, NULL, "smii_pclk");
321
322         clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
323         clk_register_clkdev(clk, NULL, "smii");
324
325         clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
326                         ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
327                         SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK,
328                         0, &_lock);
329         clk_register_clkdev(clk, NULL, "a3000000.serial");
330
331         clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
332                         ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
333                         SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT,
334                         SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
335         clk_register_clkdev(clk, NULL, "a4000000.serial");
336
337         clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
338                         ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
339                         SPEAR320_EXT_CTRL_REG, SPEAR320_UART3_PCLK_SHIFT,
340                         SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
341         clk_register_clkdev(clk, NULL, "a9100000.serial");
342
343         clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
344                         ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
345                         SPEAR320_EXT_CTRL_REG, SPEAR320_UART4_PCLK_SHIFT,
346                         SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
347         clk_register_clkdev(clk, NULL, "a9200000.serial");
348
349         clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
350                         ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
351                         SPEAR320_EXT_CTRL_REG, SPEAR320_UART5_PCLK_SHIFT,
352                         SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
353         clk_register_clkdev(clk, NULL, "60000000.serial");
354
355         clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
356                         ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
357                         SPEAR320_EXT_CTRL_REG, SPEAR320_UART6_PCLK_SHIFT,
358                         SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
359         clk_register_clkdev(clk, NULL, "60100000.serial");
360 }
361 #else
362 static inline void spear320_clk_init(void) { }
363 #endif
364
365 void __init spear3xx_clk_init(void)
366 {
367         struct clk *clk, *clk1;
368
369         clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
370                         32000);
371         clk_register_clkdev(clk, "osc_32k_clk", NULL);
372
373         clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
374                         24000000);
375         clk_register_clkdev(clk, "osc_24m_clk", NULL);
376
377         /* clock derived from 32 KHz osc clk */
378         clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
379                         PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
380         clk_register_clkdev(clk, NULL, "fc900000.rtc");
381
382         /* clock derived from 24 MHz osc clk */
383         clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
384                         48000000);
385         clk_register_clkdev(clk, "pll3_clk", NULL);
386
387         clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1,
388                         1);
389         clk_register_clkdev(clk, NULL, "fc880000.wdt");
390
391         clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL,
392                         "osc_24m_clk", 0, PLL1_CTR, PLL1_FRQ, pll_rtbl,
393                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
394         clk_register_clkdev(clk, "vco1_clk", NULL);
395         clk_register_clkdev(clk1, "pll1_clk", NULL);
396
397         clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL,
398                         "osc_24m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl,
399                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
400         clk_register_clkdev(clk, "vco2_clk", NULL);
401         clk_register_clkdev(clk1, "pll2_clk", NULL);
402
403         /* clock derived from pll1 clk */
404         clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
405                         CLK_SET_RATE_PARENT, 1, 1);
406         clk_register_clkdev(clk, "cpu_clk", NULL);
407
408         clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
409                         CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
410                         HCLK_RATIO_MASK, 0, &_lock);
411         clk_register_clkdev(clk, "ahb_clk", NULL);
412
413         clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
414                         UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
415                         &_lock, &clk1);
416         clk_register_clkdev(clk, "uart_syn_clk", NULL);
417         clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
418
419         clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
420                         ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT,
421                         PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
422                         &_lock);
423         clk_register_clkdev(clk, "uart0_mclk", NULL);
424
425         clk = clk_register_gate(NULL, "uart0", "uart0_mclk",
426                         CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, UART_CLK_ENB, 0,
427                         &_lock);
428         clk_register_clkdev(clk, NULL, "d0000000.serial");
429
430         clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0,
431                         FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
432                         &_lock, &clk1);
433         clk_register_clkdev(clk, "firda_syn_clk", NULL);
434         clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
435
436         clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
437                         ARRAY_SIZE(firda_parents), CLK_SET_RATE_PARENT,
438                         PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
439                         &_lock);
440         clk_register_clkdev(clk, "firda_mclk", NULL);
441
442         clk = clk_register_gate(NULL, "firda_clk", "firda_mclk",
443                         CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0,
444                         &_lock);
445         clk_register_clkdev(clk, NULL, "firda");
446
447         /* gpt clocks */
448         clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl,
449                         ARRAY_SIZE(gpt_rtbl), &_lock);
450         clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
451                         ARRAY_SIZE(gpt0_parents), CLK_SET_RATE_PARENT,
452                         PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
453         clk_register_clkdev(clk, NULL, "gpt0");
454
455         clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl,
456                         ARRAY_SIZE(gpt_rtbl), &_lock);
457         clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents,
458                         ARRAY_SIZE(gpt1_parents), CLK_SET_RATE_PARENT,
459                         PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
460         clk_register_clkdev(clk, "gpt1_mclk", NULL);
461         clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk",
462                         CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT1_CLK_ENB, 0,
463                         &_lock);
464         clk_register_clkdev(clk, NULL, "gpt1");
465
466         clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl,
467                         ARRAY_SIZE(gpt_rtbl), &_lock);
468         clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
469                         ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_PARENT,
470                         PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
471         clk_register_clkdev(clk, "gpt2_mclk", NULL);
472         clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk",
473                         CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT2_CLK_ENB, 0,
474                         &_lock);
475         clk_register_clkdev(clk, NULL, "gpt2");
476
477         /* general synths clocks */
478         clk = clk_register_aux("gen0_syn_clk", "gen0_syn_gclk", "pll1_clk",
479                         0, GEN0_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
480                         &_lock, &clk1);
481         clk_register_clkdev(clk, "gen0_syn_clk", NULL);
482         clk_register_clkdev(clk1, "gen0_syn_gclk", NULL);
483
484         clk = clk_register_aux("gen1_syn_clk", "gen1_syn_gclk", "pll1_clk",
485                         0, GEN1_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
486                         &_lock, &clk1);
487         clk_register_clkdev(clk, "gen1_syn_clk", NULL);
488         clk_register_clkdev(clk1, "gen1_syn_gclk", NULL);
489
490         clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents,
491                         ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG,
492                         GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0,
493                         &_lock);
494         clk_register_clkdev(clk, "gen2_3_par_clk", NULL);
495
496         clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk",
497                         "gen2_3_par_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl,
498                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
499         clk_register_clkdev(clk, "gen2_syn_clk", NULL);
500         clk_register_clkdev(clk1, "gen2_syn_gclk", NULL);
501
502         clk = clk_register_aux("gen3_syn_clk", "gen3_syn_gclk",
503                         "gen2_3_par_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl,
504                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
505         clk_register_clkdev(clk, "gen3_syn_clk", NULL);
506         clk_register_clkdev(clk1, "gen3_syn_gclk", NULL);
507
508         /* clock derived from pll3 clk */
509         clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
510                         USBH_CLK_ENB, 0, &_lock);
511         clk_register_clkdev(clk, NULL, "e1800000.ehci");
512         clk_register_clkdev(clk, NULL, "e1900000.ohci");
513         clk_register_clkdev(clk, NULL, "e2100000.ohci");
514
515         clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1,
516                         1);
517         clk_register_clkdev(clk, "usbh.0_clk", NULL);
518
519         clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1,
520                         1);
521         clk_register_clkdev(clk, "usbh.1_clk", NULL);
522
523         clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
524                         USBD_CLK_ENB, 0, &_lock);
525         clk_register_clkdev(clk, NULL, "e1100000.usbd");
526
527         /* clock derived from ahb clk */
528         clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
529                         1);
530         clk_register_clkdev(clk, "ahbmult2_clk", NULL);
531
532         clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
533                         ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT,
534                         MCTR_CLK_MASK, 0, &_lock);
535         clk_register_clkdev(clk, "ddr_clk", NULL);
536
537         clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
538                         CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
539                         PCLK_RATIO_MASK, 0, &_lock);
540         clk_register_clkdev(clk, "apb_clk", NULL);
541
542         clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG,
543                         AMEM_CLK_ENB, 0, &_lock);
544         clk_register_clkdev(clk, "amem_clk", NULL);
545
546         clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
547                         C3_CLK_ENB, 0, &_lock);
548         clk_register_clkdev(clk, NULL, "c3_clk");
549
550         clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
551                         DMA_CLK_ENB, 0, &_lock);
552         clk_register_clkdev(clk, NULL, "fc400000.dma");
553
554         clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
555                         GMAC_CLK_ENB, 0, &_lock);
556         clk_register_clkdev(clk, NULL, "e0800000.eth");
557
558         clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
559                         I2C_CLK_ENB, 0, &_lock);
560         clk_register_clkdev(clk, NULL, "d0180000.i2c");
561
562         clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
563                         JPEG_CLK_ENB, 0, &_lock);
564         clk_register_clkdev(clk, NULL, "jpeg");
565
566         clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
567                         SMI_CLK_ENB, 0, &_lock);
568         clk_register_clkdev(clk, NULL, "fc000000.flash");
569
570         /* clock derived from apb clk */
571         clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
572                         ADC_CLK_ENB, 0, &_lock);
573         clk_register_clkdev(clk, NULL, "d0080000.adc");
574
575         clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
576                         GPIO_CLK_ENB, 0, &_lock);
577         clk_register_clkdev(clk, NULL, "fc980000.gpio");
578
579         clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
580                         SSP_CLK_ENB, 0, &_lock);
581         clk_register_clkdev(clk, NULL, "d0100000.spi");
582
583         /* RAS clk enable */
584         clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB,
585                         RAS_AHB_CLK_ENB, 0, &_lock);
586         clk_register_clkdev(clk, "ras_ahb_clk", NULL);
587
588         clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB,
589                         RAS_APB_CLK_ENB, 0, &_lock);
590         clk_register_clkdev(clk, "ras_apb_clk", NULL);
591
592         clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0,
593                         RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock);
594         clk_register_clkdev(clk, "ras_32k_clk", NULL);
595
596         clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0,
597                         RAS_CLK_ENB, RAS_24M_CLK_ENB, 0, &_lock);
598         clk_register_clkdev(clk, "ras_24m_clk", NULL);
599
600         clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0,
601                         RAS_CLK_ENB, RAS_PLL1_CLK_ENB, 0, &_lock);
602         clk_register_clkdev(clk, "ras_pll1_clk", NULL);
603
604         clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
605                         RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock);
606         clk_register_clkdev(clk, "ras_pll2_clk", NULL);
607
608         clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
609                         RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock);
610         clk_register_clkdev(clk, "ras_pll3_clk", NULL);
611
612         clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk",
613                         CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0,
614                         &_lock);
615         clk_register_clkdev(clk, "ras_syn0_gclk", NULL);
616
617         clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk",
618                         CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0,
619                         &_lock);
620         clk_register_clkdev(clk, "ras_syn1_gclk", NULL);
621
622         clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk",
623                         CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0,
624                         &_lock);
625         clk_register_clkdev(clk, "ras_syn2_gclk", NULL);
626
627         clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk",
628                         CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0,
629                         &_lock);
630         clk_register_clkdev(clk, "ras_syn3_gclk", NULL);
631
632         if (of_machine_is_compatible("st,spear300"))
633                 spear300_clk_init();
634         else if (of_machine_is_compatible("st,spear310"))
635                 spear310_clk_init();
636         else if (of_machine_is_compatible("st,spear320"))
637                 spear320_clk_init();
638 }