2 * Copyright 2013 Emilio López
4 * Emilio López <emilio@elopez.com.ar>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
18 #include <linux/clkdev.h>
19 #include <linux/of_address.h>
20 #include <linux/platform_device.h>
22 #include "clk-factors.h"
25 * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
26 * MOD0 rate is calculated as follows
27 * rate = (parent_rate >> p) / (m + 1);
30 static void sun4i_a10_get_mod0_factors(u32 *freq, u32 parent_rate,
31 u8 *n, u8 *k, u8 *m, u8 *p)
35 /* These clocks can only divide, so we will never be able to achieve
36 * frequencies higher than the parent frequency */
37 if (*freq > parent_rate)
40 div = DIV_ROUND_UP(parent_rate, *freq);
44 else if (div / 2 < 16)
46 else if (div / 4 < 16)
51 calcm = DIV_ROUND_UP(div, 1 << calcp);
53 *freq = (parent_rate >> calcp) / calcm;
55 /* we were called to round the frequency, we can now return */
63 /* user manual says "n" but it's really "p" */
64 static struct clk_factors_config sun4i_a10_mod0_config = {
71 static const struct factors_data sun4i_a10_mod0_data = {
74 .muxmask = BIT(1) | BIT(0),
75 .table = &sun4i_a10_mod0_config,
76 .getter = sun4i_a10_get_mod0_factors,
79 static DEFINE_SPINLOCK(sun4i_a10_mod0_lock);
81 static void __init sun4i_a10_mod0_setup(struct device_node *node)
85 reg = of_iomap(node, 0);
88 * This happens with mod0 clk nodes instantiated through
89 * mfd, as those do not have their resources assigned at
90 * CLK_OF_DECLARE time yet, so do not print an error.
95 sunxi_factors_register(node, &sun4i_a10_mod0_data,
96 &sun4i_a10_mod0_lock, reg);
98 CLK_OF_DECLARE(sun4i_a10_mod0, "allwinner,sun4i-a10-mod0-clk", sun4i_a10_mod0_setup);
100 static int sun4i_a10_mod0_clk_probe(struct platform_device *pdev)
102 struct device_node *np = pdev->dev.of_node;
109 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
110 reg = devm_ioremap_resource(&pdev->dev, r);
114 sunxi_factors_register(np, &sun4i_a10_mod0_data,
115 &sun4i_a10_mod0_lock, reg);
119 static const struct of_device_id sun4i_a10_mod0_clk_dt_ids[] = {
120 { .compatible = "allwinner,sun4i-a10-mod0-clk" },
124 static struct platform_driver sun4i_a10_mod0_clk_driver = {
126 .name = "sun4i-a10-mod0-clk",
127 .of_match_table = sun4i_a10_mod0_clk_dt_ids,
129 .probe = sun4i_a10_mod0_clk_probe,
131 builtin_platform_driver(sun4i_a10_mod0_clk_driver);
133 static const struct factors_data sun9i_a80_mod0_data __initconst = {
136 .muxmask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
137 .table = &sun4i_a10_mod0_config,
138 .getter = sun4i_a10_get_mod0_factors,
141 static void __init sun9i_a80_mod0_setup(struct device_node *node)
145 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
147 pr_err("Could not get registers for mod0-clk: %s\n",
152 sunxi_factors_register(node, &sun9i_a80_mod0_data,
153 &sun4i_a10_mod0_lock, reg);
155 CLK_OF_DECLARE(sun9i_a80_mod0, "allwinner,sun9i-a80-mod0-clk", sun9i_a80_mod0_setup);
157 static DEFINE_SPINLOCK(sun5i_a13_mbus_lock);
159 static void __init sun5i_a13_mbus_setup(struct device_node *node)
164 reg = of_iomap(node, 0);
166 pr_err("Could not get registers for a13-mbus-clk\n");
170 mbus = sunxi_factors_register(node, &sun4i_a10_mod0_data,
171 &sun5i_a13_mbus_lock, reg);
173 /* The MBUS clocks needs to be always enabled */
175 clk_prepare_enable(mbus);
177 CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);
186 #define to_mmc_phase(_hw) container_of(_hw, struct mmc_phase, hw)
188 static int mmc_get_phase(struct clk_hw *hw)
190 struct clk *mmc, *mmc_parent, *clk = hw->clk;
191 struct mmc_phase *phase = to_mmc_phase(hw);
192 unsigned int mmc_rate, mmc_parent_rate;
197 value = readl(phase->reg);
198 delay = (value >> phase->offset) & 0x3;
203 /* Get the main MMC clock */
204 mmc = clk_get_parent(clk);
209 mmc_rate = clk_get_rate(mmc);
213 /* Now, get the MMC parent (most likely some PLL) */
214 mmc_parent = clk_get_parent(mmc);
219 mmc_parent_rate = clk_get_rate(mmc_parent);
220 if (!mmc_parent_rate)
223 /* Get MMC clock divider */
224 mmc_div = mmc_parent_rate / mmc_rate;
226 step = DIV_ROUND_CLOSEST(360, mmc_div);
230 static int mmc_set_phase(struct clk_hw *hw, int degrees)
232 struct clk *mmc, *mmc_parent, *clk = hw->clk;
233 struct mmc_phase *phase = to_mmc_phase(hw);
234 unsigned int mmc_rate, mmc_parent_rate;
239 /* Get the main MMC clock */
240 mmc = clk_get_parent(clk);
245 mmc_rate = clk_get_rate(mmc);
249 /* Now, get the MMC parent (most likely some PLL) */
250 mmc_parent = clk_get_parent(mmc);
255 mmc_parent_rate = clk_get_rate(mmc_parent);
256 if (!mmc_parent_rate)
259 if (degrees != 180) {
262 /* Get MMC clock divider */
263 mmc_div = mmc_parent_rate / mmc_rate;
266 * We can only outphase the clocks by multiple of the
269 * Since the MMC clock in only a divider, and the
270 * formula to get the outphasing in degrees is deg =
271 * 360 * delta / period
273 * If we simplify this formula, we can see that the
274 * only thing that we're concerned about is the number
275 * of period we want to outphase our clock from, and
276 * the divider set by the MMC clock.
278 step = DIV_ROUND_CLOSEST(360, mmc_div);
279 delay = DIV_ROUND_CLOSEST(degrees, step);
284 spin_lock_irqsave(phase->lock, flags);
285 value = readl(phase->reg);
286 value &= ~GENMASK(phase->offset + 3, phase->offset);
287 value |= delay << phase->offset;
288 writel(value, phase->reg);
289 spin_unlock_irqrestore(phase->lock, flags);
294 static const struct clk_ops mmc_clk_ops = {
295 .get_phase = mmc_get_phase,
296 .set_phase = mmc_set_phase,
300 * sunxi_mmc_setup - Common setup function for mmc module clocks
302 * The only difference between module clocks on different platforms is the
303 * width of the mux register bits and the valid values, which are passed in
304 * through struct factors_data. The phase clocks parts are identical.
306 static void __init sunxi_mmc_setup(struct device_node *node,
307 const struct factors_data *data,
310 struct clk_onecell_data *clk_data;
315 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
317 pr_err("Couldn't map the %s clock registers\n", node->name);
321 clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
325 clk_data->clks = kcalloc(3, sizeof(*clk_data->clks), GFP_KERNEL);
329 clk_data->clk_num = 3;
330 clk_data->clks[0] = sunxi_factors_register(node, data, lock, reg);
331 if (!clk_data->clks[0])
334 parent = __clk_get_name(clk_data->clks[0]);
336 for (i = 1; i < 3; i++) {
337 struct clk_init_data init = {
339 .parent_names = &parent,
342 struct mmc_phase *phase;
344 phase = kmalloc(sizeof(*phase), GFP_KERNEL);
348 phase->hw.init = &init;
357 if (of_property_read_string_index(node, "clock-output-names",
359 init.name = node->name;
361 clk_data->clks[i] = clk_register(NULL, &phase->hw);
362 if (IS_ERR(clk_data->clks[i])) {
368 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
373 kfree(clk_data->clks);
378 static DEFINE_SPINLOCK(sun4i_a10_mmc_lock);
380 static void __init sun4i_a10_mmc_setup(struct device_node *node)
382 sunxi_mmc_setup(node, &sun4i_a10_mod0_data, &sun4i_a10_mmc_lock);
384 CLK_OF_DECLARE(sun4i_a10_mmc, "allwinner,sun4i-a10-mmc-clk", sun4i_a10_mmc_setup);
386 static DEFINE_SPINLOCK(sun9i_a80_mmc_lock);
388 static void __init sun9i_a80_mmc_setup(struct device_node *node)
390 sunxi_mmc_setup(node, &sun9i_a80_mod0_data, &sun9i_a80_mmc_lock);
392 CLK_OF_DECLARE(sun9i_a80_mmc, "allwinner,sun9i-a80-mmc-clk", sun9i_a80_mmc_setup);