drivers/clk/sunxi-ng/ccu_div.c

   1 /*
   2  * Copyright (C) 2016 Maxime Ripard
   3  * Maxime Ripard <maxime.ripard@free-electrons.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  */
  10
  11 #include <linux/clk-provider.h>
  12
  13 #include "ccu_gate.h"
  14 #include "ccu_div.h"
  15
  16 static unsigned long ccu_div_round_rate(struct ccu_mux_internal *mux,
  17                                         unsigned long parent_rate,
  18                                         unsigned long rate,
  19                                         void *data)
  20 {
  21         struct ccu_div *cd = data;
  22         unsigned long val;
  23
  24         /*
  25          * We can't use divider_round_rate that assumes that there's
  26          * several parents, while we might be called to evaluate
  27          * several different parents.
  28          */
  29         val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
  30                               cd->div.flags);
  31
  32         return divider_recalc_rate(&cd->common.hw, parent_rate, val,
  33                                    cd->div.table, cd->div.flags);
  34 }
  35
  36 static void ccu_div_disable(struct clk_hw *hw)
  37 {
  38         struct ccu_div *cd = hw_to_ccu_div(hw);
  39
  40         return ccu_gate_helper_disable(&cd->common, cd->enable);
  41 }
  42
  43 static int ccu_div_enable(struct clk_hw *hw)
  44 {
  45         struct ccu_div *cd = hw_to_ccu_div(hw);
  46
  47         return ccu_gate_helper_enable(&cd->common, cd->enable);
  48 }
  49
  50 static int ccu_div_is_enabled(struct clk_hw *hw)
  51 {
  52         struct ccu_div *cd = hw_to_ccu_div(hw);
  53
  54         return ccu_gate_helper_is_enabled(&cd->common, cd->enable);
  55 }
  56
  57 static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
  58                                         unsigned long parent_rate)
  59 {
  60         struct ccu_div *cd = hw_to_ccu_div(hw);
  61         unsigned long val;
  62         u32 reg;
  63
  64         reg = readl(cd->common.base + cd->common.reg);
  65         val = reg >> cd->div.shift;
  66         val &= (1 << cd->div.width) - 1;
  67
  68         ccu_mux_helper_adjust_parent_for_prediv(&cd->common, &cd->mux, -1,
  69                                                 &parent_rate);
  70
  71         return divider_recalc_rate(hw, parent_rate, val, cd->div.table,
  72                                    cd->div.flags);
  73 }
  74
  75 static int ccu_div_determine_rate(struct clk_hw *hw,
  76                                 struct clk_rate_request *req)
  77 {
  78         struct ccu_div *cd = hw_to_ccu_div(hw);
  79
  80         if (clk_hw_get_num_parents(hw) == 1) {
  81                 req->rate = divider_round_rate(hw, req->rate,
  82                                                &req->best_parent_rate,
  83                                                cd->div.table,
  84                                                cd->div.width,
  85                                                cd->div.flags);
  86
  87                 req->best_parent_hw = clk_hw_get_parent(hw);
  88
  89                 return 0;
  90         }
  91
  92         return ccu_mux_helper_determine_rate(&cd->common, &cd->mux,
  93                                              req, ccu_div_round_rate, cd);
  94 }
  95
  96 static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate,
  97                            unsigned long parent_rate)
  98 {
  99         struct ccu_div *cd = hw_to_ccu_div(hw);
 100         unsigned long flags;
 101         unsigned long val;
 102         u32 reg;
 103
 104         ccu_mux_helper_adjust_parent_for_prediv(&cd->common, &cd->mux, -1,
 105                                                 &parent_rate);
 106
 107         val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
 108                               cd->div.flags);
 109
 110         spin_lock_irqsave(cd->common.lock, flags);
 111
 112         reg = readl(cd->common.base + cd->common.reg);
 113         reg &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift);
 114
 115         writel(reg | (val << cd->div.shift),
 116                cd->common.base + cd->common.reg);
 117
 118         spin_unlock_irqrestore(cd->common.lock, flags);
 119
 120         return 0;
 121 }
 122
 123 static u8 ccu_div_get_parent(struct clk_hw *hw)
 124 {
 125         struct ccu_div *cd = hw_to_ccu_div(hw);
 126
 127         return ccu_mux_helper_get_parent(&cd->common, &cd->mux);
 128 }
 129
 130 static int ccu_div_set_parent(struct clk_hw *hw, u8 index)
 131 {
 132         struct ccu_div *cd = hw_to_ccu_div(hw);
 133
 134         return ccu_mux_helper_set_parent(&cd->common, &cd->mux, index);
 135 }
 136
 137 const struct clk_ops ccu_div_ops = {
 138         .disable        = ccu_div_disable,
 139         .enable         = ccu_div_enable,
 140         .is_enabled     = ccu_div_is_enabled,
 141
 142         .get_parent     = ccu_div_get_parent,
 143         .set_parent     = ccu_div_set_parent,
 144
 145         .determine_rate = ccu_div_determine_rate,
 146         .recalc_rate    = ccu_div_recalc_rate,
 147         .set_rate       = ccu_div_set_rate,
 148 };