2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/kernel.h>
19 #include <linux/err.h>
20 #include <linux/slab.h>
21 #include <linux/clk-provider.h>
25 #define pll_out_override(p) (BIT((p->shift - 6)))
26 #define div_mask(d) ((1 << (d->width)) - 1)
27 #define get_mul(d) (1 << d->frac_width)
28 #define get_max_div(d) div_mask(d)
30 #define PERIPH_CLK_UART_DIV_ENB BIT(24)
32 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
33 unsigned long parent_rate)
35 u64 divider_ux1 = parent_rate;
36 u8 flags = divider->flags;
42 mul = get_mul(divider);
44 if (!(flags & TEGRA_DIVIDER_INT))
47 if (flags & TEGRA_DIVIDER_ROUND_UP)
48 divider_ux1 += rate - 1;
50 do_div(divider_ux1, rate);
52 if (flags & TEGRA_DIVIDER_INT)
57 if ((s64)divider_ux1 < 0)
60 if (divider_ux1 > get_max_div(divider))
61 return get_max_div(divider);
66 static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
67 unsigned long parent_rate)
69 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
72 u64 rate = parent_rate;
74 reg = readl_relaxed(divider->reg) >> divider->shift;
75 div = reg & div_mask(divider);
77 mul = get_mul(divider);
87 static long clk_frac_div_round_rate(struct clk_hw *hw, unsigned long rate,
90 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
92 unsigned long output_rate = *prate;
97 div = get_div(divider, rate, output_rate);
101 mul = get_mul(divider);
103 return DIV_ROUND_UP(output_rate * mul, div + mul);
106 static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate,
107 unsigned long parent_rate)
109 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
111 unsigned long flags = 0;
114 div = get_div(divider, rate, parent_rate);
119 spin_lock_irqsave(divider->lock, flags);
121 val = readl_relaxed(divider->reg);
122 val &= ~(div_mask(divider) << divider->shift);
123 val |= div << divider->shift;
125 if (divider->flags & TEGRA_DIVIDER_UART) {
127 val |= PERIPH_CLK_UART_DIV_ENB;
129 val &= ~PERIPH_CLK_UART_DIV_ENB;
132 if (divider->flags & TEGRA_DIVIDER_FIXED)
133 val |= pll_out_override(divider);
135 writel_relaxed(val, divider->reg);
138 spin_unlock_irqrestore(divider->lock, flags);
143 const struct clk_ops tegra_clk_frac_div_ops = {
144 .recalc_rate = clk_frac_div_recalc_rate,
145 .set_rate = clk_frac_div_set_rate,
146 .round_rate = clk_frac_div_round_rate,
149 struct clk *tegra_clk_register_divider(const char *name,
150 const char *parent_name, void __iomem *reg,
151 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
152 u8 frac_width, spinlock_t *lock)
154 struct tegra_clk_frac_div *divider;
156 struct clk_init_data init;
158 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
160 pr_err("%s: could not allocate fractional divider clk\n",
162 return ERR_PTR(-ENOMEM);
166 init.ops = &tegra_clk_frac_div_ops;
168 init.parent_names = parent_name ? &parent_name : NULL;
169 init.num_parents = parent_name ? 1 : 0;
172 divider->shift = shift;
173 divider->width = width;
174 divider->frac_width = frac_width;
175 divider->lock = lock;
176 divider->flags = clk_divider_flags;
178 /* Data in .init is copied by clk_register(), so stack variable OK */
179 divider->hw.init = &init;
181 clk = clk_register(NULL, ÷r->hw);
188 static const struct clk_div_table mc_div_table[] = {
189 { .val = 0, .div = 2 },
190 { .val = 1, .div = 1 },
191 { .val = 0, .div = 0 },
194 struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
195 void __iomem *reg, spinlock_t *lock)
197 return clk_register_divider_table(NULL, name, parent_name, 0, reg,
198 16, 1, 0, mc_div_table, lock);