drivers/clk/tegra/clk-pll.c

   1 /*
   2  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/slab.h>
  18 #include <linux/io.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/clk.h>
  23
  24 #include "clk.h"
  25
  26 #define PLL_BASE_BYPASS BIT(31)
  27 #define PLL_BASE_ENABLE BIT(30)
  28 #define PLL_BASE_REF_ENABLE BIT(29)
  29 #define PLL_BASE_OVERRIDE BIT(28)
  30
  31 #define PLL_BASE_DIVP_SHIFT 20
  32 #define PLL_BASE_DIVP_WIDTH 3
  33 #define PLL_BASE_DIVN_SHIFT 8
  34 #define PLL_BASE_DIVN_WIDTH 10
  35 #define PLL_BASE_DIVM_SHIFT 0
  36 #define PLL_BASE_DIVM_WIDTH 5
  37 #define PLLU_POST_DIVP_MASK 0x1
  38
  39 #define PLL_MISC_DCCON_SHIFT 20
  40 #define PLL_MISC_CPCON_SHIFT 8
  41 #define PLL_MISC_CPCON_WIDTH 4
  42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
  43 #define PLL_MISC_LFCON_SHIFT 4
  44 #define PLL_MISC_LFCON_WIDTH 4
  45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
  46 #define PLL_MISC_VCOCON_SHIFT 0
  47 #define PLL_MISC_VCOCON_WIDTH 4
  48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
  49
  50 #define OUT_OF_TABLE_CPCON 8
  51
  52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
  53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
  54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
  55
  56 #define PLL_POST_LOCK_DELAY 50
  57
  58 #define PLLDU_LFCON_SET_DIVN 600
  59
  60 #define PLLE_BASE_DIVCML_SHIFT 24
  61 #define PLLE_BASE_DIVCML_WIDTH 4
  62 #define PLLE_BASE_DIVP_SHIFT 16
  63 #define PLLE_BASE_DIVP_WIDTH 7
  64 #define PLLE_BASE_DIVN_SHIFT 8
  65 #define PLLE_BASE_DIVN_WIDTH 8
  66 #define PLLE_BASE_DIVM_SHIFT 0
  67 #define PLLE_BASE_DIVM_WIDTH 8
  68
  69 #define PLLE_MISC_SETUP_BASE_SHIFT 16
  70 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
  71 #define PLLE_MISC_LOCK_ENABLE BIT(9)
  72 #define PLLE_MISC_READY BIT(15)
  73 #define PLLE_MISC_SETUP_EX_SHIFT 2
  74 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
  75 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK |       \
  76                               PLLE_MISC_SETUP_EX_MASK)
  77 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
  78
  79 #define PLLE_SS_CTRL 0x68
  80 #define PLLE_SS_DISABLE (7 << 10)
  81
  82 #define PLLE_AUX_PLLP_SEL       BIT(2)
  83 #define PLLE_AUX_ENABLE_SWCTL   BIT(4)
  84 #define PLLE_AUX_SEQ_ENABLE     BIT(24)
  85 #define PLLE_AUX_PLLRE_SEL      BIT(28)
  86
  87 #define PLLE_MISC_PLLE_PTS      BIT(8)
  88 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
  89 #define PLLE_MISC_IDDQ_SW_CTRL  BIT(14)
  90 #define PLLE_MISC_VREG_BG_CTRL_SHIFT    4
  91 #define PLLE_MISC_VREG_BG_CTRL_MASK     (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
  92 #define PLLE_MISC_VREG_CTRL_SHIFT       2
  93 #define PLLE_MISC_VREG_CTRL_MASK        (2 << PLLE_MISC_VREG_CTRL_SHIFT)
  94
  95 #define PLLCX_MISC_STROBE       BIT(31)
  96 #define PLLCX_MISC_RESET        BIT(30)
  97 #define PLLCX_MISC_SDM_DIV_SHIFT 28
  98 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
  99 #define PLLCX_MISC_FILT_DIV_SHIFT 26
 100 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
 101 #define PLLCX_MISC_ALPHA_SHIFT 18
 102 #define PLLCX_MISC_DIV_LOW_RANGE \
 103                 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 104                 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
 105 #define PLLCX_MISC_DIV_HIGH_RANGE \
 106                 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 107                 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
 108 #define PLLCX_MISC_COEF_LOW_RANGE \
 109                 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
 110 #define PLLCX_MISC_KA_SHIFT 2
 111 #define PLLCX_MISC_KB_SHIFT 9
 112 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
 113                             (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
 114                             PLLCX_MISC_DIV_LOW_RANGE | \
 115                             PLLCX_MISC_RESET)
 116 #define PLLCX_MISC1_DEFAULT 0x000d2308
 117 #define PLLCX_MISC2_DEFAULT 0x30211200
 118 #define PLLCX_MISC3_DEFAULT 0x200
 119
 120 #define PMC_PLLM_WB0_OVERRIDE   0x1dc
 121 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
 122 #define PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK BIT(27)
 123
 124 #define PMC_SATA_PWRGT 0x1ac
 125 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
 126 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
 127
 128 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
 129 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
 130 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
 131
 132 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
 133 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
 134 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
 135
 136 #define mask(w) ((1 << (w)) - 1)
 137 #define divm_mask(p) mask(p->divm_width)
 138 #define divn_mask(p) mask(p->divn_width)
 139 #define divp_mask(p) (p->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :     \
 140                       mask(p->divp_width))
 141
 142 #define divm_max(p) (divm_mask(p))
 143 #define divn_max(p) (divn_mask(p))
 144 #define divp_max(p) (1 << (divp_mask(p)))
 145
 146
 147 #ifdef CONFIG_ARCH_TEGRA_114_SOC
 148 /* PLLXC has 4-bit PDIV, but entry 15 is not allowed in h/w */
 149 #define PLLXC_PDIV_MAX                  14
 150
 151 /* non-monotonic mapping below is not a typo */
 152 static u8 pllxc_p[PLLXC_PDIV_MAX + 1] = {
 153         /* PDIV: 0, 1, 2, 3, 4, 5, 6,  7,  8,  9, 10, 11, 12, 13, 14 */
 154         /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32
 155 };
 156
 157 #define PLLCX_PDIV_MAX 7
 158 static u8 pllcx_p[PLLCX_PDIV_MAX + 1] = {
 159         /* PDIV: 0, 1, 2, 3, 4, 5,  6,  7 */
 160         /* p: */ 1, 2, 3, 4, 6, 8, 12, 16
 161 };
 162 #endif
 163
 164 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
 165 {
 166         u32 val;
 167
 168         if (!(pll->flags & TEGRA_PLL_USE_LOCK))
 169                 return;
 170
 171         if (!(pll->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
 172                 return;
 173
 174         val = pll_readl_misc(pll);
 175         val |= BIT(pll->params->lock_enable_bit_idx);
 176         pll_writel_misc(val, pll);
 177 }
 178
 179 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
 180 {
 181         int i;
 182         u32 val, lock_mask;
 183         void __iomem *lock_addr;
 184
 185         if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
 186                 udelay(pll->params->lock_delay);
 187                 return 0;
 188         }
 189
 190         lock_addr = pll->clk_base;
 191         if (pll->flags & TEGRA_PLL_LOCK_MISC)
 192                 lock_addr += pll->params->misc_reg;
 193         else
 194                 lock_addr += pll->params->base_reg;
 195
 196         lock_mask = pll->params->lock_mask;
 197
 198         for (i = 0; i < pll->params->lock_delay; i++) {
 199                 val = readl_relaxed(lock_addr);
 200                 if ((val & lock_mask) == lock_mask) {
 201                         udelay(PLL_POST_LOCK_DELAY);
 202                         return 0;
 203                 }
 204                 udelay(2); /* timeout = 2 * lock time */
 205         }
 206
 207         pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
 208                __clk_get_name(pll->hw.clk));
 209
 210         return -1;
 211 }
 212
 213 static int clk_pll_is_enabled(struct clk_hw *hw)
 214 {
 215         struct tegra_clk_pll *pll = to_clk_pll(hw);
 216         u32 val;
 217
 218         if (pll->flags & TEGRA_PLLM) {
 219                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 220                 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
 221                         return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
 222         }
 223
 224         val = pll_readl_base(pll);
 225
 226         return val & PLL_BASE_ENABLE ? 1 : 0;
 227 }
 228
 229 static void _clk_pll_enable(struct clk_hw *hw)
 230 {
 231         struct tegra_clk_pll *pll = to_clk_pll(hw);
 232         u32 val;
 233
 234         clk_pll_enable_lock(pll);
 235
 236         val = pll_readl_base(pll);
 237         if (pll->flags & TEGRA_PLL_BYPASS)
 238                 val &= ~PLL_BASE_BYPASS;
 239         val |= PLL_BASE_ENABLE;
 240         pll_writel_base(val, pll);
 241
 242         if (pll->flags & TEGRA_PLLM) {
 243                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 244                 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 245                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 246         }
 247 }
 248
 249 static void _clk_pll_disable(struct clk_hw *hw)
 250 {
 251         struct tegra_clk_pll *pll = to_clk_pll(hw);
 252         u32 val;
 253
 254         val = pll_readl_base(pll);
 255         if (pll->flags & TEGRA_PLL_BYPASS)
 256                 val &= ~PLL_BASE_BYPASS;
 257         val &= ~PLL_BASE_ENABLE;
 258         pll_writel_base(val, pll);
 259
 260         if (pll->flags & TEGRA_PLLM) {
 261                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 262                 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 263                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 264         }
 265 }
 266
 267 static int clk_pll_enable(struct clk_hw *hw)
 268 {
 269         struct tegra_clk_pll *pll = to_clk_pll(hw);
 270         unsigned long flags = 0;
 271         int ret;
 272
 273         if (pll->lock)
 274                 spin_lock_irqsave(pll->lock, flags);
 275
 276         _clk_pll_enable(hw);
 277
 278         ret = clk_pll_wait_for_lock(pll);
 279
 280         if (pll->lock)
 281                 spin_unlock_irqrestore(pll->lock, flags);
 282
 283         return ret;
 284 }
 285
 286 static void clk_pll_disable(struct clk_hw *hw)
 287 {
 288         struct tegra_clk_pll *pll = to_clk_pll(hw);
 289         unsigned long flags = 0;
 290
 291         if (pll->lock)
 292                 spin_lock_irqsave(pll->lock, flags);
 293
 294         _clk_pll_disable(hw);
 295
 296         if (pll->lock)
 297                 spin_unlock_irqrestore(pll->lock, flags);
 298 }
 299
 300 static int _get_table_rate(struct clk_hw *hw,
 301                            struct tegra_clk_pll_freq_table *cfg,
 302                            unsigned long rate, unsigned long parent_rate)
 303 {
 304         struct tegra_clk_pll *pll = to_clk_pll(hw);
 305         struct tegra_clk_pll_freq_table *sel;
 306
 307         for (sel = pll->freq_table; sel->input_rate != 0; sel++)
 308                 if (sel->input_rate == parent_rate &&
 309                     sel->output_rate == rate)
 310                         break;
 311
 312         if (sel->input_rate == 0)
 313                 return -EINVAL;
 314
 315         cfg->input_rate = sel->input_rate;
 316         cfg->output_rate = sel->output_rate;
 317         cfg->m = sel->m;
 318         cfg->n = sel->n;
 319         cfg->p = sel->p;
 320         cfg->cpcon = sel->cpcon;
 321
 322         return 0;
 323 }
 324
 325 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 326                       unsigned long rate, unsigned long parent_rate)
 327 {
 328         struct tegra_clk_pll *pll = to_clk_pll(hw);
 329         struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 330         unsigned long cfreq;
 331         u32 p_div = 0;
 332
 333         switch (parent_rate) {
 334         case 12000000:
 335         case 26000000:
 336                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
 337                 break;
 338         case 13000000:
 339                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
 340                 break;
 341         case 16800000:
 342         case 19200000:
 343                 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
 344                 break;
 345         case 9600000:
 346         case 28800000:
 347                 /*
 348                  * PLL_P_OUT1 rate is not listed in PLLA table
 349                  */
 350                 cfreq = parent_rate/(parent_rate/1000000);
 351                 break;
 352         default:
 353                 pr_err("%s Unexpected reference rate %lu\n",
 354                        __func__, parent_rate);
 355                 BUG();
 356         }
 357
 358         /* Raise VCO to guarantee 0.5% accuracy */
 359         for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
 360              cfg->output_rate <<= 1)
 361                 p_div++;
 362
 363         cfg->m = parent_rate / cfreq;
 364         cfg->n = cfg->output_rate / cfreq;
 365         cfg->cpcon = OUT_OF_TABLE_CPCON;
 366
 367         if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
 368             (1 << p_div) > divp_max(pll)
 369             || cfg->output_rate > pll->params->vco_max) {
 370                 pr_err("%s: Failed to set %s rate %lu\n",
 371                        __func__, __clk_get_name(hw->clk), rate);
 372                 return -EINVAL;
 373         }
 374
 375         if (p_tohw) {
 376                 p_div = 1 << p_div;
 377                 while (p_tohw->pdiv) {
 378                         if (p_div <= p_tohw->pdiv) {
 379                                 cfg->p = p_tohw->hw_val;
 380                                 break;
 381                         }
 382                         p_tohw++;
 383                 }
 384                 if (!p_tohw->pdiv)
 385                         return -EINVAL;
 386         } else
 387                 cfg->p = p_div;
 388
 389         return 0;
 390 }
 391
 392 static void _update_pll_mnp(struct tegra_clk_pll *pll,
 393                             struct tegra_clk_pll_freq_table *cfg)
 394 {
 395         u32 val;
 396
 397         val = pll_readl_base(pll);
 398
 399         val &= ~((divm_mask(pll) << pll->divm_shift) |
 400                  (divn_mask(pll) << pll->divn_shift) |
 401                  (divp_mask(pll) << pll->divp_shift));
 402         val |= ((cfg->m << pll->divm_shift) |
 403                 (cfg->n << pll->divn_shift) |
 404                 (cfg->p << pll->divp_shift));
 405
 406         pll_writel_base(val, pll);
 407 }
 408
 409 static void _get_pll_mnp(struct tegra_clk_pll *pll,
 410                          struct tegra_clk_pll_freq_table *cfg)
 411 {
 412         u32 val;
 413
 414         val = pll_readl_base(pll);
 415
 416         cfg->m = (val >> pll->divm_shift) & (divm_mask(pll));
 417         cfg->n = (val >> pll->divn_shift) & (divn_mask(pll));
 418         cfg->p = (val >> pll->divp_shift) & (divp_mask(pll));
 419 }
 420
 421 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
 422                               struct tegra_clk_pll_freq_table *cfg,
 423                               unsigned long rate)
 424 {
 425         u32 val;
 426
 427         val = pll_readl_misc(pll);
 428
 429         val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
 430         val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
 431
 432         if (pll->flags & TEGRA_PLL_SET_LFCON) {
 433                 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
 434                 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
 435                         val |= 1 << PLL_MISC_LFCON_SHIFT;
 436         } else if (pll->flags & TEGRA_PLL_SET_DCCON) {
 437                 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
 438                 if (rate >= (pll->params->vco_max >> 1))
 439                         val |= 1 << PLL_MISC_DCCON_SHIFT;
 440         }
 441
 442         pll_writel_misc(val, pll);
 443 }
 444
 445 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 446                         unsigned long rate)
 447 {
 448         struct tegra_clk_pll *pll = to_clk_pll(hw);
 449         int state, ret = 0;
 450
 451         state = clk_pll_is_enabled(hw);
 452
 453         if (state)
 454                 _clk_pll_disable(hw);
 455
 456         _update_pll_mnp(pll, cfg);
 457
 458         if (pll->flags & TEGRA_PLL_HAS_CPCON)
 459                 _update_pll_cpcon(pll, cfg, rate);
 460
 461         if (state) {
 462                 _clk_pll_enable(hw);
 463                 ret = clk_pll_wait_for_lock(pll);
 464         }
 465
 466         return ret;
 467 }
 468
 469 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 470                         unsigned long parent_rate)
 471 {
 472         struct tegra_clk_pll *pll = to_clk_pll(hw);
 473         struct tegra_clk_pll_freq_table cfg, old_cfg;
 474         unsigned long flags = 0;
 475         int ret = 0;
 476
 477         if (pll->flags & TEGRA_PLL_FIXED) {
 478                 if (rate != pll->fixed_rate) {
 479                         pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
 480                                 __func__, __clk_get_name(hw->clk),
 481                                 pll->fixed_rate, rate);
 482                         return -EINVAL;
 483                 }
 484                 return 0;
 485         }
 486
 487         if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
 488             _calc_rate(hw, &cfg, rate, parent_rate))
 489                 return -EINVAL;
 490
 491         if (pll->lock)
 492                 spin_lock_irqsave(pll->lock, flags);
 493
 494         _get_pll_mnp(pll, &old_cfg);
 495
 496         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
 497                 ret = _program_pll(hw, &cfg, rate);
 498
 499         if (pll->lock)
 500                 spin_unlock_irqrestore(pll->lock, flags);
 501
 502         return ret;
 503 }
 504
 505 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 506                         unsigned long *prate)
 507 {
 508         struct tegra_clk_pll *pll = to_clk_pll(hw);
 509         struct tegra_clk_pll_freq_table cfg;
 510         u64 output_rate = *prate;
 511
 512         if (pll->flags & TEGRA_PLL_FIXED)
 513                 return pll->fixed_rate;
 514
 515         /* PLLM is used for memory; we do not change rate */
 516         if (pll->flags & TEGRA_PLLM)
 517                 return __clk_get_rate(hw->clk);
 518
 519         if (_get_table_rate(hw, &cfg, rate, *prate) &&
 520             _calc_rate(hw, &cfg, rate, *prate))
 521                 return -EINVAL;
 522
 523         output_rate *= cfg.n;
 524         do_div(output_rate, cfg.m * (1 << cfg.p));
 525
 526         return output_rate;
 527 }
 528
 529 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 530                                          unsigned long parent_rate)
 531 {
 532         struct tegra_clk_pll *pll = to_clk_pll(hw);
 533         struct tegra_clk_pll_freq_table cfg;
 534         struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 535         u32 val;
 536         u64 rate = parent_rate;
 537         int pdiv;
 538
 539         val = pll_readl_base(pll);
 540
 541         if ((pll->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
 542                 return parent_rate;
 543
 544         if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) {
 545                 struct tegra_clk_pll_freq_table sel;
 546                 if (_get_table_rate(hw, &sel, pll->fixed_rate, parent_rate)) {
 547                         pr_err("Clock %s has unknown fixed frequency\n",
 548                                __clk_get_name(hw->clk));
 549                         BUG();
 550                 }
 551                 return pll->fixed_rate;
 552         }
 553
 554         _get_pll_mnp(pll, &cfg);
 555
 556         if (p_tohw) {
 557                 while (p_tohw->pdiv) {
 558                         if (cfg.p == p_tohw->hw_val) {
 559                                 pdiv = p_tohw->pdiv;
 560                                 break;
 561                         }
 562                         p_tohw++;
 563                 }
 564
 565                 if (!p_tohw->pdiv) {
 566                         WARN_ON(1);
 567                         pdiv = 1;
 568                 }
 569         } else
 570                 pdiv = 1 << cfg.p;
 571
 572         cfg.m *= pdiv;
 573
 574         rate *= cfg.n;
 575         do_div(rate, cfg.m);
 576
 577         return rate;
 578 }
 579
 580 static int clk_plle_training(struct tegra_clk_pll *pll)
 581 {
 582         u32 val;
 583         unsigned long timeout;
 584
 585         if (!pll->pmc)
 586                 return -ENOSYS;
 587
 588         /*
 589          * PLLE is already disabled, and setup cleared;
 590          * create falling edge on PLLE IDDQ input.
 591          */
 592         val = readl(pll->pmc + PMC_SATA_PWRGT);
 593         val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 594         writel(val, pll->pmc + PMC_SATA_PWRGT);
 595
 596         val = readl(pll->pmc + PMC_SATA_PWRGT);
 597         val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
 598         writel(val, pll->pmc + PMC_SATA_PWRGT);
 599
 600         val = readl(pll->pmc + PMC_SATA_PWRGT);
 601         val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 602         writel(val, pll->pmc + PMC_SATA_PWRGT);
 603
 604         val = pll_readl_misc(pll);
 605
 606         timeout = jiffies + msecs_to_jiffies(100);
 607         while (1) {
 608                 val = pll_readl_misc(pll);
 609                 if (val & PLLE_MISC_READY)
 610                         break;
 611                 if (time_after(jiffies, timeout)) {
 612                         pr_err("%s: timeout waiting for PLLE\n", __func__);
 613                         return -EBUSY;
 614                 }
 615                 udelay(300);
 616         }
 617
 618         return 0;
 619 }
 620
 621 static int clk_plle_enable(struct clk_hw *hw)
 622 {
 623         struct tegra_clk_pll *pll = to_clk_pll(hw);
 624         unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
 625         struct tegra_clk_pll_freq_table sel;
 626         u32 val;
 627         int err;
 628
 629         if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate))
 630                 return -EINVAL;
 631
 632         clk_pll_disable(hw);
 633
 634         val = pll_readl_misc(pll);
 635         val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
 636         pll_writel_misc(val, pll);
 637
 638         val = pll_readl_misc(pll);
 639         if (!(val & PLLE_MISC_READY)) {
 640                 err = clk_plle_training(pll);
 641                 if (err)
 642                         return err;
 643         }
 644
 645         if (pll->flags & TEGRA_PLLE_CONFIGURE) {
 646                 /* configure dividers */
 647                 val = pll_readl_base(pll);
 648                 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
 649                 val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
 650                 val |= sel.m << pll->divm_shift;
 651                 val |= sel.n << pll->divn_shift;
 652                 val |= sel.p << pll->divp_shift;
 653                 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
 654                 pll_writel_base(val, pll);
 655         }
 656
 657         val = pll_readl_misc(pll);
 658         val |= PLLE_MISC_SETUP_VALUE;
 659         val |= PLLE_MISC_LOCK_ENABLE;
 660         pll_writel_misc(val, pll);
 661
 662         val = readl(pll->clk_base + PLLE_SS_CTRL);
 663         val |= PLLE_SS_DISABLE;
 664         writel(val, pll->clk_base + PLLE_SS_CTRL);
 665
 666         val |= pll_readl_base(pll);
 667         val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
 668         pll_writel_base(val, pll);
 669
 670         clk_pll_wait_for_lock(pll);
 671
 672         return 0;
 673 }
 674
 675 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
 676                                          unsigned long parent_rate)
 677 {
 678         struct tegra_clk_pll *pll = to_clk_pll(hw);
 679         u32 val = pll_readl_base(pll);
 680         u32 divn = 0, divm = 0, divp = 0;
 681         u64 rate = parent_rate;
 682
 683         divp = (val >> pll->divp_shift) & (divp_mask(pll));
 684         divn = (val >> pll->divn_shift) & (divn_mask(pll));
 685         divm = (val >> pll->divm_shift) & (divm_mask(pll));
 686         divm *= divp;
 687
 688         rate *= divn;
 689         do_div(rate, divm);
 690         return rate;
 691 }
 692
 693 const struct clk_ops tegra_clk_pll_ops = {
 694         .is_enabled = clk_pll_is_enabled,
 695         .enable = clk_pll_enable,
 696         .disable = clk_pll_disable,
 697         .recalc_rate = clk_pll_recalc_rate,
 698         .round_rate = clk_pll_round_rate,
 699         .set_rate = clk_pll_set_rate,
 700 };
 701
 702 const struct clk_ops tegra_clk_plle_ops = {
 703         .recalc_rate = clk_plle_recalc_rate,
 704         .is_enabled = clk_pll_is_enabled,
 705         .disable = clk_pll_disable,
 706         .enable = clk_plle_enable,
 707 };
 708
 709 #ifdef CONFIG_ARCH_TEGRA_114_SOC
 710
 711 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
 712                            unsigned long parent_rate)
 713 {
 714         if (parent_rate > pll_params->cf_max)
 715                 return 2;
 716         else
 717                 return 1;
 718 }
 719
 720 static int clk_pll_iddq_enable(struct clk_hw *hw)
 721 {
 722         struct tegra_clk_pll *pll = to_clk_pll(hw);
 723         unsigned long flags = 0;
 724
 725         u32 val;
 726         int ret;
 727
 728         if (pll->lock)
 729                 spin_lock_irqsave(pll->lock, flags);
 730
 731         val = pll_readl(pll->params->iddq_reg, pll);
 732         val &= ~BIT(pll->params->iddq_bit_idx);
 733         pll_writel(val, pll->params->iddq_reg, pll);
 734         udelay(2);
 735
 736         _clk_pll_enable(hw);
 737
 738         ret = clk_pll_wait_for_lock(pll);
 739
 740         if (pll->lock)
 741                 spin_unlock_irqrestore(pll->lock, flags);
 742
 743         return 0;
 744 }
 745
 746 static void clk_pll_iddq_disable(struct clk_hw *hw)
 747 {
 748         struct tegra_clk_pll *pll = to_clk_pll(hw);
 749         unsigned long flags = 0;
 750         u32 val;
 751
 752         if (pll->lock)
 753                 spin_lock_irqsave(pll->lock, flags);
 754
 755         _clk_pll_disable(hw);
 756
 757         val = pll_readl(pll->params->iddq_reg, pll);
 758         val |= BIT(pll->params->iddq_bit_idx);
 759         pll_writel(val, pll->params->iddq_reg, pll);
 760         udelay(2);
 761
 762         if (pll->lock)
 763                 spin_unlock_irqrestore(pll->lock, flags);
 764 }
 765
 766 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
 767                                 struct tegra_clk_pll_freq_table *cfg,
 768                                 unsigned long rate, unsigned long parent_rate)
 769 {
 770         struct tegra_clk_pll *pll = to_clk_pll(hw);
 771         unsigned int p;
 772
 773         if (!rate)
 774                 return -EINVAL;
 775
 776         p = DIV_ROUND_UP(pll->params->vco_min, rate);
 777         cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
 778         cfg->p = p;
 779         cfg->output_rate = rate * cfg->p;
 780         cfg->n = cfg->output_rate * cfg->m / parent_rate;
 781
 782         if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
 783                 return -EINVAL;
 784
 785         return 0;
 786 }
 787
 788 static int _pll_ramp_calc_pll(struct clk_hw *hw,
 789                               struct tegra_clk_pll_freq_table *cfg,
 790                               unsigned long rate, unsigned long parent_rate)
 791 {
 792         struct tegra_clk_pll *pll = to_clk_pll(hw);
 793         int err = 0;
 794
 795         err = _get_table_rate(hw, cfg, rate, parent_rate);
 796         if (err < 0)
 797                 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
 798         else if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
 799                         WARN_ON(1);
 800                         err = -EINVAL;
 801                         goto out;
 802         }
 803
 804         if (!cfg->p || (cfg->p >  pll->params->max_p))
 805                 err = -EINVAL;
 806
 807 out:
 808         return err;
 809 }
 810
 811 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
 812                                 unsigned long parent_rate)
 813 {
 814         struct tegra_clk_pll *pll = to_clk_pll(hw);
 815         struct tegra_clk_pll_freq_table cfg, old_cfg;
 816         unsigned long flags = 0;
 817         int ret = 0;
 818         u8 old_p;
 819
 820         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
 821         if (ret < 0)
 822                 return ret;
 823
 824         if (pll->lock)
 825                 spin_lock_irqsave(pll->lock, flags);
 826
 827         _get_pll_mnp(pll, &old_cfg);
 828
 829         old_p = pllxc_p[old_cfg.p];
 830         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_p != cfg.p) {
 831                 cfg.p -= 1;
 832                 ret = _program_pll(hw, &cfg, rate);
 833         }
 834
 835         if (pll->lock)
 836                 spin_unlock_irqrestore(pll->lock, flags);
 837
 838         return ret;
 839 }
 840
 841 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
 842                                 unsigned long *prate)
 843 {
 844         struct tegra_clk_pll_freq_table cfg;
 845         int ret = 0;
 846         u64 output_rate = *prate;
 847
 848         ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
 849         if (ret < 0)
 850                 return ret;
 851
 852         output_rate *= cfg.n;
 853         do_div(output_rate, cfg.m * cfg.p);
 854
 855         return output_rate;
 856 }
 857
 858 static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate,
 859                                 unsigned long parent_rate)
 860 {
 861         struct tegra_clk_pll_freq_table cfg;
 862         struct tegra_clk_pll *pll = to_clk_pll(hw);
 863         unsigned long flags = 0;
 864         int state, ret = 0;
 865         u32 val;
 866
 867         if (pll->lock)
 868                 spin_lock_irqsave(pll->lock, flags);
 869
 870         state = clk_pll_is_enabled(hw);
 871         if (state) {
 872                 if (rate != clk_get_rate(hw->clk)) {
 873                         pr_err("%s: Cannot change active PLLM\n", __func__);
 874                         ret = -EINVAL;
 875                         goto out;
 876                 }
 877                 goto out;
 878         }
 879
 880         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
 881         if (ret < 0)
 882                 goto out;
 883
 884         cfg.p -= 1;
 885
 886         val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE);
 887         if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
 888                 val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE_2);
 889                 val = cfg.p ? (val | PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) :
 890                         (val & ~PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK);
 891                 writel_relaxed(val, pll->pmc + PMC_PLLM_WB0_OVERRIDE_2);
 892
 893                 val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE);
 894                 val &= ~(divn_mask(pll) | divm_mask(pll));
 895                 val |= (cfg.m << pll->divm_shift) | (cfg.n << pll->divn_shift);
 896                 writel_relaxed(val, pll->pmc + PMC_PLLM_WB0_OVERRIDE);
 897         } else
 898                 _update_pll_mnp(pll, &cfg);
 899
 900
 901 out:
 902         if (pll->lock)
 903                 spin_unlock_irqrestore(pll->lock, flags);
 904
 905         return ret;
 906 }
 907
 908 static void _pllcx_strobe(struct tegra_clk_pll *pll)
 909 {
 910         u32 val;
 911
 912         val = pll_readl_misc(pll);
 913         val |= PLLCX_MISC_STROBE;
 914         pll_writel_misc(val, pll);
 915         udelay(2);
 916
 917         val &= ~PLLCX_MISC_STROBE;
 918         pll_writel_misc(val, pll);
 919 }
 920
 921 static int clk_pllc_enable(struct clk_hw *hw)
 922 {
 923         struct tegra_clk_pll *pll = to_clk_pll(hw);
 924         u32 val;
 925         int ret = 0;
 926         unsigned long flags = 0;
 927
 928         if (pll->lock)
 929                 spin_lock_irqsave(pll->lock, flags);
 930
 931         _clk_pll_enable(hw);
 932         udelay(2);
 933
 934         val = pll_readl_misc(pll);
 935         val &= ~PLLCX_MISC_RESET;
 936         pll_writel_misc(val, pll);
 937         udelay(2);
 938
 939         _pllcx_strobe(pll);
 940
 941         ret = clk_pll_wait_for_lock(pll);
 942
 943         if (pll->lock)
 944                 spin_unlock_irqrestore(pll->lock, flags);
 945
 946         return ret;
 947 }
 948
 949 static void _clk_pllc_disable(struct clk_hw *hw)
 950 {
 951         struct tegra_clk_pll *pll = to_clk_pll(hw);
 952         u32 val;
 953
 954         _clk_pll_disable(hw);
 955
 956         val = pll_readl_misc(pll);
 957         val |= PLLCX_MISC_RESET;
 958         pll_writel_misc(val, pll);
 959         udelay(2);
 960 }
 961
 962 static void clk_pllc_disable(struct clk_hw *hw)
 963 {
 964         struct tegra_clk_pll *pll = to_clk_pll(hw);
 965         unsigned long flags = 0;
 966
 967         if (pll->lock)
 968                 spin_lock_irqsave(pll->lock, flags);
 969
 970         _clk_pllc_disable(hw);
 971
 972         if (pll->lock)
 973                 spin_unlock_irqrestore(pll->lock, flags);
 974 }
 975
 976 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
 977                                         unsigned long input_rate, u32 n)
 978 {
 979         u32 val, n_threshold;
 980
 981         switch (input_rate) {
 982         case 12000000:
 983                 n_threshold = 70;
 984                 break;
 985         case 13000000:
 986         case 26000000:
 987                 n_threshold = 71;
 988                 break;
 989         case 16800000:
 990                 n_threshold = 55;
 991                 break;
 992         case 19200000:
 993                 n_threshold = 48;
 994                 break;
 995         default:
 996                 pr_err("%s: Unexpected reference rate %lu\n",
 997                         __func__, input_rate);
 998                 return -EINVAL;
 999         }
1000
1001         val = pll_readl_misc(pll);
1002         val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1003         val |= n <= n_threshold ?
1004                 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1005         pll_writel_misc(val, pll);
1006
1007         return 0;
1008 }
1009
1010 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1011                                 unsigned long parent_rate)
1012 {
1013         struct tegra_clk_pll_freq_table cfg;
1014         struct tegra_clk_pll *pll = to_clk_pll(hw);
1015         unsigned long flags = 0;
1016         int state, ret = 0;
1017         u32 val;
1018         u16 old_m, old_n;
1019         u8 old_p;
1020
1021         if (pll->lock)
1022                 spin_lock_irqsave(pll->lock, flags);
1023
1024         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1025         if (ret < 0)
1026                 goto out;
1027
1028         val = pll_readl_base(pll);
1029         old_m = (val >> pll->divm_shift) & (divm_mask(pll));
1030         old_n = (val >> pll->divn_shift) & (divn_mask(pll));
1031         old_p = pllcx_p[(val >> pll->divp_shift) & (divp_mask(pll))];
1032
1033         if (cfg.m != old_m) {
1034                 WARN_ON(1);
1035                 goto out;
1036         }
1037
1038         if (old_n == cfg.n && old_p == cfg.p)
1039                 goto out;
1040
1041         cfg.p -= 1;
1042
1043         state = clk_pll_is_enabled(hw);
1044         if (state)
1045                 _clk_pllc_disable(hw);
1046
1047         ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1048         if (ret < 0)
1049                 goto out;
1050
1051         _update_pll_mnp(pll, &cfg);
1052
1053         if (state)
1054                 ret = clk_pllc_enable(hw);
1055
1056 out:
1057         if (pll->lock)
1058                 spin_unlock_irqrestore(pll->lock, flags);
1059
1060         return ret;
1061 }
1062
1063 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1064                              struct tegra_clk_pll_freq_table *cfg,
1065                              unsigned long rate, unsigned long parent_rate)
1066 {
1067         u16 m, n;
1068         u64 output_rate = parent_rate;
1069
1070         m = _pll_fixed_mdiv(pll->params, parent_rate);
1071         n = rate * m / parent_rate;
1072
1073         output_rate *= n;
1074         do_div(output_rate, m);
1075
1076         if (cfg) {
1077                 cfg->m = m;
1078                 cfg->n = n;
1079         }
1080
1081         return output_rate;
1082 }
1083 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1084                                 unsigned long parent_rate)
1085 {
1086         struct tegra_clk_pll_freq_table cfg, old_cfg;
1087         struct tegra_clk_pll *pll = to_clk_pll(hw);
1088         unsigned long flags = 0;
1089         int state, ret = 0;
1090
1091         if (pll->lock)
1092                 spin_lock_irqsave(pll->lock, flags);
1093
1094         _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1095         _get_pll_mnp(pll, &old_cfg);
1096         cfg.p = old_cfg.p;
1097
1098         if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1099                 state = clk_pll_is_enabled(hw);
1100                 if (state)
1101                         _clk_pll_disable(hw);
1102
1103                 _update_pll_mnp(pll, &cfg);
1104
1105                 if (state) {
1106                         _clk_pll_enable(hw);
1107                         ret = clk_pll_wait_for_lock(pll);
1108                 }
1109         }
1110
1111         if (pll->lock)
1112                 spin_unlock_irqrestore(pll->lock, flags);
1113
1114         return ret;
1115 }
1116
1117 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1118                                          unsigned long parent_rate)
1119 {
1120         struct tegra_clk_pll_freq_table cfg;
1121         struct tegra_clk_pll *pll = to_clk_pll(hw);
1122         u64 rate = parent_rate;
1123
1124         _get_pll_mnp(pll, &cfg);
1125
1126         rate *= cfg.n;
1127         do_div(rate, cfg.m);
1128
1129         return rate;
1130 }
1131
1132 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1133                                  unsigned long *prate)
1134 {
1135         struct tegra_clk_pll *pll = to_clk_pll(hw);
1136
1137         return _pllre_calc_rate(pll, NULL, rate, *prate);
1138 }
1139
1140 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1141 {
1142         struct tegra_clk_pll *pll = to_clk_pll(hw);
1143         struct tegra_clk_pll_freq_table sel;
1144         u32 val;
1145         int ret;
1146         unsigned long flags = 0;
1147         unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
1148
1149         if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate))
1150                 return -EINVAL;
1151
1152         if (pll->lock)
1153                 spin_lock_irqsave(pll->lock, flags);
1154
1155         val = pll_readl_base(pll);
1156         val &= ~BIT(29); /* Disable lock override */
1157         pll_writel_base(val, pll);
1158
1159         val = pll_readl(pll->params->aux_reg, pll);
1160         val |= PLLE_AUX_ENABLE_SWCTL;
1161         val &= ~PLLE_AUX_SEQ_ENABLE;
1162         pll_writel(val, pll->params->aux_reg, pll);
1163         udelay(1);
1164
1165         val = pll_readl_misc(pll);
1166         val |= PLLE_MISC_LOCK_ENABLE;
1167         val |= PLLE_MISC_IDDQ_SW_CTRL;
1168         val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1169         val |= PLLE_MISC_PLLE_PTS;
1170         val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
1171         pll_writel_misc(val, pll);
1172         udelay(5);
1173
1174         val = pll_readl(PLLE_SS_CTRL, pll);
1175         val |= PLLE_SS_DISABLE;
1176         pll_writel(val, PLLE_SS_CTRL, pll);
1177
1178         val = pll_readl_base(pll);
1179         val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
1180         val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
1181         val |= sel.m << pll->divm_shift;
1182         val |= sel.n << pll->divn_shift;
1183         val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1184         pll_writel_base(val, pll);
1185         udelay(1);
1186
1187         _clk_pll_enable(hw);
1188         ret = clk_pll_wait_for_lock(pll);
1189
1190         if (ret < 0)
1191                 goto out;
1192
1193         /* TODO: enable hw control of xusb brick pll */
1194
1195 out:
1196         if (pll->lock)
1197                 spin_unlock_irqrestore(pll->lock, flags);
1198
1199         return ret;
1200 }
1201
1202 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1203 {
1204         struct tegra_clk_pll *pll = to_clk_pll(hw);
1205         unsigned long flags = 0;
1206         u32 val;
1207
1208         if (pll->lock)
1209                 spin_lock_irqsave(pll->lock, flags);
1210
1211         _clk_pll_disable(hw);
1212
1213         val = pll_readl_misc(pll);
1214         val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1215         pll_writel_misc(val, pll);
1216         udelay(1);
1217
1218         if (pll->lock)
1219                 spin_unlock_irqrestore(pll->lock, flags);
1220 }
1221 #endif
1222
1223 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1224                 void __iomem *pmc, unsigned long fixed_rate,
1225                 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
1226                 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
1227 {
1228         struct tegra_clk_pll *pll;
1229
1230         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1231         if (!pll)
1232                 return ERR_PTR(-ENOMEM);
1233
1234         pll->clk_base = clk_base;
1235         pll->pmc = pmc;
1236
1237         pll->freq_table = freq_table;
1238         pll->params = pll_params;
1239         pll->fixed_rate = fixed_rate;
1240         pll->flags = pll_flags;
1241         pll->lock = lock;
1242
1243         pll->divp_shift = PLL_BASE_DIVP_SHIFT;
1244         pll->divp_width = PLL_BASE_DIVP_WIDTH;
1245         pll->divn_shift = PLL_BASE_DIVN_SHIFT;
1246         pll->divn_width = PLL_BASE_DIVN_WIDTH;
1247         pll->divm_shift = PLL_BASE_DIVM_SHIFT;
1248         pll->divm_width = PLL_BASE_DIVM_WIDTH;
1249
1250         return pll;
1251 }
1252
1253 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1254                 const char *name, const char *parent_name, unsigned long flags,
1255                 const struct clk_ops *ops)
1256 {
1257         struct clk_init_data init;
1258
1259         init.name = name;
1260         init.ops = ops;
1261         init.flags = flags;
1262         init.parent_names = (parent_name ? &parent_name : NULL);
1263         init.num_parents = (parent_name ? 1 : 0);
1264
1265         /* Data in .init is copied by clk_register(), so stack variable OK */
1266         pll->hw.init = &init;
1267
1268         return clk_register(NULL, &pll->hw);
1269 }
1270
1271 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1272                 void __iomem *clk_base, void __iomem *pmc,
1273                 unsigned long flags, unsigned long fixed_rate,
1274                 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
1275                 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
1276 {
1277         struct tegra_clk_pll *pll;
1278         struct clk *clk;
1279
1280         pll_flags |= TEGRA_PLL_BYPASS;
1281         pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1282         pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1283                               freq_table, lock);
1284         if (IS_ERR(pll))
1285                 return ERR_CAST(pll);
1286
1287         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1288                                       &tegra_clk_pll_ops);
1289         if (IS_ERR(clk))
1290                 kfree(pll);
1291
1292         return clk;
1293 }
1294
1295 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1296                 void __iomem *clk_base, void __iomem *pmc,
1297                 unsigned long flags, unsigned long fixed_rate,
1298                 struct tegra_clk_pll_params *pll_params, u32 pll_flags,
1299                 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
1300 {
1301         struct tegra_clk_pll *pll;
1302         struct clk *clk;
1303
1304         pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
1305         pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1306         pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1307                               freq_table, lock);
1308         if (IS_ERR(pll))
1309                 return ERR_CAST(pll);
1310
1311         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1312                                       &tegra_clk_plle_ops);
1313         if (IS_ERR(clk))
1314                 kfree(pll);
1315
1316         return clk;
1317 }
1318
1319 #ifdef CONFIG_ARCH_TEGRA_114_SOC
1320 const struct clk_ops tegra_clk_pllxc_ops = {
1321         .is_enabled = clk_pll_is_enabled,
1322         .enable = clk_pll_iddq_enable,
1323         .disable = clk_pll_iddq_disable,
1324         .recalc_rate = clk_pll_recalc_rate,
1325         .round_rate = clk_pll_ramp_round_rate,
1326         .set_rate = clk_pllxc_set_rate,
1327 };
1328
1329 const struct clk_ops tegra_clk_pllm_ops = {
1330         .is_enabled = clk_pll_is_enabled,
1331         .enable = clk_pll_iddq_enable,
1332         .disable = clk_pll_iddq_disable,
1333         .recalc_rate = clk_pll_recalc_rate,
1334         .round_rate = clk_pll_ramp_round_rate,
1335         .set_rate = clk_pllm_set_rate,
1336 };
1337
1338 const struct clk_ops tegra_clk_pllc_ops = {
1339         .is_enabled = clk_pll_is_enabled,
1340         .enable = clk_pllc_enable,
1341         .disable = clk_pllc_disable,
1342         .recalc_rate = clk_pll_recalc_rate,
1343         .round_rate = clk_pll_ramp_round_rate,
1344         .set_rate = clk_pllc_set_rate,
1345 };
1346
1347 const struct clk_ops tegra_clk_pllre_ops = {
1348         .is_enabled = clk_pll_is_enabled,
1349         .enable = clk_pll_iddq_enable,
1350         .disable = clk_pll_iddq_disable,
1351         .recalc_rate = clk_pllre_recalc_rate,
1352         .round_rate = clk_pllre_round_rate,
1353         .set_rate = clk_pllre_set_rate,
1354 };
1355
1356 const struct clk_ops tegra_clk_plle_tegra114_ops = {
1357         .is_enabled =  clk_pll_is_enabled,
1358         .enable = clk_plle_tegra114_enable,
1359         .disable = clk_plle_tegra114_disable,
1360         .recalc_rate = clk_pll_recalc_rate,
1361 };
1362
1363
1364 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1365                           void __iomem *clk_base, void __iomem *pmc,
1366                           unsigned long flags, unsigned long fixed_rate,
1367                           struct tegra_clk_pll_params *pll_params,
1368                           u32 pll_flags,
1369                           struct tegra_clk_pll_freq_table *freq_table,
1370                           spinlock_t *lock)
1371 {
1372         struct tegra_clk_pll *pll;
1373         struct clk *clk;
1374
1375         if (!pll_params->pdiv_tohw)
1376                 return ERR_PTR(-EINVAL);
1377
1378         pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1379         pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1380                               freq_table, lock);
1381         if (IS_ERR(pll))
1382                 return ERR_CAST(pll);
1383
1384         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1385                                       &tegra_clk_pllxc_ops);
1386         if (IS_ERR(clk))
1387                 kfree(pll);
1388
1389         return clk;
1390 }
1391
1392 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1393                           void __iomem *clk_base, void __iomem *pmc,
1394                           unsigned long flags, unsigned long fixed_rate,
1395                           struct tegra_clk_pll_params *pll_params,
1396                           u32 pll_flags,
1397                           struct tegra_clk_pll_freq_table *freq_table,
1398                           spinlock_t *lock, unsigned long parent_rate)
1399 {
1400         u32 val;
1401         struct tegra_clk_pll *pll;
1402         struct clk *clk;
1403
1404         pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1405         pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1406                               freq_table, lock);
1407         if (IS_ERR(pll))
1408                 return ERR_CAST(pll);
1409
1410         /* program minimum rate by default */
1411
1412         val = pll_readl_base(pll);
1413         if (val & PLL_BASE_ENABLE)
1414                 WARN_ON(val & pll_params->iddq_bit_idx);
1415         else {
1416                 int m;
1417
1418                 m = _pll_fixed_mdiv(pll_params, parent_rate);
1419                 val = m << PLL_BASE_DIVM_SHIFT;
1420                 val |= (pll_params->vco_min / parent_rate)
1421                                 << PLL_BASE_DIVN_SHIFT;
1422                 pll_writel_base(val, pll);
1423         }
1424
1425         /* disable lock override */
1426
1427         val = pll_readl_misc(pll);
1428         val &= ~BIT(29);
1429         pll_writel_misc(val, pll);
1430
1431         pll_flags |= TEGRA_PLL_LOCK_MISC;
1432         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1433                                       &tegra_clk_pllre_ops);
1434         if (IS_ERR(clk))
1435                 kfree(pll);
1436
1437         return clk;
1438 }
1439
1440 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1441                           void __iomem *clk_base, void __iomem *pmc,
1442                           unsigned long flags, unsigned long fixed_rate,
1443                           struct tegra_clk_pll_params *pll_params,
1444                           u32 pll_flags,
1445                           struct tegra_clk_pll_freq_table *freq_table,
1446                           spinlock_t *lock)
1447 {
1448         struct tegra_clk_pll *pll;
1449         struct clk *clk;
1450
1451         if (!pll_params->pdiv_tohw)
1452                 return ERR_PTR(-EINVAL);
1453
1454         pll_flags |= TEGRA_PLL_BYPASS;
1455         pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1456         pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1457                               freq_table, lock);
1458         if (IS_ERR(pll))
1459                 return ERR_CAST(pll);
1460
1461         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1462                                       &tegra_clk_pllm_ops);
1463         if (IS_ERR(clk))
1464                 kfree(pll);
1465
1466         return clk;
1467 }
1468
1469 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1470                           void __iomem *clk_base, void __iomem *pmc,
1471                           unsigned long flags, unsigned long fixed_rate,
1472                           struct tegra_clk_pll_params *pll_params,
1473                           u32 pll_flags,
1474                           struct tegra_clk_pll_freq_table *freq_table,
1475                           spinlock_t *lock)
1476 {
1477         struct clk *parent, *clk;
1478         struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
1479         struct tegra_clk_pll *pll;
1480         struct tegra_clk_pll_freq_table cfg;
1481         unsigned long parent_rate;
1482
1483         if (!p_tohw)
1484                 return ERR_PTR(-EINVAL);
1485
1486         parent = __clk_lookup(parent_name);
1487         if (IS_ERR(parent)) {
1488                 WARN(1, "parent clk %s of %s must be registered first\n",
1489                         name, parent_name);
1490                 return ERR_PTR(-EINVAL);
1491         }
1492
1493         pll_flags |= TEGRA_PLL_BYPASS;
1494         pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
1495                               freq_table, lock);
1496         if (IS_ERR(pll))
1497                 return ERR_CAST(pll);
1498
1499         parent_rate = __clk_get_rate(parent);
1500
1501         /*
1502          * Most of PLLC register fields are shadowed, and can not be read
1503          * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
1504          * Initialize PLL to default state: disabled, reset; shadow registers
1505          * loaded with default parameters; dividers are preset for half of
1506          * minimum VCO rate (the latter assured that shadowed divider settings
1507          * are within supported range).
1508          */
1509
1510         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1511         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1512
1513         while (p_tohw->pdiv) {
1514                 if (p_tohw->pdiv == 2) {
1515                         cfg.p = p_tohw->hw_val;
1516                         break;
1517                 }
1518                 p_tohw++;
1519         }
1520
1521         if (!p_tohw->pdiv) {
1522                 WARN_ON(1);
1523                 return ERR_PTR(-EINVAL);
1524         }
1525
1526         pll_writel_base(0, pll);
1527         _update_pll_mnp(pll, &cfg);
1528
1529         pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
1530         pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
1531         pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
1532         pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
1533
1534         _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1535
1536         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1537                                       &tegra_clk_pllc_ops);
1538         if (IS_ERR(clk))
1539                 kfree(pll);
1540
1541         return clk;
1542 }
1543
1544 struct clk *tegra_clk_register_plle_tegra114(const char *name,
1545                                 const char *parent_name,
1546                                 void __iomem *clk_base, unsigned long flags,
1547                                 unsigned long fixed_rate,
1548                                 struct tegra_clk_pll_params *pll_params,
1549                                 struct tegra_clk_pll_freq_table *freq_table,
1550                                 spinlock_t *lock)
1551 {
1552         struct tegra_clk_pll *pll;
1553         struct clk *clk;
1554         u32 val, val_aux;
1555
1556         pll = _tegra_init_pll(clk_base, NULL, fixed_rate, pll_params,
1557                               TEGRA_PLL_HAS_LOCK_ENABLE, freq_table, lock);
1558         if (IS_ERR(pll))
1559                 return ERR_CAST(pll);
1560
1561         /* ensure parent is set to pll_re_vco */
1562
1563         val = pll_readl_base(pll);
1564         val_aux = pll_readl(pll_params->aux_reg, pll);
1565
1566         if (val & PLL_BASE_ENABLE) {
1567                 if (!(val_aux & PLLE_AUX_PLLRE_SEL))
1568                         WARN(1, "pll_e enabled with unsupported parent %s\n",
1569                           (val & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : "pll_ref");
1570         } else {
1571                 val_aux |= PLLE_AUX_PLLRE_SEL;
1572                 pll_writel(val, pll_params->aux_reg, pll);
1573         }
1574
1575         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1576                                       &tegra_clk_plle_tegra114_ops);
1577         if (IS_ERR(clk))
1578                 kfree(pll);
1579
1580         return clk;
1581 }
1582 #endif