drivers/clk/tegra/clk-pll.c

   1 /*
   2  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/slab.h>
  18 #include <linux/io.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/clk.h>
  23
  24 #include "clk.h"
  25
  26 #define PLL_BASE_BYPASS BIT(31)
  27 #define PLL_BASE_ENABLE BIT(30)
  28 #define PLL_BASE_REF_ENABLE BIT(29)
  29 #define PLL_BASE_OVERRIDE BIT(28)
  30
  31 #define PLL_BASE_DIVP_SHIFT 20
  32 #define PLL_BASE_DIVP_WIDTH 3
  33 #define PLL_BASE_DIVN_SHIFT 8
  34 #define PLL_BASE_DIVN_WIDTH 10
  35 #define PLL_BASE_DIVM_SHIFT 0
  36 #define PLL_BASE_DIVM_WIDTH 5
  37 #define PLLU_POST_DIVP_MASK 0x1
  38
  39 #define PLL_MISC_DCCON_SHIFT 20
  40 #define PLL_MISC_CPCON_SHIFT 8
  41 #define PLL_MISC_CPCON_WIDTH 4
  42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
  43 #define PLL_MISC_LFCON_SHIFT 4
  44 #define PLL_MISC_LFCON_WIDTH 4
  45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
  46 #define PLL_MISC_VCOCON_SHIFT 0
  47 #define PLL_MISC_VCOCON_WIDTH 4
  48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
  49
  50 #define OUT_OF_TABLE_CPCON 8
  51
  52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
  53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
  54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
  55
  56 #define PLL_POST_LOCK_DELAY 50
  57
  58 #define PLLDU_LFCON_SET_DIVN 600
  59
  60 #define PLLE_BASE_DIVCML_SHIFT 24
  61 #define PLLE_BASE_DIVCML_MASK 0xf
  62 #define PLLE_BASE_DIVP_SHIFT 16
  63 #define PLLE_BASE_DIVP_WIDTH 6
  64 #define PLLE_BASE_DIVN_SHIFT 8
  65 #define PLLE_BASE_DIVN_WIDTH 8
  66 #define PLLE_BASE_DIVM_SHIFT 0
  67 #define PLLE_BASE_DIVM_WIDTH 8
  68
  69 #define PLLE_MISC_SETUP_BASE_SHIFT 16
  70 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
  71 #define PLLE_MISC_LOCK_ENABLE BIT(9)
  72 #define PLLE_MISC_READY BIT(15)
  73 #define PLLE_MISC_SETUP_EX_SHIFT 2
  74 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
  75 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK |       \
  76                               PLLE_MISC_SETUP_EX_MASK)
  77 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
  78
  79 #define PLLE_SS_CTRL 0x68
  80 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
  81 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
  82 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
  83 #define PLLE_SS_CNTL_CENTER BIT(14)
  84 #define PLLE_SS_CNTL_INVERT BIT(15)
  85 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
  86                                 PLLE_SS_CNTL_SSC_BYP)
  87 #define PLLE_SS_MAX_MASK 0x1ff
  88 #define PLLE_SS_MAX_VAL 0x25
  89 #define PLLE_SS_INC_MASK (0xff << 16)
  90 #define PLLE_SS_INC_VAL (0x1 << 16)
  91 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
  92 #define PLLE_SS_INCINTRV_VAL (0x20 << 24)
  93 #define PLLE_SS_COEFFICIENTS_MASK \
  94         (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
  95 #define PLLE_SS_COEFFICIENTS_VAL \
  96         (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)
  97
  98 #define PLLE_AUX_PLLP_SEL       BIT(2)
  99 #define PLLE_AUX_ENABLE_SWCTL   BIT(4)
 100 #define PLLE_AUX_SEQ_ENABLE     BIT(24)
 101 #define PLLE_AUX_PLLRE_SEL      BIT(28)
 102
 103 #define PLLE_MISC_PLLE_PTS      BIT(8)
 104 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
 105 #define PLLE_MISC_IDDQ_SW_CTRL  BIT(14)
 106 #define PLLE_MISC_VREG_BG_CTRL_SHIFT    4
 107 #define PLLE_MISC_VREG_BG_CTRL_MASK     (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
 108 #define PLLE_MISC_VREG_CTRL_SHIFT       2
 109 #define PLLE_MISC_VREG_CTRL_MASK        (2 << PLLE_MISC_VREG_CTRL_SHIFT)
 110
 111 #define PLLCX_MISC_STROBE       BIT(31)
 112 #define PLLCX_MISC_RESET        BIT(30)
 113 #define PLLCX_MISC_SDM_DIV_SHIFT 28
 114 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
 115 #define PLLCX_MISC_FILT_DIV_SHIFT 26
 116 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
 117 #define PLLCX_MISC_ALPHA_SHIFT 18
 118 #define PLLCX_MISC_DIV_LOW_RANGE \
 119                 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 120                 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
 121 #define PLLCX_MISC_DIV_HIGH_RANGE \
 122                 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 123                 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
 124 #define PLLCX_MISC_COEF_LOW_RANGE \
 125                 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
 126 #define PLLCX_MISC_KA_SHIFT 2
 127 #define PLLCX_MISC_KB_SHIFT 9
 128 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
 129                             (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
 130                             PLLCX_MISC_DIV_LOW_RANGE | \
 131                             PLLCX_MISC_RESET)
 132 #define PLLCX_MISC1_DEFAULT 0x000d2308
 133 #define PLLCX_MISC2_DEFAULT 0x30211200
 134 #define PLLCX_MISC3_DEFAULT 0x200
 135
 136 #define PMC_SATA_PWRGT 0x1ac
 137 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
 138 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
 139
 140 #define PLLSS_MISC_KCP          0
 141 #define PLLSS_MISC_KVCO         0
 142 #define PLLSS_MISC_SETUP        0
 143 #define PLLSS_EN_SDM            0
 144 #define PLLSS_EN_SSC            0
 145 #define PLLSS_EN_DITHER2        0
 146 #define PLLSS_EN_DITHER         1
 147 #define PLLSS_SDM_RESET         0
 148 #define PLLSS_CLAMP             0
 149 #define PLLSS_SDM_SSC_MAX       0
 150 #define PLLSS_SDM_SSC_MIN       0
 151 #define PLLSS_SDM_SSC_STEP      0
 152 #define PLLSS_SDM_DIN           0
 153 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
 154                             (PLLSS_MISC_KVCO << 24) | \
 155                             PLLSS_MISC_SETUP)
 156 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
 157                            (PLLSS_EN_SSC << 30) | \
 158                            (PLLSS_EN_DITHER2 << 29) | \
 159                            (PLLSS_EN_DITHER << 28) | \
 160                            (PLLSS_SDM_RESET) << 27 | \
 161                            (PLLSS_CLAMP << 22))
 162 #define PLLSS_CTRL1_DEFAULT \
 163                         ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
 164 #define PLLSS_CTRL2_DEFAULT \
 165                         ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
 166 #define PLLSS_LOCK_OVERRIDE     BIT(24)
 167 #define PLLSS_REF_SRC_SEL_SHIFT 25
 168 #define PLLSS_REF_SRC_SEL_MASK  (3 << PLLSS_REF_SRC_SEL_SHIFT)
 169
 170 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
 171 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
 172 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
 173 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
 174
 175 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
 176 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
 177 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
 178 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
 179
 180 #define mask(w) ((1 << (w)) - 1)
 181 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
 182 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
 183 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
 184                       mask(p->params->div_nmp->divp_width))
 185
 186 #define divm_shift(p) (p)->params->div_nmp->divm_shift
 187 #define divn_shift(p) (p)->params->div_nmp->divn_shift
 188 #define divp_shift(p) (p)->params->div_nmp->divp_shift
 189
 190 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
 191 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
 192 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
 193
 194 #define divm_max(p) (divm_mask(p))
 195 #define divn_max(p) (divn_mask(p))
 196 #define divp_max(p) (1 << (divp_mask(p)))
 197
 198 static struct div_nmp default_nmp = {
 199         .divn_shift = PLL_BASE_DIVN_SHIFT,
 200         .divn_width = PLL_BASE_DIVN_WIDTH,
 201         .divm_shift = PLL_BASE_DIVM_SHIFT,
 202         .divm_width = PLL_BASE_DIVM_WIDTH,
 203         .divp_shift = PLL_BASE_DIVP_SHIFT,
 204         .divp_width = PLL_BASE_DIVP_WIDTH,
 205 };
 206
 207 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
 208 {
 209         u32 val;
 210
 211         if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
 212                 return;
 213
 214         if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
 215                 return;
 216
 217         val = pll_readl_misc(pll);
 218         val |= BIT(pll->params->lock_enable_bit_idx);
 219         pll_writel_misc(val, pll);
 220 }
 221
 222 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
 223 {
 224         int i;
 225         u32 val, lock_mask;
 226         void __iomem *lock_addr;
 227
 228         if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
 229                 udelay(pll->params->lock_delay);
 230                 return 0;
 231         }
 232
 233         lock_addr = pll->clk_base;
 234         if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
 235                 lock_addr += pll->params->misc_reg;
 236         else
 237                 lock_addr += pll->params->base_reg;
 238
 239         lock_mask = pll->params->lock_mask;
 240
 241         for (i = 0; i < pll->params->lock_delay; i++) {
 242                 val = readl_relaxed(lock_addr);
 243                 if ((val & lock_mask) == lock_mask) {
 244                         udelay(PLL_POST_LOCK_DELAY);
 245                         return 0;
 246                 }
 247                 udelay(2); /* timeout = 2 * lock time */
 248         }
 249
 250         pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
 251                __clk_get_name(pll->hw.clk));
 252
 253         return -1;
 254 }
 255
 256 static int clk_pll_is_enabled(struct clk_hw *hw)
 257 {
 258         struct tegra_clk_pll *pll = to_clk_pll(hw);
 259         u32 val;
 260
 261         if (pll->params->flags & TEGRA_PLLM) {
 262                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 263                 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
 264                         return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
 265         }
 266
 267         val = pll_readl_base(pll);
 268
 269         return val & PLL_BASE_ENABLE ? 1 : 0;
 270 }
 271
 272 static void _clk_pll_enable(struct clk_hw *hw)
 273 {
 274         struct tegra_clk_pll *pll = to_clk_pll(hw);
 275         u32 val;
 276
 277         clk_pll_enable_lock(pll);
 278
 279         val = pll_readl_base(pll);
 280         if (pll->params->flags & TEGRA_PLL_BYPASS)
 281                 val &= ~PLL_BASE_BYPASS;
 282         val |= PLL_BASE_ENABLE;
 283         pll_writel_base(val, pll);
 284
 285         if (pll->params->flags & TEGRA_PLLM) {
 286                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 287                 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 288                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 289         }
 290 }
 291
 292 static void _clk_pll_disable(struct clk_hw *hw)
 293 {
 294         struct tegra_clk_pll *pll = to_clk_pll(hw);
 295         u32 val;
 296
 297         val = pll_readl_base(pll);
 298         if (pll->params->flags & TEGRA_PLL_BYPASS)
 299                 val &= ~PLL_BASE_BYPASS;
 300         val &= ~PLL_BASE_ENABLE;
 301         pll_writel_base(val, pll);
 302
 303         if (pll->params->flags & TEGRA_PLLM) {
 304                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 305                 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 306                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 307         }
 308 }
 309
 310 static int clk_pll_enable(struct clk_hw *hw)
 311 {
 312         struct tegra_clk_pll *pll = to_clk_pll(hw);
 313         unsigned long flags = 0;
 314         int ret;
 315
 316         if (pll->lock)
 317                 spin_lock_irqsave(pll->lock, flags);
 318
 319         _clk_pll_enable(hw);
 320
 321         ret = clk_pll_wait_for_lock(pll);
 322
 323         if (pll->lock)
 324                 spin_unlock_irqrestore(pll->lock, flags);
 325
 326         return ret;
 327 }
 328
 329 static void clk_pll_disable(struct clk_hw *hw)
 330 {
 331         struct tegra_clk_pll *pll = to_clk_pll(hw);
 332         unsigned long flags = 0;
 333
 334         if (pll->lock)
 335                 spin_lock_irqsave(pll->lock, flags);
 336
 337         _clk_pll_disable(hw);
 338
 339         if (pll->lock)
 340                 spin_unlock_irqrestore(pll->lock, flags);
 341 }
 342
 343 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
 344 {
 345         struct tegra_clk_pll *pll = to_clk_pll(hw);
 346         struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 347
 348         if (p_tohw) {
 349                 while (p_tohw->pdiv) {
 350                         if (p_div <= p_tohw->pdiv)
 351                                 return p_tohw->hw_val;
 352                         p_tohw++;
 353                 }
 354                 return -EINVAL;
 355         }
 356         return -EINVAL;
 357 }
 358
 359 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
 360 {
 361         struct tegra_clk_pll *pll = to_clk_pll(hw);
 362         struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 363
 364         if (p_tohw) {
 365                 while (p_tohw->pdiv) {
 366                         if (p_div_hw == p_tohw->hw_val)
 367                                 return p_tohw->pdiv;
 368                         p_tohw++;
 369                 }
 370                 return -EINVAL;
 371         }
 372
 373         return 1 << p_div_hw;
 374 }
 375
 376 static int _get_table_rate(struct clk_hw *hw,
 377                            struct tegra_clk_pll_freq_table *cfg,
 378                            unsigned long rate, unsigned long parent_rate)
 379 {
 380         struct tegra_clk_pll *pll = to_clk_pll(hw);
 381         struct tegra_clk_pll_freq_table *sel;
 382
 383         for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
 384                 if (sel->input_rate == parent_rate &&
 385                     sel->output_rate == rate)
 386                         break;
 387
 388         if (sel->input_rate == 0)
 389                 return -EINVAL;
 390
 391         cfg->input_rate = sel->input_rate;
 392         cfg->output_rate = sel->output_rate;
 393         cfg->m = sel->m;
 394         cfg->n = sel->n;
 395         cfg->p = sel->p;
 396         cfg->cpcon = sel->cpcon;
 397
 398         return 0;
 399 }
 400
 401 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 402                       unsigned long rate, unsigned long parent_rate)
 403 {
 404         struct tegra_clk_pll *pll = to_clk_pll(hw);
 405         unsigned long cfreq;
 406         u32 p_div = 0;
 407         int ret;
 408
 409         switch (parent_rate) {
 410         case 12000000:
 411         case 26000000:
 412                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
 413                 break;
 414         case 13000000:
 415                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
 416                 break;
 417         case 16800000:
 418         case 19200000:
 419                 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
 420                 break;
 421         case 9600000:
 422         case 28800000:
 423                 /*
 424                  * PLL_P_OUT1 rate is not listed in PLLA table
 425                  */
 426                 cfreq = parent_rate/(parent_rate/1000000);
 427                 break;
 428         default:
 429                 pr_err("%s Unexpected reference rate %lu\n",
 430                        __func__, parent_rate);
 431                 BUG();
 432         }
 433
 434         /* Raise VCO to guarantee 0.5% accuracy */
 435         for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
 436              cfg->output_rate <<= 1)
 437                 p_div++;
 438
 439         cfg->m = parent_rate / cfreq;
 440         cfg->n = cfg->output_rate / cfreq;
 441         cfg->cpcon = OUT_OF_TABLE_CPCON;
 442
 443         if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
 444             (1 << p_div) > divp_max(pll)
 445             || cfg->output_rate > pll->params->vco_max) {
 446                 return -EINVAL;
 447         }
 448
 449         cfg->output_rate >>= p_div;
 450
 451         if (pll->params->pdiv_tohw) {
 452                 ret = _p_div_to_hw(hw, 1 << p_div);
 453                 if (ret < 0)
 454                         return ret;
 455                 else
 456                         cfg->p = ret;
 457         } else
 458                 cfg->p = p_div;
 459
 460         return 0;
 461 }
 462
 463 static void _update_pll_mnp(struct tegra_clk_pll *pll,
 464                             struct tegra_clk_pll_freq_table *cfg)
 465 {
 466         u32 val;
 467         struct tegra_clk_pll_params *params = pll->params;
 468         struct div_nmp *div_nmp = params->div_nmp;
 469
 470         if ((params->flags & TEGRA_PLLM) &&
 471                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 472                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 473                 val = pll_override_readl(params->pmc_divp_reg, pll);
 474                 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
 475                 val |= cfg->p << div_nmp->override_divp_shift;
 476                 pll_override_writel(val, params->pmc_divp_reg, pll);
 477
 478                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 479                 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) |
 480                         ~(divn_mask(pll) << div_nmp->override_divn_shift);
 481                 val |= (cfg->m << div_nmp->override_divm_shift) |
 482                         (cfg->n << div_nmp->override_divn_shift);
 483                 pll_override_writel(val, params->pmc_divnm_reg, pll);
 484         } else {
 485                 val = pll_readl_base(pll);
 486
 487                 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
 488                          divp_mask_shifted(pll));
 489
 490                 val |= (cfg->m << divm_shift(pll)) |
 491                        (cfg->n << divn_shift(pll)) |
 492                        (cfg->p << divp_shift(pll));
 493
 494                 pll_writel_base(val, pll);
 495         }
 496 }
 497
 498 static void _get_pll_mnp(struct tegra_clk_pll *pll,
 499                          struct tegra_clk_pll_freq_table *cfg)
 500 {
 501         u32 val;
 502         struct tegra_clk_pll_params *params = pll->params;
 503         struct div_nmp *div_nmp = params->div_nmp;
 504
 505         if ((params->flags & TEGRA_PLLM) &&
 506                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 507                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 508                 val = pll_override_readl(params->pmc_divp_reg, pll);
 509                 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
 510
 511                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 512                 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
 513                 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
 514         }  else {
 515                 val = pll_readl_base(pll);
 516
 517                 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
 518                 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
 519                 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
 520         }
 521 }
 522
 523 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
 524                               struct tegra_clk_pll_freq_table *cfg,
 525                               unsigned long rate)
 526 {
 527         u32 val;
 528
 529         val = pll_readl_misc(pll);
 530
 531         val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
 532         val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
 533
 534         if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
 535                 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
 536                 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
 537                         val |= 1 << PLL_MISC_LFCON_SHIFT;
 538         } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
 539                 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
 540                 if (rate >= (pll->params->vco_max >> 1))
 541                         val |= 1 << PLL_MISC_DCCON_SHIFT;
 542         }
 543
 544         pll_writel_misc(val, pll);
 545 }
 546
 547 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 548                         unsigned long rate)
 549 {
 550         struct tegra_clk_pll *pll = to_clk_pll(hw);
 551         int state, ret = 0;
 552
 553         state = clk_pll_is_enabled(hw);
 554
 555         if (state)
 556                 _clk_pll_disable(hw);
 557
 558         _update_pll_mnp(pll, cfg);
 559
 560         if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
 561                 _update_pll_cpcon(pll, cfg, rate);
 562
 563         if (state) {
 564                 _clk_pll_enable(hw);
 565                 ret = clk_pll_wait_for_lock(pll);
 566         }
 567
 568         return ret;
 569 }
 570
 571 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 572                         unsigned long parent_rate)
 573 {
 574         struct tegra_clk_pll *pll = to_clk_pll(hw);
 575         struct tegra_clk_pll_freq_table cfg, old_cfg;
 576         unsigned long flags = 0;
 577         int ret = 0;
 578
 579         if (pll->params->flags & TEGRA_PLL_FIXED) {
 580                 if (rate != pll->params->fixed_rate) {
 581                         pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
 582                                 __func__, __clk_get_name(hw->clk),
 583                                 pll->params->fixed_rate, rate);
 584                         return -EINVAL;
 585                 }
 586                 return 0;
 587         }
 588
 589         if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
 590             _calc_rate(hw, &cfg, rate, parent_rate)) {
 591                 pr_err("%s: Failed to set %s rate %lu\n", __func__,
 592                        __clk_get_name(hw->clk), rate);
 593                 WARN_ON(1);
 594                 return -EINVAL;
 595         }
 596         if (pll->lock)
 597                 spin_lock_irqsave(pll->lock, flags);
 598
 599         _get_pll_mnp(pll, &old_cfg);
 600
 601         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
 602                 ret = _program_pll(hw, &cfg, rate);
 603
 604         if (pll->lock)
 605                 spin_unlock_irqrestore(pll->lock, flags);
 606
 607         return ret;
 608 }
 609
 610 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 611                         unsigned long *prate)
 612 {
 613         struct tegra_clk_pll *pll = to_clk_pll(hw);
 614         struct tegra_clk_pll_freq_table cfg;
 615
 616         if (pll->params->flags & TEGRA_PLL_FIXED)
 617                 return pll->params->fixed_rate;
 618
 619         /* PLLM is used for memory; we do not change rate */
 620         if (pll->params->flags & TEGRA_PLLM)
 621                 return __clk_get_rate(hw->clk);
 622
 623         if (_get_table_rate(hw, &cfg, rate, *prate) &&
 624             _calc_rate(hw, &cfg, rate, *prate))
 625                 return -EINVAL;
 626
 627         return cfg.output_rate;
 628 }
 629
 630 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 631                                          unsigned long parent_rate)
 632 {
 633         struct tegra_clk_pll *pll = to_clk_pll(hw);
 634         struct tegra_clk_pll_freq_table cfg;
 635         u32 val;
 636         u64 rate = parent_rate;
 637         int pdiv;
 638
 639         val = pll_readl_base(pll);
 640
 641         if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
 642                 return parent_rate;
 643
 644         if ((pll->params->flags & TEGRA_PLL_FIXED) &&
 645                         !(val & PLL_BASE_OVERRIDE)) {
 646                 struct tegra_clk_pll_freq_table sel;
 647                 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
 648                                         parent_rate)) {
 649                         pr_err("Clock %s has unknown fixed frequency\n",
 650                                __clk_get_name(hw->clk));
 651                         BUG();
 652                 }
 653                 return pll->params->fixed_rate;
 654         }
 655
 656         _get_pll_mnp(pll, &cfg);
 657
 658         pdiv = _hw_to_p_div(hw, cfg.p);
 659         if (pdiv < 0) {
 660                 WARN_ON(1);
 661                 pdiv = 1;
 662         }
 663
 664         cfg.m *= pdiv;
 665
 666         rate *= cfg.n;
 667         do_div(rate, cfg.m);
 668
 669         return rate;
 670 }
 671
 672 static int clk_plle_training(struct tegra_clk_pll *pll)
 673 {
 674         u32 val;
 675         unsigned long timeout;
 676
 677         if (!pll->pmc)
 678                 return -ENOSYS;
 679
 680         /*
 681          * PLLE is already disabled, and setup cleared;
 682          * create falling edge on PLLE IDDQ input.
 683          */
 684         val = readl(pll->pmc + PMC_SATA_PWRGT);
 685         val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 686         writel(val, pll->pmc + PMC_SATA_PWRGT);
 687
 688         val = readl(pll->pmc + PMC_SATA_PWRGT);
 689         val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
 690         writel(val, pll->pmc + PMC_SATA_PWRGT);
 691
 692         val = readl(pll->pmc + PMC_SATA_PWRGT);
 693         val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 694         writel(val, pll->pmc + PMC_SATA_PWRGT);
 695
 696         val = pll_readl_misc(pll);
 697
 698         timeout = jiffies + msecs_to_jiffies(100);
 699         while (1) {
 700                 val = pll_readl_misc(pll);
 701                 if (val & PLLE_MISC_READY)
 702                         break;
 703                 if (time_after(jiffies, timeout)) {
 704                         pr_err("%s: timeout waiting for PLLE\n", __func__);
 705                         return -EBUSY;
 706                 }
 707                 udelay(300);
 708         }
 709
 710         return 0;
 711 }
 712
 713 static int clk_plle_enable(struct clk_hw *hw)
 714 {
 715         struct tegra_clk_pll *pll = to_clk_pll(hw);
 716         unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
 717         struct tegra_clk_pll_freq_table sel;
 718         u32 val;
 719         int err;
 720
 721         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
 722                 return -EINVAL;
 723
 724         clk_pll_disable(hw);
 725
 726         val = pll_readl_misc(pll);
 727         val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
 728         pll_writel_misc(val, pll);
 729
 730         val = pll_readl_misc(pll);
 731         if (!(val & PLLE_MISC_READY)) {
 732                 err = clk_plle_training(pll);
 733                 if (err)
 734                         return err;
 735         }
 736
 737         if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
 738                 /* configure dividers */
 739                 val = pll_readl_base(pll);
 740                 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
 741                          divm_mask_shifted(pll));
 742                 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
 743                 val |= sel.m << divm_shift(pll);
 744                 val |= sel.n << divn_shift(pll);
 745                 val |= sel.p << divp_shift(pll);
 746                 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
 747                 pll_writel_base(val, pll);
 748         }
 749
 750         val = pll_readl_misc(pll);
 751         val |= PLLE_MISC_SETUP_VALUE;
 752         val |= PLLE_MISC_LOCK_ENABLE;
 753         pll_writel_misc(val, pll);
 754
 755         val = readl(pll->clk_base + PLLE_SS_CTRL);
 756         val &= ~PLLE_SS_COEFFICIENTS_MASK;
 757         val |= PLLE_SS_DISABLE;
 758         writel(val, pll->clk_base + PLLE_SS_CTRL);
 759
 760         val = pll_readl_base(pll);
 761         val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
 762         pll_writel_base(val, pll);
 763
 764         clk_pll_wait_for_lock(pll);
 765
 766         return 0;
 767 }
 768
 769 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
 770                                          unsigned long parent_rate)
 771 {
 772         struct tegra_clk_pll *pll = to_clk_pll(hw);
 773         u32 val = pll_readl_base(pll);
 774         u32 divn = 0, divm = 0, divp = 0;
 775         u64 rate = parent_rate;
 776
 777         divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
 778         divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
 779         divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
 780         divm *= divp;
 781
 782         rate *= divn;
 783         do_div(rate, divm);
 784         return rate;
 785 }
 786
 787 const struct clk_ops tegra_clk_pll_ops = {
 788         .is_enabled = clk_pll_is_enabled,
 789         .enable = clk_pll_enable,
 790         .disable = clk_pll_disable,
 791         .recalc_rate = clk_pll_recalc_rate,
 792         .round_rate = clk_pll_round_rate,
 793         .set_rate = clk_pll_set_rate,
 794 };
 795
 796 const struct clk_ops tegra_clk_plle_ops = {
 797         .recalc_rate = clk_plle_recalc_rate,
 798         .is_enabled = clk_pll_is_enabled,
 799         .disable = clk_pll_disable,
 800         .enable = clk_plle_enable,
 801 };
 802
 803 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
 804
 805 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
 806                            unsigned long parent_rate)
 807 {
 808         if (parent_rate > pll_params->cf_max)
 809                 return 2;
 810         else
 811                 return 1;
 812 }
 813
 814 static unsigned long _clip_vco_min(unsigned long vco_min,
 815                                    unsigned long parent_rate)
 816 {
 817         return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
 818 }
 819
 820 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
 821                                void __iomem *clk_base,
 822                                unsigned long parent_rate)
 823 {
 824         u32 val;
 825         u32 step_a, step_b;
 826
 827         switch (parent_rate) {
 828         case 12000000:
 829         case 13000000:
 830         case 26000000:
 831                 step_a = 0x2B;
 832                 step_b = 0x0B;
 833                 break;
 834         case 16800000:
 835                 step_a = 0x1A;
 836                 step_b = 0x09;
 837                 break;
 838         case 19200000:
 839                 step_a = 0x12;
 840                 step_b = 0x08;
 841                 break;
 842         default:
 843                 pr_err("%s: Unexpected reference rate %lu\n",
 844                         __func__, parent_rate);
 845                 WARN_ON(1);
 846                 return -EINVAL;
 847         }
 848
 849         val = step_a << pll_params->stepa_shift;
 850         val |= step_b << pll_params->stepb_shift;
 851         writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
 852
 853         return 0;
 854 }
 855
 856 static int clk_pll_iddq_enable(struct clk_hw *hw)
 857 {
 858         struct tegra_clk_pll *pll = to_clk_pll(hw);
 859         unsigned long flags = 0;
 860
 861         u32 val;
 862         int ret;
 863
 864         if (pll->lock)
 865                 spin_lock_irqsave(pll->lock, flags);
 866
 867         val = pll_readl(pll->params->iddq_reg, pll);
 868         val &= ~BIT(pll->params->iddq_bit_idx);
 869         pll_writel(val, pll->params->iddq_reg, pll);
 870         udelay(2);
 871
 872         _clk_pll_enable(hw);
 873
 874         ret = clk_pll_wait_for_lock(pll);
 875
 876         if (pll->lock)
 877                 spin_unlock_irqrestore(pll->lock, flags);
 878
 879         return 0;
 880 }
 881
 882 static void clk_pll_iddq_disable(struct clk_hw *hw)
 883 {
 884         struct tegra_clk_pll *pll = to_clk_pll(hw);
 885         unsigned long flags = 0;
 886         u32 val;
 887
 888         if (pll->lock)
 889                 spin_lock_irqsave(pll->lock, flags);
 890
 891         _clk_pll_disable(hw);
 892
 893         val = pll_readl(pll->params->iddq_reg, pll);
 894         val |= BIT(pll->params->iddq_bit_idx);
 895         pll_writel(val, pll->params->iddq_reg, pll);
 896         udelay(2);
 897
 898         if (pll->lock)
 899                 spin_unlock_irqrestore(pll->lock, flags);
 900 }
 901
 902 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
 903                                 struct tegra_clk_pll_freq_table *cfg,
 904                                 unsigned long rate, unsigned long parent_rate)
 905 {
 906         struct tegra_clk_pll *pll = to_clk_pll(hw);
 907         unsigned int p;
 908         int p_div;
 909
 910         if (!rate)
 911                 return -EINVAL;
 912
 913         p = DIV_ROUND_UP(pll->params->vco_min, rate);
 914         cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
 915         cfg->output_rate = rate * p;
 916         cfg->n = cfg->output_rate * cfg->m / parent_rate;
 917
 918         p_div = _p_div_to_hw(hw, p);
 919         if (p_div < 0)
 920                 return p_div;
 921         else
 922                 cfg->p = p_div;
 923
 924         if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
 925                 return -EINVAL;
 926
 927         return 0;
 928 }
 929
 930 static int _pll_ramp_calc_pll(struct clk_hw *hw,
 931                               struct tegra_clk_pll_freq_table *cfg,
 932                               unsigned long rate, unsigned long parent_rate)
 933 {
 934         struct tegra_clk_pll *pll = to_clk_pll(hw);
 935         int err = 0, p_div;
 936
 937         err = _get_table_rate(hw, cfg, rate, parent_rate);
 938         if (err < 0)
 939                 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
 940         else {
 941                 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
 942                         WARN_ON(1);
 943                         err = -EINVAL;
 944                         goto out;
 945                 }
 946                 p_div = _p_div_to_hw(hw, cfg->p);
 947                 if (p_div < 0)
 948                         return p_div;
 949                 else
 950                         cfg->p = p_div;
 951         }
 952
 953         if (cfg->p >  pll->params->max_p)
 954                 err = -EINVAL;
 955
 956 out:
 957         return err;
 958 }
 959
 960 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
 961                                 unsigned long parent_rate)
 962 {
 963         struct tegra_clk_pll *pll = to_clk_pll(hw);
 964         struct tegra_clk_pll_freq_table cfg, old_cfg;
 965         unsigned long flags = 0;
 966         int ret = 0;
 967
 968         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
 969         if (ret < 0)
 970                 return ret;
 971
 972         if (pll->lock)
 973                 spin_lock_irqsave(pll->lock, flags);
 974
 975         _get_pll_mnp(pll, &old_cfg);
 976
 977         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
 978                 ret = _program_pll(hw, &cfg, rate);
 979
 980         if (pll->lock)
 981                 spin_unlock_irqrestore(pll->lock, flags);
 982
 983         return ret;
 984 }
 985
 986 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
 987                                 unsigned long *prate)
 988 {
 989         struct tegra_clk_pll_freq_table cfg;
 990         int ret = 0, p_div;
 991         u64 output_rate = *prate;
 992
 993         ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
 994         if (ret < 0)
 995                 return ret;
 996
 997         p_div = _hw_to_p_div(hw, cfg.p);
 998         if (p_div < 0)
 999                 return p_div;
1000
1001         output_rate *= cfg.n;
1002         do_div(output_rate, cfg.m * p_div);
1003
1004         return output_rate;
1005 }
1006
1007 static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate,
1008                                 unsigned long parent_rate)
1009 {
1010         struct tegra_clk_pll_freq_table cfg;
1011         struct tegra_clk_pll *pll = to_clk_pll(hw);
1012         unsigned long flags = 0;
1013         int state, ret = 0;
1014
1015         if (pll->lock)
1016                 spin_lock_irqsave(pll->lock, flags);
1017
1018         state = clk_pll_is_enabled(hw);
1019         if (state) {
1020                 if (rate != clk_get_rate(hw->clk)) {
1021                         pr_err("%s: Cannot change active PLLM\n", __func__);
1022                         ret = -EINVAL;
1023                         goto out;
1024                 }
1025                 goto out;
1026         }
1027
1028         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1029         if (ret < 0)
1030                 goto out;
1031
1032         _update_pll_mnp(pll, &cfg);
1033
1034 out:
1035         if (pll->lock)
1036                 spin_unlock_irqrestore(pll->lock, flags);
1037
1038         return ret;
1039 }
1040
1041 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1042 {
1043         u32 val;
1044
1045         val = pll_readl_misc(pll);
1046         val |= PLLCX_MISC_STROBE;
1047         pll_writel_misc(val, pll);
1048         udelay(2);
1049
1050         val &= ~PLLCX_MISC_STROBE;
1051         pll_writel_misc(val, pll);
1052 }
1053
1054 static int clk_pllc_enable(struct clk_hw *hw)
1055 {
1056         struct tegra_clk_pll *pll = to_clk_pll(hw);
1057         u32 val;
1058         int ret = 0;
1059         unsigned long flags = 0;
1060
1061         if (pll->lock)
1062                 spin_lock_irqsave(pll->lock, flags);
1063
1064         _clk_pll_enable(hw);
1065         udelay(2);
1066
1067         val = pll_readl_misc(pll);
1068         val &= ~PLLCX_MISC_RESET;
1069         pll_writel_misc(val, pll);
1070         udelay(2);
1071
1072         _pllcx_strobe(pll);
1073
1074         ret = clk_pll_wait_for_lock(pll);
1075
1076         if (pll->lock)
1077                 spin_unlock_irqrestore(pll->lock, flags);
1078
1079         return ret;
1080 }
1081
1082 static void _clk_pllc_disable(struct clk_hw *hw)
1083 {
1084         struct tegra_clk_pll *pll = to_clk_pll(hw);
1085         u32 val;
1086
1087         _clk_pll_disable(hw);
1088
1089         val = pll_readl_misc(pll);
1090         val |= PLLCX_MISC_RESET;
1091         pll_writel_misc(val, pll);
1092         udelay(2);
1093 }
1094
1095 static void clk_pllc_disable(struct clk_hw *hw)
1096 {
1097         struct tegra_clk_pll *pll = to_clk_pll(hw);
1098         unsigned long flags = 0;
1099
1100         if (pll->lock)
1101                 spin_lock_irqsave(pll->lock, flags);
1102
1103         _clk_pllc_disable(hw);
1104
1105         if (pll->lock)
1106                 spin_unlock_irqrestore(pll->lock, flags);
1107 }
1108
1109 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1110                                         unsigned long input_rate, u32 n)
1111 {
1112         u32 val, n_threshold;
1113
1114         switch (input_rate) {
1115         case 12000000:
1116                 n_threshold = 70;
1117                 break;
1118         case 13000000:
1119         case 26000000:
1120                 n_threshold = 71;
1121                 break;
1122         case 16800000:
1123                 n_threshold = 55;
1124                 break;
1125         case 19200000:
1126                 n_threshold = 48;
1127                 break;
1128         default:
1129                 pr_err("%s: Unexpected reference rate %lu\n",
1130                         __func__, input_rate);
1131                 return -EINVAL;
1132         }
1133
1134         val = pll_readl_misc(pll);
1135         val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1136         val |= n <= n_threshold ?
1137                 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1138         pll_writel_misc(val, pll);
1139
1140         return 0;
1141 }
1142
1143 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1144                                 unsigned long parent_rate)
1145 {
1146         struct tegra_clk_pll_freq_table cfg, old_cfg;
1147         struct tegra_clk_pll *pll = to_clk_pll(hw);
1148         unsigned long flags = 0;
1149         int state, ret = 0;
1150
1151         if (pll->lock)
1152                 spin_lock_irqsave(pll->lock, flags);
1153
1154         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1155         if (ret < 0)
1156                 goto out;
1157
1158         _get_pll_mnp(pll, &old_cfg);
1159
1160         if (cfg.m != old_cfg.m) {
1161                 WARN_ON(1);
1162                 goto out;
1163         }
1164
1165         if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1166                 goto out;
1167
1168         state = clk_pll_is_enabled(hw);
1169         if (state)
1170                 _clk_pllc_disable(hw);
1171
1172         ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1173         if (ret < 0)
1174                 goto out;
1175
1176         _update_pll_mnp(pll, &cfg);
1177
1178         if (state)
1179                 ret = clk_pllc_enable(hw);
1180
1181 out:
1182         if (pll->lock)
1183                 spin_unlock_irqrestore(pll->lock, flags);
1184
1185         return ret;
1186 }
1187
1188 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1189                              struct tegra_clk_pll_freq_table *cfg,
1190                              unsigned long rate, unsigned long parent_rate)
1191 {
1192         u16 m, n;
1193         u64 output_rate = parent_rate;
1194
1195         m = _pll_fixed_mdiv(pll->params, parent_rate);
1196         n = rate * m / parent_rate;
1197
1198         output_rate *= n;
1199         do_div(output_rate, m);
1200
1201         if (cfg) {
1202                 cfg->m = m;
1203                 cfg->n = n;
1204         }
1205
1206         return output_rate;
1207 }
1208 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1209                                 unsigned long parent_rate)
1210 {
1211         struct tegra_clk_pll_freq_table cfg, old_cfg;
1212         struct tegra_clk_pll *pll = to_clk_pll(hw);
1213         unsigned long flags = 0;
1214         int state, ret = 0;
1215
1216         if (pll->lock)
1217                 spin_lock_irqsave(pll->lock, flags);
1218
1219         _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1220         _get_pll_mnp(pll, &old_cfg);
1221         cfg.p = old_cfg.p;
1222
1223         if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1224                 state = clk_pll_is_enabled(hw);
1225                 if (state)
1226                         _clk_pll_disable(hw);
1227
1228                 _update_pll_mnp(pll, &cfg);
1229
1230                 if (state) {
1231                         _clk_pll_enable(hw);
1232                         ret = clk_pll_wait_for_lock(pll);
1233                 }
1234         }
1235
1236         if (pll->lock)
1237                 spin_unlock_irqrestore(pll->lock, flags);
1238
1239         return ret;
1240 }
1241
1242 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1243                                          unsigned long parent_rate)
1244 {
1245         struct tegra_clk_pll_freq_table cfg;
1246         struct tegra_clk_pll *pll = to_clk_pll(hw);
1247         u64 rate = parent_rate;
1248
1249         _get_pll_mnp(pll, &cfg);
1250
1251         rate *= cfg.n;
1252         do_div(rate, cfg.m);
1253
1254         return rate;
1255 }
1256
1257 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1258                                  unsigned long *prate)
1259 {
1260         struct tegra_clk_pll *pll = to_clk_pll(hw);
1261
1262         return _pllre_calc_rate(pll, NULL, rate, *prate);
1263 }
1264
1265 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1266 {
1267         struct tegra_clk_pll *pll = to_clk_pll(hw);
1268         struct tegra_clk_pll_freq_table sel;
1269         u32 val;
1270         int ret;
1271         unsigned long flags = 0;
1272         unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
1273
1274         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1275                 return -EINVAL;
1276
1277         if (pll->lock)
1278                 spin_lock_irqsave(pll->lock, flags);
1279
1280         val = pll_readl_base(pll);
1281         val &= ~BIT(29); /* Disable lock override */
1282         pll_writel_base(val, pll);
1283
1284         val = pll_readl(pll->params->aux_reg, pll);
1285         val |= PLLE_AUX_ENABLE_SWCTL;
1286         val &= ~PLLE_AUX_SEQ_ENABLE;
1287         pll_writel(val, pll->params->aux_reg, pll);
1288         udelay(1);
1289
1290         val = pll_readl_misc(pll);
1291         val |= PLLE_MISC_LOCK_ENABLE;
1292         val |= PLLE_MISC_IDDQ_SW_CTRL;
1293         val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1294         val |= PLLE_MISC_PLLE_PTS;
1295         val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
1296         pll_writel_misc(val, pll);
1297         udelay(5);
1298
1299         val = pll_readl(PLLE_SS_CTRL, pll);
1300         val |= PLLE_SS_DISABLE;
1301         pll_writel(val, PLLE_SS_CTRL, pll);
1302
1303         val = pll_readl_base(pll);
1304         val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1305                  divm_mask_shifted(pll));
1306         val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1307         val |= sel.m << divm_shift(pll);
1308         val |= sel.n << divn_shift(pll);
1309         val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1310         pll_writel_base(val, pll);
1311         udelay(1);
1312
1313         _clk_pll_enable(hw);
1314         ret = clk_pll_wait_for_lock(pll);
1315
1316         if (ret < 0)
1317                 goto out;
1318
1319         val = pll_readl(PLLE_SS_CTRL, pll);
1320         val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1321         val &= ~PLLE_SS_COEFFICIENTS_MASK;
1322         val |= PLLE_SS_COEFFICIENTS_VAL;
1323         pll_writel(val, PLLE_SS_CTRL, pll);
1324         val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1325         pll_writel(val, PLLE_SS_CTRL, pll);
1326         udelay(1);
1327         val &= ~PLLE_SS_CNTL_INTERP_RESET;
1328         pll_writel(val, PLLE_SS_CTRL, pll);
1329         udelay(1);
1330
1331         /* TODO: enable hw control of xusb brick pll */
1332
1333 out:
1334         if (pll->lock)
1335                 spin_unlock_irqrestore(pll->lock, flags);
1336
1337         return ret;
1338 }
1339
1340 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1341 {
1342         struct tegra_clk_pll *pll = to_clk_pll(hw);
1343         unsigned long flags = 0;
1344         u32 val;
1345
1346         if (pll->lock)
1347                 spin_lock_irqsave(pll->lock, flags);
1348
1349         _clk_pll_disable(hw);
1350
1351         val = pll_readl_misc(pll);
1352         val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1353         pll_writel_misc(val, pll);
1354         udelay(1);
1355
1356         if (pll->lock)
1357                 spin_unlock_irqrestore(pll->lock, flags);
1358 }
1359 #endif
1360
1361 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1362                 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1363                 spinlock_t *lock)
1364 {
1365         struct tegra_clk_pll *pll;
1366
1367         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1368         if (!pll)
1369                 return ERR_PTR(-ENOMEM);
1370
1371         pll->clk_base = clk_base;
1372         pll->pmc = pmc;
1373
1374         pll->params = pll_params;
1375         pll->lock = lock;
1376
1377         if (!pll_params->div_nmp)
1378                 pll_params->div_nmp = &default_nmp;
1379
1380         return pll;
1381 }
1382
1383 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1384                 const char *name, const char *parent_name, unsigned long flags,
1385                 const struct clk_ops *ops)
1386 {
1387         struct clk_init_data init;
1388
1389         init.name = name;
1390         init.ops = ops;
1391         init.flags = flags;
1392         init.parent_names = (parent_name ? &parent_name : NULL);
1393         init.num_parents = (parent_name ? 1 : 0);
1394
1395         /* Data in .init is copied by clk_register(), so stack variable OK */
1396         pll->hw.init = &init;
1397
1398         return clk_register(NULL, &pll->hw);
1399 }
1400
1401 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1402                 void __iomem *clk_base, void __iomem *pmc,
1403                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1404                 spinlock_t *lock)
1405 {
1406         struct tegra_clk_pll *pll;
1407         struct clk *clk;
1408
1409         pll_params->flags |= TEGRA_PLL_BYPASS;
1410         pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1411         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1412         if (IS_ERR(pll))
1413                 return ERR_CAST(pll);
1414
1415         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1416                                       &tegra_clk_pll_ops);
1417         if (IS_ERR(clk))
1418                 kfree(pll);
1419
1420         return clk;
1421 }
1422
1423 static struct div_nmp pll_e_nmp = {
1424         .divn_shift = PLLE_BASE_DIVN_SHIFT,
1425         .divn_width = PLLE_BASE_DIVN_WIDTH,
1426         .divm_shift = PLLE_BASE_DIVM_SHIFT,
1427         .divm_width = PLLE_BASE_DIVM_WIDTH,
1428         .divp_shift = PLLE_BASE_DIVP_SHIFT,
1429         .divp_width = PLLE_BASE_DIVP_WIDTH,
1430 };
1431
1432 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1433                 void __iomem *clk_base, void __iomem *pmc,
1434                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1435                 spinlock_t *lock)
1436 {
1437         struct tegra_clk_pll *pll;
1438         struct clk *clk;
1439
1440         pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
1441         pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1442
1443         if (!pll_params->div_nmp)
1444                 pll_params->div_nmp = &pll_e_nmp;
1445
1446         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1447         if (IS_ERR(pll))
1448                 return ERR_CAST(pll);
1449
1450         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1451                                       &tegra_clk_plle_ops);
1452         if (IS_ERR(clk))
1453                 kfree(pll);
1454
1455         return clk;
1456 }
1457
1458 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
1459 static const struct clk_ops tegra_clk_pllxc_ops = {
1460         .is_enabled = clk_pll_is_enabled,
1461         .enable = clk_pll_iddq_enable,
1462         .disable = clk_pll_iddq_disable,
1463         .recalc_rate = clk_pll_recalc_rate,
1464         .round_rate = clk_pll_ramp_round_rate,
1465         .set_rate = clk_pllxc_set_rate,
1466 };
1467
1468 static const struct clk_ops tegra_clk_pllm_ops = {
1469         .is_enabled = clk_pll_is_enabled,
1470         .enable = clk_pll_iddq_enable,
1471         .disable = clk_pll_iddq_disable,
1472         .recalc_rate = clk_pll_recalc_rate,
1473         .round_rate = clk_pll_ramp_round_rate,
1474         .set_rate = clk_pllm_set_rate,
1475 };
1476
1477 static const struct clk_ops tegra_clk_pllc_ops = {
1478         .is_enabled = clk_pll_is_enabled,
1479         .enable = clk_pllc_enable,
1480         .disable = clk_pllc_disable,
1481         .recalc_rate = clk_pll_recalc_rate,
1482         .round_rate = clk_pll_ramp_round_rate,
1483         .set_rate = clk_pllc_set_rate,
1484 };
1485
1486 static const struct clk_ops tegra_clk_pllre_ops = {
1487         .is_enabled = clk_pll_is_enabled,
1488         .enable = clk_pll_iddq_enable,
1489         .disable = clk_pll_iddq_disable,
1490         .recalc_rate = clk_pllre_recalc_rate,
1491         .round_rate = clk_pllre_round_rate,
1492         .set_rate = clk_pllre_set_rate,
1493 };
1494
1495 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1496         .is_enabled =  clk_pll_is_enabled,
1497         .enable = clk_plle_tegra114_enable,
1498         .disable = clk_plle_tegra114_disable,
1499         .recalc_rate = clk_pll_recalc_rate,
1500 };
1501
1502
1503 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1504                           void __iomem *clk_base, void __iomem *pmc,
1505                           unsigned long flags,
1506                           struct tegra_clk_pll_params *pll_params,
1507                           spinlock_t *lock)
1508 {
1509         struct tegra_clk_pll *pll;
1510         struct clk *clk, *parent;
1511         unsigned long parent_rate;
1512         int err;
1513         u32 val, val_iddq;
1514
1515         parent = __clk_lookup(parent_name);
1516         if (!parent) {
1517                 WARN(1, "parent clk %s of %s must be registered first\n",
1518                         name, parent_name);
1519                 return ERR_PTR(-EINVAL);
1520         }
1521
1522         if (!pll_params->pdiv_tohw)
1523                 return ERR_PTR(-EINVAL);
1524
1525         parent_rate = __clk_get_rate(parent);
1526
1527         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1528
1529         err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
1530         if (err)
1531                 return ERR_PTR(err);
1532
1533         val = readl_relaxed(clk_base + pll_params->base_reg);
1534         val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1535
1536         if (val & PLL_BASE_ENABLE)
1537                 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
1538         else {
1539                 val_iddq |= BIT(pll_params->iddq_bit_idx);
1540                 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
1541         }
1542
1543         pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1544         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1545         if (IS_ERR(pll))
1546                 return ERR_CAST(pll);
1547
1548         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1549                                       &tegra_clk_pllxc_ops);
1550         if (IS_ERR(clk))
1551                 kfree(pll);
1552
1553         return clk;
1554 }
1555
1556 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1557                           void __iomem *clk_base, void __iomem *pmc,
1558                           unsigned long flags,
1559                           struct tegra_clk_pll_params *pll_params,
1560                           spinlock_t *lock, unsigned long parent_rate)
1561 {
1562         u32 val;
1563         struct tegra_clk_pll *pll;
1564         struct clk *clk;
1565
1566         pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC;
1567
1568         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1569
1570         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1571         if (IS_ERR(pll))
1572                 return ERR_CAST(pll);
1573
1574         /* program minimum rate by default */
1575
1576         val = pll_readl_base(pll);
1577         if (val & PLL_BASE_ENABLE)
1578                 WARN_ON(val & pll_params->iddq_bit_idx);
1579         else {
1580                 int m;
1581
1582                 m = _pll_fixed_mdiv(pll_params, parent_rate);
1583                 val = m << divm_shift(pll);
1584                 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
1585                 pll_writel_base(val, pll);
1586         }
1587
1588         /* disable lock override */
1589
1590         val = pll_readl_misc(pll);
1591         val &= ~BIT(29);
1592         pll_writel_misc(val, pll);
1593
1594         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1595                                       &tegra_clk_pllre_ops);
1596         if (IS_ERR(clk))
1597                 kfree(pll);
1598
1599         return clk;
1600 }
1601
1602 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1603                           void __iomem *clk_base, void __iomem *pmc,
1604                           unsigned long flags,
1605                           struct tegra_clk_pll_params *pll_params,
1606                           spinlock_t *lock)
1607 {
1608         struct tegra_clk_pll *pll;
1609         struct clk *clk, *parent;
1610         unsigned long parent_rate;
1611
1612         if (!pll_params->pdiv_tohw)
1613                 return ERR_PTR(-EINVAL);
1614
1615         parent = __clk_lookup(parent_name);
1616         if (!parent) {
1617                 WARN(1, "parent clk %s of %s must be registered first\n",
1618                         name, parent_name);
1619                 return ERR_PTR(-EINVAL);
1620         }
1621
1622         parent_rate = __clk_get_rate(parent);
1623
1624         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1625
1626         pll_params->flags |= TEGRA_PLL_BYPASS;
1627         pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1628         pll_params->flags |= TEGRA_PLLM;
1629         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1630         if (IS_ERR(pll))
1631                 return ERR_CAST(pll);
1632
1633         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1634                                       &tegra_clk_pllm_ops);
1635         if (IS_ERR(clk))
1636                 kfree(pll);
1637
1638         return clk;
1639 }
1640
1641 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1642                           void __iomem *clk_base, void __iomem *pmc,
1643                           unsigned long flags,
1644                           struct tegra_clk_pll_params *pll_params,
1645                           spinlock_t *lock)
1646 {
1647         struct clk *parent, *clk;
1648         struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
1649         struct tegra_clk_pll *pll;
1650         struct tegra_clk_pll_freq_table cfg;
1651         unsigned long parent_rate;
1652
1653         if (!p_tohw)
1654                 return ERR_PTR(-EINVAL);
1655
1656         parent = __clk_lookup(parent_name);
1657         if (!parent) {
1658                 WARN(1, "parent clk %s of %s must be registered first\n",
1659                         name, parent_name);
1660                 return ERR_PTR(-EINVAL);
1661         }
1662
1663         parent_rate = __clk_get_rate(parent);
1664
1665         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1666
1667         pll_params->flags |= TEGRA_PLL_BYPASS;
1668         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1669         if (IS_ERR(pll))
1670                 return ERR_CAST(pll);
1671
1672         /*
1673          * Most of PLLC register fields are shadowed, and can not be read
1674          * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
1675          * Initialize PLL to default state: disabled, reset; shadow registers
1676          * loaded with default parameters; dividers are preset for half of
1677          * minimum VCO rate (the latter assured that shadowed divider settings
1678          * are within supported range).
1679          */
1680
1681         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1682         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1683
1684         while (p_tohw->pdiv) {
1685                 if (p_tohw->pdiv == 2) {
1686                         cfg.p = p_tohw->hw_val;
1687                         break;
1688                 }
1689                 p_tohw++;
1690         }
1691
1692         if (!p_tohw->pdiv) {
1693                 WARN_ON(1);
1694                 return ERR_PTR(-EINVAL);
1695         }
1696
1697         pll_writel_base(0, pll);
1698         _update_pll_mnp(pll, &cfg);
1699
1700         pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
1701         pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
1702         pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
1703         pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
1704
1705         _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1706
1707         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1708                                       &tegra_clk_pllc_ops);
1709         if (IS_ERR(clk))
1710                 kfree(pll);
1711
1712         return clk;
1713 }
1714
1715 struct clk *tegra_clk_register_plle_tegra114(const char *name,
1716                                 const char *parent_name,
1717                                 void __iomem *clk_base, unsigned long flags,
1718                                 struct tegra_clk_pll_params *pll_params,
1719                                 spinlock_t *lock)
1720 {
1721         struct tegra_clk_pll *pll;
1722         struct clk *clk;
1723         u32 val, val_aux;
1724
1725         pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1726         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1727         if (IS_ERR(pll))
1728                 return ERR_CAST(pll);
1729
1730         /* ensure parent is set to pll_re_vco */
1731
1732         val = pll_readl_base(pll);
1733         val_aux = pll_readl(pll_params->aux_reg, pll);
1734
1735         if (val & PLL_BASE_ENABLE) {
1736                 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
1737                         (val_aux & PLLE_AUX_PLLP_SEL))
1738                         WARN(1, "pll_e enabled with unsupported parent %s\n",
1739                           (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
1740                                         "pll_re_vco");
1741         } else {
1742                 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
1743                 pll_writel(val_aux, pll_params->aux_reg, pll);
1744         }
1745
1746         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1747                                       &tegra_clk_plle_tegra114_ops);
1748         if (IS_ERR(clk))
1749                 kfree(pll);
1750
1751         return clk;
1752 }
1753 #endif
1754
1755 #ifdef CONFIG_ARCH_TEGRA_124_SOC
1756 static const struct clk_ops tegra_clk_pllss_ops = {
1757         .is_enabled = clk_pll_is_enabled,
1758         .enable = clk_pll_iddq_enable,
1759         .disable = clk_pll_iddq_disable,
1760         .recalc_rate = clk_pll_recalc_rate,
1761         .round_rate = clk_pll_ramp_round_rate,
1762         .set_rate = clk_pllxc_set_rate,
1763 };
1764
1765 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
1766                                 void __iomem *clk_base, unsigned long flags,
1767                                 struct tegra_clk_pll_params *pll_params,
1768                                 spinlock_t *lock)
1769 {
1770         struct tegra_clk_pll *pll;
1771         struct clk *clk, *parent;
1772         struct tegra_clk_pll_freq_table cfg;
1773         unsigned long parent_rate;
1774         u32 val;
1775         int i;
1776
1777         if (!pll_params->div_nmp)
1778                 return ERR_PTR(-EINVAL);
1779
1780         parent = __clk_lookup(parent_name);
1781         if (!parent) {
1782                 WARN(1, "parent clk %s of %s must be registered first\n",
1783                         name, parent_name);
1784                 return ERR_PTR(-EINVAL);
1785         }
1786
1787         pll_params->flags = TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_USE_LOCK;
1788         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1789         if (IS_ERR(pll))
1790                 return ERR_CAST(pll);
1791
1792         val = pll_readl_base(pll);
1793         val &= ~PLLSS_REF_SRC_SEL_MASK;
1794         pll_writel_base(val, pll);
1795
1796         parent_rate = __clk_get_rate(parent);
1797
1798         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1799
1800         /* initialize PLL to minimum rate */
1801
1802         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1803         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1804
1805         for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
1806                 ;
1807         if (!i) {
1808                 kfree(pll);
1809                 return ERR_PTR(-EINVAL);
1810         }
1811
1812         cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
1813
1814         _update_pll_mnp(pll, &cfg);
1815
1816         pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
1817         pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
1818         pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
1819         pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
1820
1821         val = pll_readl_base(pll);
1822         if (val & PLL_BASE_ENABLE) {
1823                 if (val & BIT(pll_params->iddq_bit_idx)) {
1824                         WARN(1, "%s is on but IDDQ set\n", name);
1825                         kfree(pll);
1826                         return ERR_PTR(-EINVAL);
1827                 }
1828         } else
1829                 val |= BIT(pll_params->iddq_bit_idx);
1830
1831         val &= ~PLLSS_LOCK_OVERRIDE;
1832         pll_writel_base(val, pll);
1833
1834         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1835                                         &tegra_clk_pllss_ops);
1836
1837         if (IS_ERR(clk))
1838                 kfree(pll);
1839
1840         return clk;
1841 }
1842 #endif