2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/slab.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/clk-provider.h>
22 #include <linux/clk.h>
26 #define PLL_BASE_BYPASS BIT(31)
27 #define PLL_BASE_ENABLE BIT(30)
28 #define PLL_BASE_REF_ENABLE BIT(29)
29 #define PLL_BASE_OVERRIDE BIT(28)
31 #define PLL_BASE_DIVP_SHIFT 20
32 #define PLL_BASE_DIVP_WIDTH 3
33 #define PLL_BASE_DIVN_SHIFT 8
34 #define PLL_BASE_DIVN_WIDTH 10
35 #define PLL_BASE_DIVM_SHIFT 0
36 #define PLL_BASE_DIVM_WIDTH 5
37 #define PLLU_POST_DIVP_MASK 0x1
39 #define PLL_MISC_DCCON_SHIFT 20
40 #define PLL_MISC_CPCON_SHIFT 8
41 #define PLL_MISC_CPCON_WIDTH 4
42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
43 #define PLL_MISC_LFCON_SHIFT 4
44 #define PLL_MISC_LFCON_WIDTH 4
45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
46 #define PLL_MISC_VCOCON_SHIFT 0
47 #define PLL_MISC_VCOCON_WIDTH 4
48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
50 #define OUT_OF_TABLE_CPCON 8
52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
56 #define PLL_POST_LOCK_DELAY 50
58 #define PLLDU_LFCON_SET_DIVN 600
60 #define PLLE_BASE_DIVCML_SHIFT 24
61 #define PLLE_BASE_DIVCML_WIDTH 4
62 #define PLLE_BASE_DIVP_SHIFT 16
63 #define PLLE_BASE_DIVP_WIDTH 7
64 #define PLLE_BASE_DIVN_SHIFT 8
65 #define PLLE_BASE_DIVN_WIDTH 8
66 #define PLLE_BASE_DIVM_SHIFT 0
67 #define PLLE_BASE_DIVM_WIDTH 8
69 #define PLLE_MISC_SETUP_BASE_SHIFT 16
70 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
71 #define PLLE_MISC_LOCK_ENABLE BIT(9)
72 #define PLLE_MISC_READY BIT(15)
73 #define PLLE_MISC_SETUP_EX_SHIFT 2
74 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
75 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
76 PLLE_MISC_SETUP_EX_MASK)
77 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
79 #define PLLE_SS_CTRL 0x68
80 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
81 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
82 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
83 #define PLLE_SS_CNTL_CENTER BIT(14)
84 #define PLLE_SS_CNTL_INVERT BIT(15)
85 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
87 #define PLLE_SS_MAX_MASK 0x1ff
88 #define PLLE_SS_MAX_VAL 0x25
89 #define PLLE_SS_INC_MASK (0xff << 16)
90 #define PLLE_SS_INC_VAL (0x1 << 16)
91 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
92 #define PLLE_SS_INCINTRV_VAL (0x20 << 24)
93 #define PLLE_SS_COEFFICIENTS_MASK \
94 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
95 #define PLLE_SS_COEFFICIENTS_VAL \
96 (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)
98 #define PLLE_AUX_PLLP_SEL BIT(2)
99 #define PLLE_AUX_ENABLE_SWCTL BIT(4)
100 #define PLLE_AUX_SEQ_ENABLE BIT(24)
101 #define PLLE_AUX_PLLRE_SEL BIT(28)
103 #define PLLE_MISC_PLLE_PTS BIT(8)
104 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
105 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
106 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
107 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
108 #define PLLE_MISC_VREG_CTRL_SHIFT 2
109 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
111 #define PLLCX_MISC_STROBE BIT(31)
112 #define PLLCX_MISC_RESET BIT(30)
113 #define PLLCX_MISC_SDM_DIV_SHIFT 28
114 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
115 #define PLLCX_MISC_FILT_DIV_SHIFT 26
116 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
117 #define PLLCX_MISC_ALPHA_SHIFT 18
118 #define PLLCX_MISC_DIV_LOW_RANGE \
119 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
120 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
121 #define PLLCX_MISC_DIV_HIGH_RANGE \
122 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
123 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
124 #define PLLCX_MISC_COEF_LOW_RANGE \
125 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
126 #define PLLCX_MISC_KA_SHIFT 2
127 #define PLLCX_MISC_KB_SHIFT 9
128 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
129 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
130 PLLCX_MISC_DIV_LOW_RANGE | \
132 #define PLLCX_MISC1_DEFAULT 0x000d2308
133 #define PLLCX_MISC2_DEFAULT 0x30211200
134 #define PLLCX_MISC3_DEFAULT 0x200
136 #define PMC_SATA_PWRGT 0x1ac
137 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
138 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
140 #define PLLSS_MISC_KCP 0
141 #define PLLSS_MISC_KVCO 0
142 #define PLLSS_MISC_SETUP 0
143 #define PLLSS_EN_SDM 0
144 #define PLLSS_EN_SSC 0
145 #define PLLSS_EN_DITHER2 0
146 #define PLLSS_EN_DITHER 1
147 #define PLLSS_SDM_RESET 0
148 #define PLLSS_CLAMP 0
149 #define PLLSS_SDM_SSC_MAX 0
150 #define PLLSS_SDM_SSC_MIN 0
151 #define PLLSS_SDM_SSC_STEP 0
152 #define PLLSS_SDM_DIN 0
153 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
154 (PLLSS_MISC_KVCO << 24) | \
156 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
157 (PLLSS_EN_SSC << 30) | \
158 (PLLSS_EN_DITHER2 << 29) | \
159 (PLLSS_EN_DITHER << 28) | \
160 (PLLSS_SDM_RESET) << 27 | \
162 #define PLLSS_CTRL1_DEFAULT \
163 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
164 #define PLLSS_CTRL2_DEFAULT \
165 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
166 #define PLLSS_LOCK_OVERRIDE BIT(24)
167 #define PLLSS_REF_SRC_SEL_SHIFT 25
168 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT)
170 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
171 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
172 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
173 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
175 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
176 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
177 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
178 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
180 #define mask(w) ((1 << (w)) - 1)
181 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
182 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
183 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
184 mask(p->params->div_nmp->divp_width))
186 #define divm_max(p) (divm_mask(p))
187 #define divn_max(p) (divn_mask(p))
188 #define divp_max(p) (1 << (divp_mask(p)))
190 static struct div_nmp default_nmp = {
191 .divn_shift = PLL_BASE_DIVN_SHIFT,
192 .divn_width = PLL_BASE_DIVN_WIDTH,
193 .divm_shift = PLL_BASE_DIVM_SHIFT,
194 .divm_width = PLL_BASE_DIVM_WIDTH,
195 .divp_shift = PLL_BASE_DIVP_SHIFT,
196 .divp_width = PLL_BASE_DIVP_WIDTH,
199 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
203 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
206 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
209 val = pll_readl_misc(pll);
210 val |= BIT(pll->params->lock_enable_bit_idx);
211 pll_writel_misc(val, pll);
214 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
218 void __iomem *lock_addr;
220 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
221 udelay(pll->params->lock_delay);
225 lock_addr = pll->clk_base;
226 if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
227 lock_addr += pll->params->misc_reg;
229 lock_addr += pll->params->base_reg;
231 lock_mask = pll->params->lock_mask;
233 for (i = 0; i < pll->params->lock_delay; i++) {
234 val = readl_relaxed(lock_addr);
235 if ((val & lock_mask) == lock_mask) {
236 udelay(PLL_POST_LOCK_DELAY);
239 udelay(2); /* timeout = 2 * lock time */
242 pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
243 __clk_get_name(pll->hw.clk));
248 static int clk_pll_is_enabled(struct clk_hw *hw)
250 struct tegra_clk_pll *pll = to_clk_pll(hw);
253 if (pll->params->flags & TEGRA_PLLM) {
254 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
255 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
256 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
259 val = pll_readl_base(pll);
261 return val & PLL_BASE_ENABLE ? 1 : 0;
264 static void _clk_pll_enable(struct clk_hw *hw)
266 struct tegra_clk_pll *pll = to_clk_pll(hw);
269 clk_pll_enable_lock(pll);
271 val = pll_readl_base(pll);
272 if (pll->params->flags & TEGRA_PLL_BYPASS)
273 val &= ~PLL_BASE_BYPASS;
274 val |= PLL_BASE_ENABLE;
275 pll_writel_base(val, pll);
277 if (pll->params->flags & TEGRA_PLLM) {
278 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
279 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
280 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
284 static void _clk_pll_disable(struct clk_hw *hw)
286 struct tegra_clk_pll *pll = to_clk_pll(hw);
289 val = pll_readl_base(pll);
290 if (pll->params->flags & TEGRA_PLL_BYPASS)
291 val &= ~PLL_BASE_BYPASS;
292 val &= ~PLL_BASE_ENABLE;
293 pll_writel_base(val, pll);
295 if (pll->params->flags & TEGRA_PLLM) {
296 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
297 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
298 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
302 static int clk_pll_enable(struct clk_hw *hw)
304 struct tegra_clk_pll *pll = to_clk_pll(hw);
305 unsigned long flags = 0;
309 spin_lock_irqsave(pll->lock, flags);
313 ret = clk_pll_wait_for_lock(pll);
316 spin_unlock_irqrestore(pll->lock, flags);
321 static void clk_pll_disable(struct clk_hw *hw)
323 struct tegra_clk_pll *pll = to_clk_pll(hw);
324 unsigned long flags = 0;
327 spin_lock_irqsave(pll->lock, flags);
329 _clk_pll_disable(hw);
332 spin_unlock_irqrestore(pll->lock, flags);
335 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
337 struct tegra_clk_pll *pll = to_clk_pll(hw);
338 struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
341 while (p_tohw->pdiv) {
342 if (p_div <= p_tohw->pdiv)
343 return p_tohw->hw_val;
351 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
353 struct tegra_clk_pll *pll = to_clk_pll(hw);
354 struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
357 while (p_tohw->pdiv) {
358 if (p_div_hw == p_tohw->hw_val)
365 return 1 << p_div_hw;
368 static int _get_table_rate(struct clk_hw *hw,
369 struct tegra_clk_pll_freq_table *cfg,
370 unsigned long rate, unsigned long parent_rate)
372 struct tegra_clk_pll *pll = to_clk_pll(hw);
373 struct tegra_clk_pll_freq_table *sel;
375 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
376 if (sel->input_rate == parent_rate &&
377 sel->output_rate == rate)
380 if (sel->input_rate == 0)
383 cfg->input_rate = sel->input_rate;
384 cfg->output_rate = sel->output_rate;
388 cfg->cpcon = sel->cpcon;
393 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
394 unsigned long rate, unsigned long parent_rate)
396 struct tegra_clk_pll *pll = to_clk_pll(hw);
401 switch (parent_rate) {
404 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
407 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
411 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
416 * PLL_P_OUT1 rate is not listed in PLLA table
418 cfreq = parent_rate/(parent_rate/1000000);
421 pr_err("%s Unexpected reference rate %lu\n",
422 __func__, parent_rate);
426 /* Raise VCO to guarantee 0.5% accuracy */
427 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
428 cfg->output_rate <<= 1)
431 cfg->m = parent_rate / cfreq;
432 cfg->n = cfg->output_rate / cfreq;
433 cfg->cpcon = OUT_OF_TABLE_CPCON;
435 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
436 (1 << p_div) > divp_max(pll)
437 || cfg->output_rate > pll->params->vco_max) {
441 cfg->output_rate >>= p_div;
443 if (pll->params->pdiv_tohw) {
444 ret = _p_div_to_hw(hw, 1 << p_div);
455 static void _update_pll_mnp(struct tegra_clk_pll *pll,
456 struct tegra_clk_pll_freq_table *cfg)
459 struct tegra_clk_pll_params *params = pll->params;
460 struct div_nmp *div_nmp = params->div_nmp;
462 if ((params->flags & TEGRA_PLLM) &&
463 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
464 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
465 val = pll_override_readl(params->pmc_divp_reg, pll);
466 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
467 val |= cfg->p << div_nmp->override_divp_shift;
468 pll_override_writel(val, params->pmc_divp_reg, pll);
470 val = pll_override_readl(params->pmc_divnm_reg, pll);
471 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) |
472 ~(divn_mask(pll) << div_nmp->override_divn_shift);
473 val |= (cfg->m << div_nmp->override_divm_shift) |
474 (cfg->n << div_nmp->override_divn_shift);
475 pll_override_writel(val, params->pmc_divnm_reg, pll);
477 val = pll_readl_base(pll);
479 val &= ~((divm_mask(pll) << div_nmp->divm_shift) |
480 (divn_mask(pll) << div_nmp->divn_shift) |
481 (divp_mask(pll) << div_nmp->divp_shift));
483 val |= ((cfg->m << div_nmp->divm_shift) |
484 (cfg->n << div_nmp->divn_shift) |
485 (cfg->p << div_nmp->divp_shift));
487 pll_writel_base(val, pll);
491 static void _get_pll_mnp(struct tegra_clk_pll *pll,
492 struct tegra_clk_pll_freq_table *cfg)
495 struct tegra_clk_pll_params *params = pll->params;
496 struct div_nmp *div_nmp = params->div_nmp;
498 if ((params->flags & TEGRA_PLLM) &&
499 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
500 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
501 val = pll_override_readl(params->pmc_divp_reg, pll);
502 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
504 val = pll_override_readl(params->pmc_divnm_reg, pll);
505 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
506 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
508 val = pll_readl_base(pll);
510 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
511 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
512 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
516 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
517 struct tegra_clk_pll_freq_table *cfg,
522 val = pll_readl_misc(pll);
524 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
525 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
527 if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
528 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
529 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
530 val |= 1 << PLL_MISC_LFCON_SHIFT;
531 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
532 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
533 if (rate >= (pll->params->vco_max >> 1))
534 val |= 1 << PLL_MISC_DCCON_SHIFT;
537 pll_writel_misc(val, pll);
540 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
543 struct tegra_clk_pll *pll = to_clk_pll(hw);
546 state = clk_pll_is_enabled(hw);
549 _clk_pll_disable(hw);
551 _update_pll_mnp(pll, cfg);
553 if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
554 _update_pll_cpcon(pll, cfg, rate);
558 ret = clk_pll_wait_for_lock(pll);
564 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
565 unsigned long parent_rate)
567 struct tegra_clk_pll *pll = to_clk_pll(hw);
568 struct tegra_clk_pll_freq_table cfg, old_cfg;
569 unsigned long flags = 0;
572 if (pll->params->flags & TEGRA_PLL_FIXED) {
573 if (rate != pll->params->fixed_rate) {
574 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
575 __func__, __clk_get_name(hw->clk),
576 pll->params->fixed_rate, rate);
582 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
583 _calc_rate(hw, &cfg, rate, parent_rate)) {
584 pr_err("%s: Failed to set %s rate %lu\n", __func__,
585 __clk_get_name(hw->clk), rate);
590 spin_lock_irqsave(pll->lock, flags);
592 _get_pll_mnp(pll, &old_cfg);
594 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
595 ret = _program_pll(hw, &cfg, rate);
598 spin_unlock_irqrestore(pll->lock, flags);
603 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
604 unsigned long *prate)
606 struct tegra_clk_pll *pll = to_clk_pll(hw);
607 struct tegra_clk_pll_freq_table cfg;
609 if (pll->params->flags & TEGRA_PLL_FIXED)
610 return pll->params->fixed_rate;
612 /* PLLM is used for memory; we do not change rate */
613 if (pll->params->flags & TEGRA_PLLM)
614 return __clk_get_rate(hw->clk);
616 if (_get_table_rate(hw, &cfg, rate, *prate) &&
617 _calc_rate(hw, &cfg, rate, *prate))
620 return cfg.output_rate;
623 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
624 unsigned long parent_rate)
626 struct tegra_clk_pll *pll = to_clk_pll(hw);
627 struct tegra_clk_pll_freq_table cfg;
629 u64 rate = parent_rate;
632 val = pll_readl_base(pll);
634 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
637 if ((pll->params->flags & TEGRA_PLL_FIXED) &&
638 !(val & PLL_BASE_OVERRIDE)) {
639 struct tegra_clk_pll_freq_table sel;
640 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
642 pr_err("Clock %s has unknown fixed frequency\n",
643 __clk_get_name(hw->clk));
646 return pll->params->fixed_rate;
649 _get_pll_mnp(pll, &cfg);
651 pdiv = _hw_to_p_div(hw, cfg.p);
665 static int clk_plle_training(struct tegra_clk_pll *pll)
668 unsigned long timeout;
674 * PLLE is already disabled, and setup cleared;
675 * create falling edge on PLLE IDDQ input.
677 val = readl(pll->pmc + PMC_SATA_PWRGT);
678 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
679 writel(val, pll->pmc + PMC_SATA_PWRGT);
681 val = readl(pll->pmc + PMC_SATA_PWRGT);
682 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
683 writel(val, pll->pmc + PMC_SATA_PWRGT);
685 val = readl(pll->pmc + PMC_SATA_PWRGT);
686 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
687 writel(val, pll->pmc + PMC_SATA_PWRGT);
689 val = pll_readl_misc(pll);
691 timeout = jiffies + msecs_to_jiffies(100);
693 val = pll_readl_misc(pll);
694 if (val & PLLE_MISC_READY)
696 if (time_after(jiffies, timeout)) {
697 pr_err("%s: timeout waiting for PLLE\n", __func__);
706 static int clk_plle_enable(struct clk_hw *hw)
708 struct tegra_clk_pll *pll = to_clk_pll(hw);
709 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
710 struct tegra_clk_pll_freq_table sel;
714 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
719 val = pll_readl_misc(pll);
720 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
721 pll_writel_misc(val, pll);
723 val = pll_readl_misc(pll);
724 if (!(val & PLLE_MISC_READY)) {
725 err = clk_plle_training(pll);
730 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
731 /* configure dividers */
732 val = pll_readl_base(pll);
733 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
734 val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
735 val |= sel.m << pll->params->div_nmp->divm_shift;
736 val |= sel.n << pll->params->div_nmp->divn_shift;
737 val |= sel.p << pll->params->div_nmp->divp_shift;
738 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
739 pll_writel_base(val, pll);
742 val = pll_readl_misc(pll);
743 val |= PLLE_MISC_SETUP_VALUE;
744 val |= PLLE_MISC_LOCK_ENABLE;
745 pll_writel_misc(val, pll);
747 val = readl(pll->clk_base + PLLE_SS_CTRL);
748 val |= PLLE_SS_DISABLE;
749 writel(val, pll->clk_base + PLLE_SS_CTRL);
751 val |= pll_readl_base(pll);
752 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
753 pll_writel_base(val, pll);
755 clk_pll_wait_for_lock(pll);
760 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
761 unsigned long parent_rate)
763 struct tegra_clk_pll *pll = to_clk_pll(hw);
764 u32 val = pll_readl_base(pll);
765 u32 divn = 0, divm = 0, divp = 0;
766 u64 rate = parent_rate;
768 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
769 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
770 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
778 const struct clk_ops tegra_clk_pll_ops = {
779 .is_enabled = clk_pll_is_enabled,
780 .enable = clk_pll_enable,
781 .disable = clk_pll_disable,
782 .recalc_rate = clk_pll_recalc_rate,
783 .round_rate = clk_pll_round_rate,
784 .set_rate = clk_pll_set_rate,
787 const struct clk_ops tegra_clk_plle_ops = {
788 .recalc_rate = clk_plle_recalc_rate,
789 .is_enabled = clk_pll_is_enabled,
790 .disable = clk_pll_disable,
791 .enable = clk_plle_enable,
794 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
796 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
797 unsigned long parent_rate)
799 if (parent_rate > pll_params->cf_max)
805 static unsigned long _clip_vco_min(unsigned long vco_min,
806 unsigned long parent_rate)
808 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
811 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
812 void __iomem *clk_base,
813 unsigned long parent_rate)
818 switch (parent_rate) {
834 pr_err("%s: Unexpected reference rate %lu\n",
835 __func__, parent_rate);
840 val = step_a << pll_params->stepa_shift;
841 val |= step_b << pll_params->stepb_shift;
842 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
847 static int clk_pll_iddq_enable(struct clk_hw *hw)
849 struct tegra_clk_pll *pll = to_clk_pll(hw);
850 unsigned long flags = 0;
856 spin_lock_irqsave(pll->lock, flags);
858 val = pll_readl(pll->params->iddq_reg, pll);
859 val &= ~BIT(pll->params->iddq_bit_idx);
860 pll_writel(val, pll->params->iddq_reg, pll);
865 ret = clk_pll_wait_for_lock(pll);
868 spin_unlock_irqrestore(pll->lock, flags);
873 static void clk_pll_iddq_disable(struct clk_hw *hw)
875 struct tegra_clk_pll *pll = to_clk_pll(hw);
876 unsigned long flags = 0;
880 spin_lock_irqsave(pll->lock, flags);
882 _clk_pll_disable(hw);
884 val = pll_readl(pll->params->iddq_reg, pll);
885 val |= BIT(pll->params->iddq_bit_idx);
886 pll_writel(val, pll->params->iddq_reg, pll);
890 spin_unlock_irqrestore(pll->lock, flags);
893 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
894 struct tegra_clk_pll_freq_table *cfg,
895 unsigned long rate, unsigned long parent_rate)
897 struct tegra_clk_pll *pll = to_clk_pll(hw);
904 p = DIV_ROUND_UP(pll->params->vco_min, rate);
905 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
906 cfg->output_rate = rate * p;
907 cfg->n = cfg->output_rate * cfg->m / parent_rate;
909 p_div = _p_div_to_hw(hw, p);
915 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
921 static int _pll_ramp_calc_pll(struct clk_hw *hw,
922 struct tegra_clk_pll_freq_table *cfg,
923 unsigned long rate, unsigned long parent_rate)
925 struct tegra_clk_pll *pll = to_clk_pll(hw);
928 err = _get_table_rate(hw, cfg, rate, parent_rate);
930 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
932 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
937 p_div = _p_div_to_hw(hw, cfg->p);
944 if (cfg->p > pll->params->max_p)
951 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
952 unsigned long parent_rate)
954 struct tegra_clk_pll *pll = to_clk_pll(hw);
955 struct tegra_clk_pll_freq_table cfg, old_cfg;
956 unsigned long flags = 0;
959 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
964 spin_lock_irqsave(pll->lock, flags);
966 _get_pll_mnp(pll, &old_cfg);
968 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
969 ret = _program_pll(hw, &cfg, rate);
972 spin_unlock_irqrestore(pll->lock, flags);
977 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
978 unsigned long *prate)
980 struct tegra_clk_pll_freq_table cfg;
982 u64 output_rate = *prate;
984 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
988 p_div = _hw_to_p_div(hw, cfg.p);
992 output_rate *= cfg.n;
993 do_div(output_rate, cfg.m * p_div);
998 static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate,
999 unsigned long parent_rate)
1001 struct tegra_clk_pll_freq_table cfg;
1002 struct tegra_clk_pll *pll = to_clk_pll(hw);
1003 unsigned long flags = 0;
1007 spin_lock_irqsave(pll->lock, flags);
1009 state = clk_pll_is_enabled(hw);
1011 if (rate != clk_get_rate(hw->clk)) {
1012 pr_err("%s: Cannot change active PLLM\n", __func__);
1019 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1023 _update_pll_mnp(pll, &cfg);
1027 spin_unlock_irqrestore(pll->lock, flags);
1032 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1036 val = pll_readl_misc(pll);
1037 val |= PLLCX_MISC_STROBE;
1038 pll_writel_misc(val, pll);
1041 val &= ~PLLCX_MISC_STROBE;
1042 pll_writel_misc(val, pll);
1045 static int clk_pllc_enable(struct clk_hw *hw)
1047 struct tegra_clk_pll *pll = to_clk_pll(hw);
1050 unsigned long flags = 0;
1053 spin_lock_irqsave(pll->lock, flags);
1055 _clk_pll_enable(hw);
1058 val = pll_readl_misc(pll);
1059 val &= ~PLLCX_MISC_RESET;
1060 pll_writel_misc(val, pll);
1065 ret = clk_pll_wait_for_lock(pll);
1068 spin_unlock_irqrestore(pll->lock, flags);
1073 static void _clk_pllc_disable(struct clk_hw *hw)
1075 struct tegra_clk_pll *pll = to_clk_pll(hw);
1078 _clk_pll_disable(hw);
1080 val = pll_readl_misc(pll);
1081 val |= PLLCX_MISC_RESET;
1082 pll_writel_misc(val, pll);
1086 static void clk_pllc_disable(struct clk_hw *hw)
1088 struct tegra_clk_pll *pll = to_clk_pll(hw);
1089 unsigned long flags = 0;
1092 spin_lock_irqsave(pll->lock, flags);
1094 _clk_pllc_disable(hw);
1097 spin_unlock_irqrestore(pll->lock, flags);
1100 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1101 unsigned long input_rate, u32 n)
1103 u32 val, n_threshold;
1105 switch (input_rate) {
1120 pr_err("%s: Unexpected reference rate %lu\n",
1121 __func__, input_rate);
1125 val = pll_readl_misc(pll);
1126 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1127 val |= n <= n_threshold ?
1128 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1129 pll_writel_misc(val, pll);
1134 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1135 unsigned long parent_rate)
1137 struct tegra_clk_pll_freq_table cfg, old_cfg;
1138 struct tegra_clk_pll *pll = to_clk_pll(hw);
1139 unsigned long flags = 0;
1143 spin_lock_irqsave(pll->lock, flags);
1145 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1149 _get_pll_mnp(pll, &old_cfg);
1151 if (cfg.m != old_cfg.m) {
1156 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1159 state = clk_pll_is_enabled(hw);
1161 _clk_pllc_disable(hw);
1163 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1167 _update_pll_mnp(pll, &cfg);
1170 ret = clk_pllc_enable(hw);
1174 spin_unlock_irqrestore(pll->lock, flags);
1179 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1180 struct tegra_clk_pll_freq_table *cfg,
1181 unsigned long rate, unsigned long parent_rate)
1184 u64 output_rate = parent_rate;
1186 m = _pll_fixed_mdiv(pll->params, parent_rate);
1187 n = rate * m / parent_rate;
1190 do_div(output_rate, m);
1199 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1200 unsigned long parent_rate)
1202 struct tegra_clk_pll_freq_table cfg, old_cfg;
1203 struct tegra_clk_pll *pll = to_clk_pll(hw);
1204 unsigned long flags = 0;
1208 spin_lock_irqsave(pll->lock, flags);
1210 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1211 _get_pll_mnp(pll, &old_cfg);
1214 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1215 state = clk_pll_is_enabled(hw);
1217 _clk_pll_disable(hw);
1219 _update_pll_mnp(pll, &cfg);
1222 _clk_pll_enable(hw);
1223 ret = clk_pll_wait_for_lock(pll);
1228 spin_unlock_irqrestore(pll->lock, flags);
1233 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1234 unsigned long parent_rate)
1236 struct tegra_clk_pll_freq_table cfg;
1237 struct tegra_clk_pll *pll = to_clk_pll(hw);
1238 u64 rate = parent_rate;
1240 _get_pll_mnp(pll, &cfg);
1243 do_div(rate, cfg.m);
1248 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1249 unsigned long *prate)
1251 struct tegra_clk_pll *pll = to_clk_pll(hw);
1253 return _pllre_calc_rate(pll, NULL, rate, *prate);
1256 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1258 struct tegra_clk_pll *pll = to_clk_pll(hw);
1259 struct tegra_clk_pll_freq_table sel;
1262 unsigned long flags = 0;
1263 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
1265 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1269 spin_lock_irqsave(pll->lock, flags);
1271 val = pll_readl_base(pll);
1272 val &= ~BIT(29); /* Disable lock override */
1273 pll_writel_base(val, pll);
1275 val = pll_readl(pll->params->aux_reg, pll);
1276 val |= PLLE_AUX_ENABLE_SWCTL;
1277 val &= ~PLLE_AUX_SEQ_ENABLE;
1278 pll_writel(val, pll->params->aux_reg, pll);
1281 val = pll_readl_misc(pll);
1282 val |= PLLE_MISC_LOCK_ENABLE;
1283 val |= PLLE_MISC_IDDQ_SW_CTRL;
1284 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1285 val |= PLLE_MISC_PLLE_PTS;
1286 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
1287 pll_writel_misc(val, pll);
1290 val = pll_readl(PLLE_SS_CTRL, pll);
1291 val |= PLLE_SS_DISABLE;
1292 pll_writel(val, PLLE_SS_CTRL, pll);
1294 val = pll_readl_base(pll);
1295 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
1296 val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
1297 val |= sel.m << pll->params->div_nmp->divm_shift;
1298 val |= sel.n << pll->params->div_nmp->divn_shift;
1299 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1300 pll_writel_base(val, pll);
1303 _clk_pll_enable(hw);
1304 ret = clk_pll_wait_for_lock(pll);
1309 val = pll_readl(PLLE_SS_CTRL, pll);
1310 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1311 val &= ~PLLE_SS_COEFFICIENTS_MASK;
1312 val |= PLLE_SS_COEFFICIENTS_VAL;
1313 pll_writel(val, PLLE_SS_CTRL, pll);
1314 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1315 pll_writel(val, PLLE_SS_CTRL, pll);
1317 val &= ~PLLE_SS_CNTL_INTERP_RESET;
1318 pll_writel(val, PLLE_SS_CTRL, pll);
1321 /* TODO: enable hw control of xusb brick pll */
1325 spin_unlock_irqrestore(pll->lock, flags);
1330 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1332 struct tegra_clk_pll *pll = to_clk_pll(hw);
1333 unsigned long flags = 0;
1337 spin_lock_irqsave(pll->lock, flags);
1339 _clk_pll_disable(hw);
1341 val = pll_readl_misc(pll);
1342 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1343 pll_writel_misc(val, pll);
1347 spin_unlock_irqrestore(pll->lock, flags);
1351 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1352 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1355 struct tegra_clk_pll *pll;
1357 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1359 return ERR_PTR(-ENOMEM);
1361 pll->clk_base = clk_base;
1364 pll->params = pll_params;
1367 if (!pll_params->div_nmp)
1368 pll_params->div_nmp = &default_nmp;
1373 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1374 const char *name, const char *parent_name, unsigned long flags,
1375 const struct clk_ops *ops)
1377 struct clk_init_data init;
1382 init.parent_names = (parent_name ? &parent_name : NULL);
1383 init.num_parents = (parent_name ? 1 : 0);
1385 /* Data in .init is copied by clk_register(), so stack variable OK */
1386 pll->hw.init = &init;
1388 return clk_register(NULL, &pll->hw);
1391 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1392 void __iomem *clk_base, void __iomem *pmc,
1393 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1396 struct tegra_clk_pll *pll;
1399 pll_params->flags |= TEGRA_PLL_BYPASS;
1400 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1401 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1403 return ERR_CAST(pll);
1405 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1406 &tegra_clk_pll_ops);
1413 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1414 void __iomem *clk_base, void __iomem *pmc,
1415 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1418 struct tegra_clk_pll *pll;
1421 pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
1422 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1423 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1425 return ERR_CAST(pll);
1427 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1428 &tegra_clk_plle_ops);
1435 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
1436 static const struct clk_ops tegra_clk_pllxc_ops = {
1437 .is_enabled = clk_pll_is_enabled,
1438 .enable = clk_pll_iddq_enable,
1439 .disable = clk_pll_iddq_disable,
1440 .recalc_rate = clk_pll_recalc_rate,
1441 .round_rate = clk_pll_ramp_round_rate,
1442 .set_rate = clk_pllxc_set_rate,
1445 static const struct clk_ops tegra_clk_pllm_ops = {
1446 .is_enabled = clk_pll_is_enabled,
1447 .enable = clk_pll_iddq_enable,
1448 .disable = clk_pll_iddq_disable,
1449 .recalc_rate = clk_pll_recalc_rate,
1450 .round_rate = clk_pll_ramp_round_rate,
1451 .set_rate = clk_pllm_set_rate,
1454 static const struct clk_ops tegra_clk_pllc_ops = {
1455 .is_enabled = clk_pll_is_enabled,
1456 .enable = clk_pllc_enable,
1457 .disable = clk_pllc_disable,
1458 .recalc_rate = clk_pll_recalc_rate,
1459 .round_rate = clk_pll_ramp_round_rate,
1460 .set_rate = clk_pllc_set_rate,
1463 static const struct clk_ops tegra_clk_pllre_ops = {
1464 .is_enabled = clk_pll_is_enabled,
1465 .enable = clk_pll_iddq_enable,
1466 .disable = clk_pll_iddq_disable,
1467 .recalc_rate = clk_pllre_recalc_rate,
1468 .round_rate = clk_pllre_round_rate,
1469 .set_rate = clk_pllre_set_rate,
1472 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1473 .is_enabled = clk_pll_is_enabled,
1474 .enable = clk_plle_tegra114_enable,
1475 .disable = clk_plle_tegra114_disable,
1476 .recalc_rate = clk_pll_recalc_rate,
1480 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1481 void __iomem *clk_base, void __iomem *pmc,
1482 unsigned long flags,
1483 struct tegra_clk_pll_params *pll_params,
1486 struct tegra_clk_pll *pll;
1487 struct clk *clk, *parent;
1488 unsigned long parent_rate;
1492 parent = __clk_lookup(parent_name);
1494 WARN(1, "parent clk %s of %s must be registered first\n",
1496 return ERR_PTR(-EINVAL);
1499 if (!pll_params->pdiv_tohw)
1500 return ERR_PTR(-EINVAL);
1502 parent_rate = __clk_get_rate(parent);
1504 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1506 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
1508 return ERR_PTR(err);
1510 val = readl_relaxed(clk_base + pll_params->base_reg);
1511 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1513 if (val & PLL_BASE_ENABLE)
1514 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
1516 val_iddq |= BIT(pll_params->iddq_bit_idx);
1517 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
1520 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1521 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1523 return ERR_CAST(pll);
1525 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1526 &tegra_clk_pllxc_ops);
1533 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1534 void __iomem *clk_base, void __iomem *pmc,
1535 unsigned long flags,
1536 struct tegra_clk_pll_params *pll_params,
1537 spinlock_t *lock, unsigned long parent_rate)
1540 struct tegra_clk_pll *pll;
1543 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC;
1545 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1547 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1549 return ERR_CAST(pll);
1551 /* program minimum rate by default */
1553 val = pll_readl_base(pll);
1554 if (val & PLL_BASE_ENABLE)
1555 WARN_ON(val & pll_params->iddq_bit_idx);
1559 m = _pll_fixed_mdiv(pll_params, parent_rate);
1560 val = m << PLL_BASE_DIVM_SHIFT;
1561 val |= (pll_params->vco_min / parent_rate)
1562 << PLL_BASE_DIVN_SHIFT;
1563 pll_writel_base(val, pll);
1566 /* disable lock override */
1568 val = pll_readl_misc(pll);
1570 pll_writel_misc(val, pll);
1572 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1573 &tegra_clk_pllre_ops);
1580 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1581 void __iomem *clk_base, void __iomem *pmc,
1582 unsigned long flags,
1583 struct tegra_clk_pll_params *pll_params,
1586 struct tegra_clk_pll *pll;
1587 struct clk *clk, *parent;
1588 unsigned long parent_rate;
1590 if (!pll_params->pdiv_tohw)
1591 return ERR_PTR(-EINVAL);
1593 parent = __clk_lookup(parent_name);
1595 WARN(1, "parent clk %s of %s must be registered first\n",
1597 return ERR_PTR(-EINVAL);
1600 parent_rate = __clk_get_rate(parent);
1602 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1604 pll_params->flags |= TEGRA_PLL_BYPASS;
1605 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1606 pll_params->flags |= TEGRA_PLLM;
1607 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1609 return ERR_CAST(pll);
1611 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1612 &tegra_clk_pllm_ops);
1619 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1620 void __iomem *clk_base, void __iomem *pmc,
1621 unsigned long flags,
1622 struct tegra_clk_pll_params *pll_params,
1625 struct clk *parent, *clk;
1626 struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
1627 struct tegra_clk_pll *pll;
1628 struct tegra_clk_pll_freq_table cfg;
1629 unsigned long parent_rate;
1632 return ERR_PTR(-EINVAL);
1634 parent = __clk_lookup(parent_name);
1636 WARN(1, "parent clk %s of %s must be registered first\n",
1638 return ERR_PTR(-EINVAL);
1641 parent_rate = __clk_get_rate(parent);
1643 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1645 pll_params->flags |= TEGRA_PLL_BYPASS;
1646 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1648 return ERR_CAST(pll);
1651 * Most of PLLC register fields are shadowed, and can not be read
1652 * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
1653 * Initialize PLL to default state: disabled, reset; shadow registers
1654 * loaded with default parameters; dividers are preset for half of
1655 * minimum VCO rate (the latter assured that shadowed divider settings
1656 * are within supported range).
1659 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1660 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1662 while (p_tohw->pdiv) {
1663 if (p_tohw->pdiv == 2) {
1664 cfg.p = p_tohw->hw_val;
1670 if (!p_tohw->pdiv) {
1672 return ERR_PTR(-EINVAL);
1675 pll_writel_base(0, pll);
1676 _update_pll_mnp(pll, &cfg);
1678 pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
1679 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
1680 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
1681 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
1683 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1685 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1686 &tegra_clk_pllc_ops);
1693 struct clk *tegra_clk_register_plle_tegra114(const char *name,
1694 const char *parent_name,
1695 void __iomem *clk_base, unsigned long flags,
1696 struct tegra_clk_pll_params *pll_params,
1699 struct tegra_clk_pll *pll;
1703 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1704 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1706 return ERR_CAST(pll);
1708 /* ensure parent is set to pll_re_vco */
1710 val = pll_readl_base(pll);
1711 val_aux = pll_readl(pll_params->aux_reg, pll);
1713 if (val & PLL_BASE_ENABLE) {
1714 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
1715 (val_aux & PLLE_AUX_PLLP_SEL))
1716 WARN(1, "pll_e enabled with unsupported parent %s\n",
1717 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
1720 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
1721 pll_writel(val_aux, pll_params->aux_reg, pll);
1724 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1725 &tegra_clk_plle_tegra114_ops);
1733 #ifdef CONFIG_ARCH_TEGRA_124_SOC
1734 static const struct clk_ops tegra_clk_pllss_ops = {
1735 .is_enabled = clk_pll_is_enabled,
1736 .enable = clk_pll_iddq_enable,
1737 .disable = clk_pll_iddq_disable,
1738 .recalc_rate = clk_pll_recalc_rate,
1739 .round_rate = clk_pll_ramp_round_rate,
1740 .set_rate = clk_pllxc_set_rate,
1743 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
1744 void __iomem *clk_base, unsigned long flags,
1745 struct tegra_clk_pll_params *pll_params,
1748 struct tegra_clk_pll *pll;
1749 struct clk *clk, *parent;
1750 struct tegra_clk_pll_freq_table cfg;
1751 unsigned long parent_rate;
1755 if (!pll_params->div_nmp)
1756 return ERR_PTR(-EINVAL);
1758 parent = __clk_lookup(parent_name);
1760 WARN(1, "parent clk %s of %s must be registered first\n",
1762 return ERR_PTR(-EINVAL);
1765 pll_params->flags = TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_USE_LOCK;
1766 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1768 return ERR_CAST(pll);
1770 val = pll_readl_base(pll);
1771 val &= ~PLLSS_REF_SRC_SEL_MASK;
1772 pll_writel_base(val, pll);
1774 parent_rate = __clk_get_rate(parent);
1776 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1778 /* initialize PLL to minimum rate */
1780 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1781 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1783 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
1787 return ERR_PTR(-EINVAL);
1790 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
1792 _update_pll_mnp(pll, &cfg);
1794 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
1795 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
1796 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
1797 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
1799 val = pll_readl_base(pll);
1800 if (val & PLL_BASE_ENABLE) {
1801 if (val & BIT(pll_params->iddq_bit_idx)) {
1802 WARN(1, "%s is on but IDDQ set\n", name);
1804 return ERR_PTR(-EINVAL);
1807 val |= BIT(pll_params->iddq_bit_idx);
1809 val &= ~PLLSS_LOCK_OVERRIDE;
1810 pll_writel_base(val, pll);
1812 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1813 &tegra_clk_pllss_ops);