2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/clk-provider.h>
20 #include <linux/of_address.h>
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/clk/tegra.h>
28 #define PLLX_BASE 0xe0
29 #define PLLX_MISC 0xe4
30 #define PLLX_MISC2 0x514
31 #define PLLX_MISC3 0x518
33 #define CCLKG_BURST_POLICY 0x368
34 #define CCLKLP_BURST_POLICY 0x370
35 #define SCLK_BURST_POLICY 0x028
36 #define SYSTEM_CLK_RATE 0x030
37 #define SCLK_DIVIDER 0x2c
39 static DEFINE_SPINLOCK(sysrate_lock);
41 enum tegra_super_gen {
46 struct tegra_super_gen_info {
47 enum tegra_super_gen gen;
48 const char **sclk_parents;
49 const char **cclk_g_parents;
50 const char **cclk_lp_parents;
52 int num_cclk_g_parents;
53 int num_cclk_lp_parents;
56 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
57 "pll_p", "pll_p_out2", "unused",
58 "clk_32k", "pll_m_out1" };
60 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
61 "pll_p", "pll_p_out4", "unused",
62 "unused", "pll_x", "unused", "unused",
63 "unused", "unused", "unused", "unused",
66 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
67 "pll_p", "pll_p_out4", "unused",
68 "unused", "pll_x", "pll_x_out0" };
70 static const struct tegra_super_gen_info tegra_super_gen_info_gen4 = {
72 .sclk_parents = sclk_parents,
73 .cclk_g_parents = cclk_g_parents,
74 .cclk_lp_parents = cclk_lp_parents,
75 .num_sclk_parents = ARRAY_SIZE(sclk_parents),
76 .num_cclk_g_parents = ARRAY_SIZE(cclk_g_parents),
77 .num_cclk_lp_parents = ARRAY_SIZE(cclk_lp_parents),
80 static const char *sclk_parents_gen5[] = { "clk_m", "pll_c_out1", "pll_c4_out3",
81 "pll_p", "pll_p_out2", "pll_c4_out1",
82 "clk_32k", "pll_c4_out2" };
84 static const char *cclk_g_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
85 "pll_p", "pll_p_out4", "unused",
86 "unused", "pll_x", "unused", "unused",
87 "unused", "unused", "unused", "unused",
90 static const char *cclk_lp_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
91 "pll_p", "pll_p_out4", "unused",
92 "unused", "pll_x", "unused", "unused",
93 "unused", "unused", "unused", "unused",
96 static const struct tegra_super_gen_info tegra_super_gen_info_gen5 = {
98 .sclk_parents = sclk_parents_gen5,
99 .cclk_g_parents = cclk_g_parents_gen5,
100 .cclk_lp_parents = cclk_lp_parents_gen5,
101 .num_sclk_parents = ARRAY_SIZE(sclk_parents_gen5),
102 .num_cclk_g_parents = ARRAY_SIZE(cclk_g_parents_gen5),
103 .num_cclk_lp_parents = ARRAY_SIZE(cclk_lp_parents_gen5),
106 static void __init tegra_sclk_init(void __iomem *clk_base,
107 struct tegra_clk *tegra_clks,
108 const struct tegra_super_gen_info *gen_info)
114 dt_clk = tegra_lookup_dt_id(tegra_clk_sclk_mux, tegra_clks);
116 clk = tegra_clk_register_super_mux("sclk_mux",
117 gen_info->sclk_parents,
118 gen_info->num_sclk_parents,
120 clk_base + SCLK_BURST_POLICY,
126 dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
128 clk = clk_register_divider(NULL, "sclk", "sclk_mux", 0,
129 clk_base + SCLK_DIVIDER, 0, 8,
135 dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
137 clk = tegra_clk_register_super_mux("sclk",
138 gen_info->sclk_parents,
139 gen_info->num_sclk_parents,
141 clk_base + SCLK_BURST_POLICY,
148 dt_clk = tegra_lookup_dt_id(tegra_clk_hclk, tegra_clks);
150 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
151 clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
153 clk = clk_register_gate(NULL, "hclk", "hclk_div",
154 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
155 clk_base + SYSTEM_CLK_RATE,
156 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
161 dt_clk = tegra_lookup_dt_id(tegra_clk_pclk, tegra_clks);
165 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
166 clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
168 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT |
169 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
170 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
174 static void __init tegra_super_clk_init(void __iomem *clk_base,
175 void __iomem *pmc_base,
176 struct tegra_clk *tegra_clks,
177 struct tegra_clk_pll_params *params,
178 const struct tegra_super_gen_info *gen_info)
184 dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_g, tegra_clks);
186 if (gen_info->gen == gen5) {
187 clk = tegra_clk_register_super_mux("cclk_g",
188 gen_info->cclk_g_parents,
189 gen_info->num_cclk_g_parents,
191 clk_base + CCLKG_BURST_POLICY,
194 clk = tegra_clk_register_super_mux("cclk_g",
195 gen_info->cclk_g_parents,
196 gen_info->num_cclk_g_parents,
198 clk_base + CCLKG_BURST_POLICY,
205 dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_lp, tegra_clks);
207 if (gen_info->gen == gen5) {
208 clk = tegra_clk_register_super_mux("cclk_lp",
209 gen_info->cclk_lp_parents,
210 gen_info->num_cclk_lp_parents,
212 clk_base + CCLKLP_BURST_POLICY,
215 clk = tegra_clk_register_super_mux("cclk_lp",
216 gen_info->cclk_lp_parents,
217 gen_info->num_cclk_lp_parents,
219 clk_base + CCLKLP_BURST_POLICY,
220 TEGRA_DIVIDER_2, 4, 8, 9, NULL);
225 tegra_sclk_init(clk_base, tegra_clks, gen_info);
227 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
228 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
229 defined(CONFIG_ARCH_TEGRA_210_SOC)
231 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x, tegra_clks);
235 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
236 pmc_base, CLK_IGNORE_UNUSED, params, NULL);
241 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x_out0, tegra_clks);
244 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
245 CLK_SET_RATE_PARENT, 1, 2);
250 void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
251 void __iomem *pmc_base,
252 struct tegra_clk *tegra_clks,
253 struct tegra_clk_pll_params *params)
255 tegra_super_clk_init(clk_base, pmc_base, tegra_clks, params,
256 &tegra_super_gen_info_gen4);
259 void __init tegra_super_clk_gen5_init(void __iomem *clk_base,
260 void __iomem *pmc_base,
261 struct tegra_clk *tegra_clks,
262 struct tegra_clk_pll_params *params)
264 tegra_super_clk_init(clk_base, pmc_base, tegra_clks, params,
265 &tegra_super_gen_info_gen5);