drivers/clk/tegra/clk-tegra30.c

   1 /*
   2  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/delay.h>
  19 #include <linux/clk.h>
  20 #include <linux/clk-provider.h>
  21 #include <linux/clkdev.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/clk/tegra.h>
  25 #include <linux/tegra-powergate.h>
  26
  27 #include "clk.h"
  28
  29 #define RST_DEVICES_L 0x004
  30 #define RST_DEVICES_H 0x008
  31 #define RST_DEVICES_U 0x00c
  32 #define RST_DEVICES_V 0x358
  33 #define RST_DEVICES_W 0x35c
  34 #define RST_DEVICES_SET_L 0x300
  35 #define RST_DEVICES_CLR_L 0x304
  36 #define RST_DEVICES_SET_H 0x308
  37 #define RST_DEVICES_CLR_H 0x30c
  38 #define RST_DEVICES_SET_U 0x310
  39 #define RST_DEVICES_CLR_U 0x314
  40 #define RST_DEVICES_SET_V 0x430
  41 #define RST_DEVICES_CLR_V 0x434
  42 #define RST_DEVICES_SET_W 0x438
  43 #define RST_DEVICES_CLR_W 0x43c
  44 #define RST_DEVICES_NUM 5
  45
  46 #define CLK_OUT_ENB_L 0x010
  47 #define CLK_OUT_ENB_H 0x014
  48 #define CLK_OUT_ENB_U 0x018
  49 #define CLK_OUT_ENB_V 0x360
  50 #define CLK_OUT_ENB_W 0x364
  51 #define CLK_OUT_ENB_SET_L 0x320
  52 #define CLK_OUT_ENB_CLR_L 0x324
  53 #define CLK_OUT_ENB_SET_H 0x328
  54 #define CLK_OUT_ENB_CLR_H 0x32c
  55 #define CLK_OUT_ENB_SET_U 0x330
  56 #define CLK_OUT_ENB_CLR_U 0x334
  57 #define CLK_OUT_ENB_SET_V 0x440
  58 #define CLK_OUT_ENB_CLR_V 0x444
  59 #define CLK_OUT_ENB_SET_W 0x448
  60 #define CLK_OUT_ENB_CLR_W 0x44c
  61 #define CLK_OUT_ENB_NUM 5
  62
  63 #define OSC_CTRL                        0x50
  64 #define OSC_CTRL_OSC_FREQ_MASK          (0xF<<28)
  65 #define OSC_CTRL_OSC_FREQ_13MHZ         (0X0<<28)
  66 #define OSC_CTRL_OSC_FREQ_19_2MHZ       (0X4<<28)
  67 #define OSC_CTRL_OSC_FREQ_12MHZ         (0X8<<28)
  68 #define OSC_CTRL_OSC_FREQ_26MHZ         (0XC<<28)
  69 #define OSC_CTRL_OSC_FREQ_16_8MHZ       (0X1<<28)
  70 #define OSC_CTRL_OSC_FREQ_38_4MHZ       (0X5<<28)
  71 #define OSC_CTRL_OSC_FREQ_48MHZ         (0X9<<28)
  72 #define OSC_CTRL_MASK                   (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
  73
  74 #define OSC_CTRL_PLL_REF_DIV_MASK       (3<<26)
  75 #define OSC_CTRL_PLL_REF_DIV_1          (0<<26)
  76 #define OSC_CTRL_PLL_REF_DIV_2          (1<<26)
  77 #define OSC_CTRL_PLL_REF_DIV_4          (2<<26)
  78
  79 #define OSC_FREQ_DET                    0x58
  80 #define OSC_FREQ_DET_TRIG               BIT(31)
  81
  82 #define OSC_FREQ_DET_STATUS             0x5c
  83 #define OSC_FREQ_DET_BUSY               BIT(31)
  84 #define OSC_FREQ_DET_CNT_MASK           0xffff
  85
  86 #define CCLKG_BURST_POLICY 0x368
  87 #define SUPER_CCLKG_DIVIDER 0x36c
  88 #define CCLKLP_BURST_POLICY 0x370
  89 #define SUPER_CCLKLP_DIVIDER 0x374
  90 #define SCLK_BURST_POLICY 0x028
  91 #define SUPER_SCLK_DIVIDER 0x02c
  92
  93 #define SYSTEM_CLK_RATE 0x030
  94
  95 #define PLLC_BASE 0x80
  96 #define PLLC_MISC 0x8c
  97 #define PLLM_BASE 0x90
  98 #define PLLM_MISC 0x9c
  99 #define PLLP_BASE 0xa0
 100 #define PLLP_MISC 0xac
 101 #define PLLX_BASE 0xe0
 102 #define PLLX_MISC 0xe4
 103 #define PLLD_BASE 0xd0
 104 #define PLLD_MISC 0xdc
 105 #define PLLD2_BASE 0x4b8
 106 #define PLLD2_MISC 0x4bc
 107 #define PLLE_BASE 0xe8
 108 #define PLLE_MISC 0xec
 109 #define PLLA_BASE 0xb0
 110 #define PLLA_MISC 0xbc
 111 #define PLLU_BASE 0xc0
 112 #define PLLU_MISC 0xcc
 113
 114 #define PLL_MISC_LOCK_ENABLE 18
 115 #define PLLDU_MISC_LOCK_ENABLE 22
 116 #define PLLE_MISC_LOCK_ENABLE 9
 117
 118 #define PLL_BASE_LOCK BIT(27)
 119 #define PLLE_MISC_LOCK BIT(11)
 120
 121 #define PLLE_AUX 0x48c
 122 #define PLLC_OUT 0x84
 123 #define PLLM_OUT 0x94
 124 #define PLLP_OUTA 0xa4
 125 #define PLLP_OUTB 0xa8
 126 #define PLLA_OUT 0xb4
 127
 128 #define AUDIO_SYNC_CLK_I2S0 0x4a0
 129 #define AUDIO_SYNC_CLK_I2S1 0x4a4
 130 #define AUDIO_SYNC_CLK_I2S2 0x4a8
 131 #define AUDIO_SYNC_CLK_I2S3 0x4ac
 132 #define AUDIO_SYNC_CLK_I2S4 0x4b0
 133 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
 134
 135 #define PMC_CLK_OUT_CNTRL 0x1a8
 136
 137 #define CLK_SOURCE_I2S0 0x1d8
 138 #define CLK_SOURCE_I2S1 0x100
 139 #define CLK_SOURCE_I2S2 0x104
 140 #define CLK_SOURCE_I2S3 0x3bc
 141 #define CLK_SOURCE_I2S4 0x3c0
 142 #define CLK_SOURCE_SPDIF_OUT 0x108
 143 #define CLK_SOURCE_SPDIF_IN 0x10c
 144 #define CLK_SOURCE_PWM 0x110
 145 #define CLK_SOURCE_D_AUDIO 0x3d0
 146 #define CLK_SOURCE_DAM0 0x3d8
 147 #define CLK_SOURCE_DAM1 0x3dc
 148 #define CLK_SOURCE_DAM2 0x3e0
 149 #define CLK_SOURCE_HDA 0x428
 150 #define CLK_SOURCE_HDA2CODEC_2X 0x3e4
 151 #define CLK_SOURCE_SBC1 0x134
 152 #define CLK_SOURCE_SBC2 0x118
 153 #define CLK_SOURCE_SBC3 0x11c
 154 #define CLK_SOURCE_SBC4 0x1b4
 155 #define CLK_SOURCE_SBC5 0x3c8
 156 #define CLK_SOURCE_SBC6 0x3cc
 157 #define CLK_SOURCE_SATA_OOB 0x420
 158 #define CLK_SOURCE_SATA 0x424
 159 #define CLK_SOURCE_NDFLASH 0x160
 160 #define CLK_SOURCE_NDSPEED 0x3f8
 161 #define CLK_SOURCE_VFIR 0x168
 162 #define CLK_SOURCE_SDMMC1 0x150
 163 #define CLK_SOURCE_SDMMC2 0x154
 164 #define CLK_SOURCE_SDMMC3 0x1bc
 165 #define CLK_SOURCE_SDMMC4 0x164
 166 #define CLK_SOURCE_VDE 0x1c8
 167 #define CLK_SOURCE_CSITE 0x1d4
 168 #define CLK_SOURCE_LA 0x1f8
 169 #define CLK_SOURCE_OWR 0x1cc
 170 #define CLK_SOURCE_NOR 0x1d0
 171 #define CLK_SOURCE_MIPI 0x174
 172 #define CLK_SOURCE_I2C1 0x124
 173 #define CLK_SOURCE_I2C2 0x198
 174 #define CLK_SOURCE_I2C3 0x1b8
 175 #define CLK_SOURCE_I2C4 0x3c4
 176 #define CLK_SOURCE_I2C5 0x128
 177 #define CLK_SOURCE_UARTA 0x178
 178 #define CLK_SOURCE_UARTB 0x17c
 179 #define CLK_SOURCE_UARTC 0x1a0
 180 #define CLK_SOURCE_UARTD 0x1c0
 181 #define CLK_SOURCE_UARTE 0x1c4
 182 #define CLK_SOURCE_VI 0x148
 183 #define CLK_SOURCE_VI_SENSOR 0x1a8
 184 #define CLK_SOURCE_3D 0x158
 185 #define CLK_SOURCE_3D2 0x3b0
 186 #define CLK_SOURCE_2D 0x15c
 187 #define CLK_SOURCE_EPP 0x16c
 188 #define CLK_SOURCE_MPE 0x170
 189 #define CLK_SOURCE_HOST1X 0x180
 190 #define CLK_SOURCE_CVE 0x140
 191 #define CLK_SOURCE_TVO 0x188
 192 #define CLK_SOURCE_DTV 0x1dc
 193 #define CLK_SOURCE_HDMI 0x18c
 194 #define CLK_SOURCE_TVDAC 0x194
 195 #define CLK_SOURCE_DISP1 0x138
 196 #define CLK_SOURCE_DISP2 0x13c
 197 #define CLK_SOURCE_DSIB 0xd0
 198 #define CLK_SOURCE_TSENSOR 0x3b8
 199 #define CLK_SOURCE_ACTMON 0x3e8
 200 #define CLK_SOURCE_EXTERN1 0x3ec
 201 #define CLK_SOURCE_EXTERN2 0x3f0
 202 #define CLK_SOURCE_EXTERN3 0x3f4
 203 #define CLK_SOURCE_I2CSLOW 0x3fc
 204 #define CLK_SOURCE_SE 0x42c
 205 #define CLK_SOURCE_MSELECT 0x3b4
 206 #define CLK_SOURCE_EMC 0x19c
 207
 208 #define AUDIO_SYNC_DOUBLER 0x49c
 209
 210 #define PMC_CTRL 0
 211 #define PMC_CTRL_BLINK_ENB 7
 212
 213 #define PMC_DPD_PADS_ORIDE 0x1c
 214 #define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
 215 #define PMC_BLINK_TIMER 0x40
 216
 217 #define UTMIP_PLL_CFG2 0x488
 218 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
 219 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
 220 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
 221 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
 222 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
 223
 224 #define UTMIP_PLL_CFG1 0x484
 225 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
 226 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
 227 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
 228 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
 229 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
 230
 231 /* Tegra CPU clock and reset control regs */
 232 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX          0x4c
 233 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET      0x340
 234 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR      0x344
 235 #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR    0x34c
 236 #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
 237
 238 #define CPU_CLOCK(cpu)  (0x1 << (8 + cpu))
 239 #define CPU_RESET(cpu)  (0x1111ul << (cpu))
 240
 241 #define CLK_RESET_CCLK_BURST    0x20
 242 #define CLK_RESET_CCLK_DIVIDER  0x24
 243 #define CLK_RESET_PLLX_BASE     0xe0
 244 #define CLK_RESET_PLLX_MISC     0xe4
 245
 246 #define CLK_RESET_SOURCE_CSITE  0x1d4
 247
 248 #define CLK_RESET_CCLK_BURST_POLICY_SHIFT       28
 249 #define CLK_RESET_CCLK_RUN_POLICY_SHIFT         4
 250 #define CLK_RESET_CCLK_IDLE_POLICY_SHIFT        0
 251 #define CLK_RESET_CCLK_IDLE_POLICY              1
 252 #define CLK_RESET_CCLK_RUN_POLICY               2
 253 #define CLK_RESET_CCLK_BURST_POLICY_PLLX        8
 254
 255 /* PLLM override registers */
 256 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
 257
 258 #ifdef CONFIG_PM_SLEEP
 259 static struct cpu_clk_suspend_context {
 260         u32 pllx_misc;
 261         u32 pllx_base;
 262
 263         u32 cpu_burst;
 264         u32 clk_csite_src;
 265         u32 cclk_divider;
 266 } tegra30_cpu_clk_sctx;
 267 #endif
 268
 269 static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
 270
 271 static void __iomem *clk_base;
 272 static void __iomem *pmc_base;
 273 static unsigned long input_freq;
 274
 275 static DEFINE_SPINLOCK(clk_doubler_lock);
 276 static DEFINE_SPINLOCK(clk_out_lock);
 277 static DEFINE_SPINLOCK(pll_div_lock);
 278 static DEFINE_SPINLOCK(cml_lock);
 279 static DEFINE_SPINLOCK(pll_d_lock);
 280 static DEFINE_SPINLOCK(sysrate_lock);
 281
 282 #define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
 283                             _clk_num, _regs, _gate_flags, _clk_id)      \
 284         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 285                         30, 2, 0, 0, 8, 1, 0, _regs, _clk_num,          \
 286                         periph_clk_enb_refcnt, _gate_flags, _clk_id)
 287
 288 #define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
 289                             _clk_num, _regs, _gate_flags, _clk_id)      \
 290         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 291                         30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,     \
 292                         _regs, _clk_num, periph_clk_enb_refcnt,         \
 293                         _gate_flags, _clk_id)
 294
 295 #define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
 296                              _clk_num, _regs, _gate_flags, _clk_id)     \
 297         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 298                         29, 3, 0, 0, 8, 1, 0, _regs, _clk_num,          \
 299                         periph_clk_enb_refcnt, _gate_flags, _clk_id)
 300
 301 #define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
 302                             _clk_num, _regs, _gate_flags, _clk_id)      \
 303         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 304                         30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,    \
 305                         _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
 306                         _clk_id)
 307
 308 #define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
 309                              _clk_num, _regs, _clk_id)                  \
 310         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 311                         30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs,  \
 312                         _clk_num, periph_clk_enb_refcnt, 0, _clk_id)
 313
 314 #define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
 315                               _mux_shift, _mux_width, _clk_num, _regs,  \
 316                               _gate_flags, _clk_id)                     \
 317         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 318                         _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs,   \
 319                         _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
 320                         _clk_id)
 321
 322 /*
 323  * IDs assigned here must be in sync with DT bindings definition
 324  * for Tegra30 clocks.
 325  */
 326 enum tegra30_clk {
 327         cpu, rtc = 4, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1, ndflash,
 328         sdmmc1, sdmmc4, pwm = 17, i2s2, epp, gr2d = 21, usbd, isp, gr3d,
 329         disp2 = 26, disp1, host1x, vcp, i2s0, cop_cache, mc, ahbdma, apbdma,
 330         kbc = 36, statmon, pmc, kfuse = 40, sbc1, nor, sbc2 = 44, sbc3 = 46,
 331         i2c5, dsia, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
 332         usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
 333         pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow,
 334         dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92,
 335         cdev2, cdev1, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
 336         i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x,
 337         atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x,
 338         spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda,
 339         se = 127, hda2hdmi, sata_cold, uartb = 160, vfir, spdif_in, spdif_out,
 340         vi, vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2,
 341         clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p,
 342         pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0,
 343         pll_d, pll_d_out0, pll_d2, pll_d2_out0, pll_u, pll_x, pll_x_out0, pll_e,
 344         spdif_in_sync, i2s0_sync, i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync,
 345         vimclk_sync, audio0, audio1, audio2, audio3, audio4, spdif, clk_out_1,
 346         clk_out_2, clk_out_3, sclk, blink, cclk_g, cclk_lp, twd, cml0, cml1,
 347         hclk, pclk, clk_out_1_mux = 300, clk_max
 348 };
 349
 350 static struct clk *clks[clk_max];
 351 static struct clk_onecell_data clk_data;
 352
 353 /*
 354  * Structure defining the fields for USB UTMI clocks Parameters.
 355  */
 356 struct utmi_clk_param {
 357         /* Oscillator Frequency in KHz */
 358         u32 osc_frequency;
 359         /* UTMIP PLL Enable Delay Count  */
 360         u8 enable_delay_count;
 361         /* UTMIP PLL Stable count */
 362         u8 stable_count;
 363         /*  UTMIP PLL Active delay count */
 364         u8 active_delay_count;
 365         /* UTMIP PLL Xtal frequency count */
 366         u8 xtal_freq_count;
 367 };
 368
 369 static const struct utmi_clk_param utmi_parameters[] = {
 370 /*      OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
 371         {13000000,     0x02,       0x33,       0x05,       0x7F},
 372         {19200000,     0x03,       0x4B,       0x06,       0xBB},
 373         {12000000,     0x02,       0x2F,       0x04,       0x76},
 374         {26000000,     0x04,       0x66,       0x09,       0xFE},
 375         {16800000,     0x03,       0x41,       0x0A,       0xA4},
 376 };
 377
 378 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
 379         { 12000000, 1040000000, 520,  6, 0, 8},
 380         { 13000000, 1040000000, 480,  6, 0, 8},
 381         { 16800000, 1040000000, 495,  8, 0, 8}, /* actual: 1039.5 MHz */
 382         { 19200000, 1040000000, 325,  6, 0, 6},
 383         { 26000000, 1040000000, 520, 13, 0, 8},
 384
 385         { 12000000, 832000000, 416,  6, 0, 8},
 386         { 13000000, 832000000, 832, 13, 0, 8},
 387         { 16800000, 832000000, 396,  8, 0, 8},  /* actual: 831.6 MHz */
 388         { 19200000, 832000000, 260,  6, 0, 8},
 389         { 26000000, 832000000, 416, 13, 0, 8},
 390
 391         { 12000000, 624000000, 624, 12, 0, 8},
 392         { 13000000, 624000000, 624, 13, 0, 8},
 393         { 16800000, 600000000, 520, 14, 0, 8},
 394         { 19200000, 624000000, 520, 16, 0, 8},
 395         { 26000000, 624000000, 624, 26, 0, 8},
 396
 397         { 12000000, 600000000, 600, 12, 0, 8},
 398         { 13000000, 600000000, 600, 13, 0, 8},
 399         { 16800000, 600000000, 500, 14, 0, 8},
 400         { 19200000, 600000000, 375, 12, 0, 6},
 401         { 26000000, 600000000, 600, 26, 0, 8},
 402
 403         { 12000000, 520000000, 520, 12, 0, 8},
 404         { 13000000, 520000000, 520, 13, 0, 8},
 405         { 16800000, 520000000, 495, 16, 0, 8},  /* actual: 519.75 MHz */
 406         { 19200000, 520000000, 325, 12, 0, 6},
 407         { 26000000, 520000000, 520, 26, 0, 8},
 408
 409         { 12000000, 416000000, 416, 12, 0, 8},
 410         { 13000000, 416000000, 416, 13, 0, 8},
 411         { 16800000, 416000000, 396, 16, 0, 8},  /* actual: 415.8 MHz */
 412         { 19200000, 416000000, 260, 12, 0, 6},
 413         { 26000000, 416000000, 416, 26, 0, 8},
 414         { 0, 0, 0, 0, 0, 0 },
 415 };
 416
 417 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
 418         { 12000000, 666000000, 666, 12, 0, 8},
 419         { 13000000, 666000000, 666, 13, 0, 8},
 420         { 16800000, 666000000, 555, 14, 0, 8},
 421         { 19200000, 666000000, 555, 16, 0, 8},
 422         { 26000000, 666000000, 666, 26, 0, 8},
 423         { 12000000, 600000000, 600, 12, 0, 8},
 424         { 13000000, 600000000, 600, 13, 0, 8},
 425         { 16800000, 600000000, 500, 14, 0, 8},
 426         { 19200000, 600000000, 375, 12, 0, 6},
 427         { 26000000, 600000000, 600, 26, 0, 8},
 428         { 0, 0, 0, 0, 0, 0 },
 429 };
 430
 431 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
 432         { 12000000, 216000000, 432, 12, 1, 8},
 433         { 13000000, 216000000, 432, 13, 1, 8},
 434         { 16800000, 216000000, 360, 14, 1, 8},
 435         { 19200000, 216000000, 360, 16, 1, 8},
 436         { 26000000, 216000000, 432, 26, 1, 8},
 437         { 0, 0, 0, 0, 0, 0 },
 438 };
 439
 440 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
 441         { 9600000, 564480000, 294, 5, 0, 4},
 442         { 9600000, 552960000, 288, 5, 0, 4},
 443         { 9600000, 24000000,  5,   2, 0, 1},
 444
 445         { 28800000, 56448000, 49, 25, 0, 1},
 446         { 28800000, 73728000, 64, 25, 0, 1},
 447         { 28800000, 24000000,  5,  6, 0, 1},
 448         { 0, 0, 0, 0, 0, 0 },
 449 };
 450
 451 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
 452         { 12000000, 216000000, 216, 12, 0, 4},
 453         { 13000000, 216000000, 216, 13, 0, 4},
 454         { 16800000, 216000000, 180, 14, 0, 4},
 455         { 19200000, 216000000, 180, 16, 0, 4},
 456         { 26000000, 216000000, 216, 26, 0, 4},
 457
 458         { 12000000, 594000000, 594, 12, 0, 8},
 459         { 13000000, 594000000, 594, 13, 0, 8},
 460         { 16800000, 594000000, 495, 14, 0, 8},
 461         { 19200000, 594000000, 495, 16, 0, 8},
 462         { 26000000, 594000000, 594, 26, 0, 8},
 463
 464         { 12000000, 1000000000, 1000, 12, 0, 12},
 465         { 13000000, 1000000000, 1000, 13, 0, 12},
 466         { 19200000, 1000000000, 625,  12, 0, 8},
 467         { 26000000, 1000000000, 1000, 26, 0, 12},
 468
 469         { 0, 0, 0, 0, 0, 0 },
 470 };
 471
 472 static struct pdiv_map pllu_p[] = {
 473         { .pdiv = 1, .hw_val = 1 },
 474         { .pdiv = 2, .hw_val = 0 },
 475         { .pdiv = 0, .hw_val = 0 },
 476 };
 477
 478 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
 479         { 12000000, 480000000, 960, 12, 0, 12},
 480         { 13000000, 480000000, 960, 13, 0, 12},
 481         { 16800000, 480000000, 400, 7,  0, 5},
 482         { 19200000, 480000000, 200, 4,  0, 3},
 483         { 26000000, 480000000, 960, 26, 0, 12},
 484         { 0, 0, 0, 0, 0, 0 },
 485 };
 486
 487 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
 488         /* 1.7 GHz */
 489         { 12000000, 1700000000, 850,  6,  0, 8},
 490         { 13000000, 1700000000, 915,  7,  0, 8},        /* actual: 1699.2 MHz */
 491         { 16800000, 1700000000, 708,  7,  0, 8},        /* actual: 1699.2 MHz */
 492         { 19200000, 1700000000, 885,  10, 0, 8},        /* actual: 1699.2 MHz */
 493         { 26000000, 1700000000, 850,  13, 0, 8},
 494
 495         /* 1.6 GHz */
 496         { 12000000, 1600000000, 800,  6,  0, 8},
 497         { 13000000, 1600000000, 738,  6,  0, 8},        /* actual: 1599.0 MHz */
 498         { 16800000, 1600000000, 857,  9,  0, 8},        /* actual: 1599.7 MHz */
 499         { 19200000, 1600000000, 500,  6,  0, 8},
 500         { 26000000, 1600000000, 800,  13, 0, 8},
 501
 502         /* 1.5 GHz */
 503         { 12000000, 1500000000, 750,  6,  0, 8},
 504         { 13000000, 1500000000, 923,  8,  0, 8},        /* actual: 1499.8 MHz */
 505         { 16800000, 1500000000, 625,  7,  0, 8},
 506         { 19200000, 1500000000, 625,  8,  0, 8},
 507         { 26000000, 1500000000, 750,  13, 0, 8},
 508
 509         /* 1.4 GHz */
 510         { 12000000, 1400000000, 700,  6,  0, 8},
 511         { 13000000, 1400000000, 969,  9,  0, 8},        /* actual: 1399.7 MHz */
 512         { 16800000, 1400000000, 1000, 12, 0, 8},
 513         { 19200000, 1400000000, 875,  12, 0, 8},
 514         { 26000000, 1400000000, 700,  13, 0, 8},
 515
 516         /* 1.3 GHz */
 517         { 12000000, 1300000000, 975,  9,  0, 8},
 518         { 13000000, 1300000000, 1000, 10, 0, 8},
 519         { 16800000, 1300000000, 928,  12, 0, 8},        /* actual: 1299.2 MHz */
 520         { 19200000, 1300000000, 812,  12, 0, 8},        /* actual: 1299.2 MHz */
 521         { 26000000, 1300000000, 650,  13, 0, 8},
 522
 523         /* 1.2 GHz */
 524         { 12000000, 1200000000, 1000, 10, 0, 8},
 525         { 13000000, 1200000000, 923,  10, 0, 8},        /* actual: 1199.9 MHz */
 526         { 16800000, 1200000000, 1000, 14, 0, 8},
 527         { 19200000, 1200000000, 1000, 16, 0, 8},
 528         { 26000000, 1200000000, 600,  13, 0, 8},
 529
 530         /* 1.1 GHz */
 531         { 12000000, 1100000000, 825,  9,  0, 8},
 532         { 13000000, 1100000000, 846,  10, 0, 8},        /* actual: 1099.8 MHz */
 533         { 16800000, 1100000000, 982,  15, 0, 8},        /* actual: 1099.8 MHz */
 534         { 19200000, 1100000000, 859,  15, 0, 8},        /* actual: 1099.5 MHz */
 535         { 26000000, 1100000000, 550,  13, 0, 8},
 536
 537         /* 1 GHz */
 538         { 12000000, 1000000000, 1000, 12, 0, 8},
 539         { 13000000, 1000000000, 1000, 13, 0, 8},
 540         { 16800000, 1000000000, 833,  14, 0, 8},        /* actual: 999.6 MHz */
 541         { 19200000, 1000000000, 625,  12, 0, 8},
 542         { 26000000, 1000000000, 1000, 26, 0, 8},
 543
 544         { 0, 0, 0, 0, 0, 0 },
 545 };
 546
 547 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
 548         /* PLLE special case: use cpcon field to store cml divider value */
 549         { 12000000,  100000000, 150, 1,  18, 11},
 550         { 216000000, 100000000, 200, 18, 24, 13},
 551         { 0, 0, 0, 0, 0, 0 },
 552 };
 553
 554 /* PLL parameters */
 555 static struct tegra_clk_pll_params pll_c_params = {
 556         .input_min = 2000000,
 557         .input_max = 31000000,
 558         .cf_min = 1000000,
 559         .cf_max = 6000000,
 560         .vco_min = 20000000,
 561         .vco_max = 1400000000,
 562         .base_reg = PLLC_BASE,
 563         .misc_reg = PLLC_MISC,
 564         .lock_mask = PLL_BASE_LOCK,
 565         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 566         .lock_delay = 300,
 567 };
 568
 569 static struct div_nmp pllm_nmp = {
 570         .divn_shift = 8,
 571         .divn_width = 10,
 572         .override_divn_shift = 5,
 573         .divm_shift = 0,
 574         .divm_width = 5,
 575         .override_divm_shift = 0,
 576         .divp_shift = 20,
 577         .divp_width = 3,
 578         .override_divp_shift = 15,
 579 };
 580
 581 static struct tegra_clk_pll_params pll_m_params = {
 582         .input_min = 2000000,
 583         .input_max = 31000000,
 584         .cf_min = 1000000,
 585         .cf_max = 6000000,
 586         .vco_min = 20000000,
 587         .vco_max = 1200000000,
 588         .base_reg = PLLM_BASE,
 589         .misc_reg = PLLM_MISC,
 590         .lock_mask = PLL_BASE_LOCK,
 591         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 592         .lock_delay = 300,
 593         .div_nmp = &pllm_nmp,
 594         .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
 595         .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,
 596 };
 597
 598 static struct tegra_clk_pll_params pll_p_params = {
 599         .input_min = 2000000,
 600         .input_max = 31000000,
 601         .cf_min = 1000000,
 602         .cf_max = 6000000,
 603         .vco_min = 20000000,
 604         .vco_max = 1400000000,
 605         .base_reg = PLLP_BASE,
 606         .misc_reg = PLLP_MISC,
 607         .lock_mask = PLL_BASE_LOCK,
 608         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 609         .lock_delay = 300,
 610 };
 611
 612 static struct tegra_clk_pll_params pll_a_params = {
 613         .input_min = 2000000,
 614         .input_max = 31000000,
 615         .cf_min = 1000000,
 616         .cf_max = 6000000,
 617         .vco_min = 20000000,
 618         .vco_max = 1400000000,
 619         .base_reg = PLLA_BASE,
 620         .misc_reg = PLLA_MISC,
 621         .lock_mask = PLL_BASE_LOCK,
 622         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 623         .lock_delay = 300,
 624 };
 625
 626 static struct tegra_clk_pll_params pll_d_params = {
 627         .input_min = 2000000,
 628         .input_max = 40000000,
 629         .cf_min = 1000000,
 630         .cf_max = 6000000,
 631         .vco_min = 40000000,
 632         .vco_max = 1000000000,
 633         .base_reg = PLLD_BASE,
 634         .misc_reg = PLLD_MISC,
 635         .lock_mask = PLL_BASE_LOCK,
 636         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 637         .lock_delay = 1000,
 638 };
 639
 640 static struct tegra_clk_pll_params pll_d2_params = {
 641         .input_min = 2000000,
 642         .input_max = 40000000,
 643         .cf_min = 1000000,
 644         .cf_max = 6000000,
 645         .vco_min = 40000000,
 646         .vco_max = 1000000000,
 647         .base_reg = PLLD2_BASE,
 648         .misc_reg = PLLD2_MISC,
 649         .lock_mask = PLL_BASE_LOCK,
 650         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 651         .lock_delay = 1000,
 652 };
 653
 654 static struct tegra_clk_pll_params pll_u_params = {
 655         .input_min = 2000000,
 656         .input_max = 40000000,
 657         .cf_min = 1000000,
 658         .cf_max = 6000000,
 659         .vco_min = 48000000,
 660         .vco_max = 960000000,
 661         .base_reg = PLLU_BASE,
 662         .misc_reg = PLLU_MISC,
 663         .lock_mask = PLL_BASE_LOCK,
 664         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 665         .lock_delay = 1000,
 666         .pdiv_tohw = pllu_p,
 667 };
 668
 669 static struct tegra_clk_pll_params pll_x_params = {
 670         .input_min = 2000000,
 671         .input_max = 31000000,
 672         .cf_min = 1000000,
 673         .cf_max = 6000000,
 674         .vco_min = 20000000,
 675         .vco_max = 1700000000,
 676         .base_reg = PLLX_BASE,
 677         .misc_reg = PLLX_MISC,
 678         .lock_mask = PLL_BASE_LOCK,
 679         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 680         .lock_delay = 300,
 681 };
 682
 683 static struct tegra_clk_pll_params pll_e_params = {
 684         .input_min = 12000000,
 685         .input_max = 216000000,
 686         .cf_min = 12000000,
 687         .cf_max = 12000000,
 688         .vco_min = 1200000000,
 689         .vco_max = 2400000000U,
 690         .base_reg = PLLE_BASE,
 691         .misc_reg = PLLE_MISC,
 692         .lock_mask = PLLE_MISC_LOCK,
 693         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
 694         .lock_delay = 300,
 695 };
 696
 697 /* Peripheral clock registers */
 698 static struct tegra_clk_periph_regs periph_l_regs = {
 699         .enb_reg = CLK_OUT_ENB_L,
 700         .enb_set_reg = CLK_OUT_ENB_SET_L,
 701         .enb_clr_reg = CLK_OUT_ENB_CLR_L,
 702         .rst_reg = RST_DEVICES_L,
 703         .rst_set_reg = RST_DEVICES_SET_L,
 704         .rst_clr_reg = RST_DEVICES_CLR_L,
 705 };
 706
 707 static struct tegra_clk_periph_regs periph_h_regs = {
 708         .enb_reg = CLK_OUT_ENB_H,
 709         .enb_set_reg = CLK_OUT_ENB_SET_H,
 710         .enb_clr_reg = CLK_OUT_ENB_CLR_H,
 711         .rst_reg = RST_DEVICES_H,
 712         .rst_set_reg = RST_DEVICES_SET_H,
 713         .rst_clr_reg = RST_DEVICES_CLR_H,
 714 };
 715
 716 static struct tegra_clk_periph_regs periph_u_regs = {
 717         .enb_reg = CLK_OUT_ENB_U,
 718         .enb_set_reg = CLK_OUT_ENB_SET_U,
 719         .enb_clr_reg = CLK_OUT_ENB_CLR_U,
 720         .rst_reg = RST_DEVICES_U,
 721         .rst_set_reg = RST_DEVICES_SET_U,
 722         .rst_clr_reg = RST_DEVICES_CLR_U,
 723 };
 724
 725 static struct tegra_clk_periph_regs periph_v_regs = {
 726         .enb_reg = CLK_OUT_ENB_V,
 727         .enb_set_reg = CLK_OUT_ENB_SET_V,
 728         .enb_clr_reg = CLK_OUT_ENB_CLR_V,
 729         .rst_reg = RST_DEVICES_V,
 730         .rst_set_reg = RST_DEVICES_SET_V,
 731         .rst_clr_reg = RST_DEVICES_CLR_V,
 732 };
 733
 734 static struct tegra_clk_periph_regs periph_w_regs = {
 735         .enb_reg = CLK_OUT_ENB_W,
 736         .enb_set_reg = CLK_OUT_ENB_SET_W,
 737         .enb_clr_reg = CLK_OUT_ENB_CLR_W,
 738         .rst_reg = RST_DEVICES_W,
 739         .rst_set_reg = RST_DEVICES_SET_W,
 740         .rst_clr_reg = RST_DEVICES_CLR_W,
 741 };
 742
 743 static void tegra30_clk_measure_input_freq(void)
 744 {
 745         u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
 746         u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK;
 747         u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
 748
 749         switch (auto_clk_control) {
 750         case OSC_CTRL_OSC_FREQ_12MHZ:
 751                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 752                 input_freq = 12000000;
 753                 break;
 754         case OSC_CTRL_OSC_FREQ_13MHZ:
 755                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 756                 input_freq = 13000000;
 757                 break;
 758         case OSC_CTRL_OSC_FREQ_19_2MHZ:
 759                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 760                 input_freq = 19200000;
 761                 break;
 762         case OSC_CTRL_OSC_FREQ_26MHZ:
 763                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 764                 input_freq = 26000000;
 765                 break;
 766         case OSC_CTRL_OSC_FREQ_16_8MHZ:
 767                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 768                 input_freq = 16800000;
 769                 break;
 770         case OSC_CTRL_OSC_FREQ_38_4MHZ:
 771                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
 772                 input_freq = 38400000;
 773                 break;
 774         case OSC_CTRL_OSC_FREQ_48MHZ:
 775                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
 776                 input_freq = 48000000;
 777                 break;
 778         default:
 779                 pr_err("Unexpected auto clock control value %d",
 780                         auto_clk_control);
 781                 BUG();
 782                 return;
 783         }
 784 }
 785
 786 static unsigned int tegra30_get_pll_ref_div(void)
 787 {
 788         u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
 789                                         OSC_CTRL_PLL_REF_DIV_MASK;
 790
 791         switch (pll_ref_div) {
 792         case OSC_CTRL_PLL_REF_DIV_1:
 793                 return 1;
 794         case OSC_CTRL_PLL_REF_DIV_2:
 795                 return 2;
 796         case OSC_CTRL_PLL_REF_DIV_4:
 797                 return 4;
 798         default:
 799                 pr_err("Invalid pll ref divider %d", pll_ref_div);
 800                 BUG();
 801         }
 802         return 0;
 803 }
 804
 805 static void tegra30_utmi_param_configure(void)
 806 {
 807         u32 reg;
 808         int i;
 809
 810         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
 811                 if (input_freq == utmi_parameters[i].osc_frequency)
 812                         break;
 813         }
 814
 815         if (i >= ARRAY_SIZE(utmi_parameters)) {
 816                 pr_err("%s: Unexpected input rate %lu\n", __func__, input_freq);
 817                 return;
 818         }
 819
 820         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
 821
 822         /* Program UTMIP PLL stable and active counts */
 823         reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
 824         reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
 825                         utmi_parameters[i].stable_count);
 826
 827         reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
 828
 829         reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
 830                         utmi_parameters[i].active_delay_count);
 831
 832         /* Remove power downs from UTMIP PLL control bits */
 833         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
 834         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
 835         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
 836
 837         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
 838
 839         /* Program UTMIP PLL delay and oscillator frequency counts */
 840         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
 841         reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
 842
 843         reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
 844                 utmi_parameters[i].enable_delay_count);
 845
 846         reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
 847         reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
 848                 utmi_parameters[i].xtal_freq_count);
 849
 850         /* Remove power downs from UTMIP PLL control bits */
 851         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
 852         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
 853         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
 854
 855         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
 856 }
 857
 858 static const char *pll_e_parents[] = {"pll_ref", "pll_p"};
 859
 860 static void __init tegra30_pll_init(void)
 861 {
 862         struct clk *clk;
 863
 864         /* PLLC */
 865         clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
 866                             0, &pll_c_params,
 867                             TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
 868                             pll_c_freq_table, NULL);
 869         clk_register_clkdev(clk, "pll_c", NULL);
 870         clks[pll_c] = clk;
 871
 872         /* PLLC_OUT1 */
 873         clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
 874                                 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
 875                                 8, 8, 1, NULL);
 876         clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
 877                                 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
 878                                 0, NULL);
 879         clk_register_clkdev(clk, "pll_c_out1", NULL);
 880         clks[pll_c_out1] = clk;
 881
 882         /* PLLP */
 883         clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc_base, 0,
 884                             408000000, &pll_p_params,
 885                             TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON |
 886                             TEGRA_PLL_USE_LOCK, pll_p_freq_table, NULL);
 887         clk_register_clkdev(clk, "pll_p", NULL);
 888         clks[pll_p] = clk;
 889
 890         /* PLLP_OUT1 */
 891         clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
 892                                 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
 893                                 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1,
 894                                 &pll_div_lock);
 895         clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
 896                                 clk_base + PLLP_OUTA, 1, 0,
 897                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
 898                                 &pll_div_lock);
 899         clk_register_clkdev(clk, "pll_p_out1", NULL);
 900         clks[pll_p_out1] = clk;
 901
 902         /* PLLP_OUT2 */
 903         clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
 904                                 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
 905                                 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
 906                                 &pll_div_lock);
 907         clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
 908                                 clk_base + PLLP_OUTA, 17, 16,
 909                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
 910                                 &pll_div_lock);
 911         clk_register_clkdev(clk, "pll_p_out2", NULL);
 912         clks[pll_p_out2] = clk;
 913
 914         /* PLLP_OUT3 */
 915         clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
 916                                 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
 917                                 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1,
 918                                 &pll_div_lock);
 919         clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
 920                                 clk_base + PLLP_OUTB, 1, 0,
 921                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
 922                                 &pll_div_lock);
 923         clk_register_clkdev(clk, "pll_p_out3", NULL);
 924         clks[pll_p_out3] = clk;
 925
 926         /* PLLP_OUT4 */
 927         clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
 928                                 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
 929                                 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
 930                                 &pll_div_lock);
 931         clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
 932                                 clk_base + PLLP_OUTB, 17, 16,
 933                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
 934                                 &pll_div_lock);
 935         clk_register_clkdev(clk, "pll_p_out4", NULL);
 936         clks[pll_p_out4] = clk;
 937
 938         /* PLLM */
 939         clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
 940                             CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0,
 941                             &pll_m_params, TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
 942                             TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
 943                             pll_m_freq_table, NULL);
 944         clk_register_clkdev(clk, "pll_m", NULL);
 945         clks[pll_m] = clk;
 946
 947         /* PLLM_OUT1 */
 948         clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
 949                                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
 950                                 8, 8, 1, NULL);
 951         clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
 952                                 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
 953                                 CLK_SET_RATE_PARENT, 0, NULL);
 954         clk_register_clkdev(clk, "pll_m_out1", NULL);
 955         clks[pll_m_out1] = clk;
 956
 957         /* PLLX */
 958         clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
 959                             0, &pll_x_params, TEGRA_PLL_HAS_CPCON |
 960                             TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
 961                             pll_x_freq_table, NULL);
 962         clk_register_clkdev(clk, "pll_x", NULL);
 963         clks[pll_x] = clk;
 964
 965         /* PLLX_OUT0 */
 966         clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
 967                                         CLK_SET_RATE_PARENT, 1, 2);
 968         clk_register_clkdev(clk, "pll_x_out0", NULL);
 969         clks[pll_x_out0] = clk;
 970
 971         /* PLLU */
 972         clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
 973                             0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON |
 974                             TEGRA_PLL_SET_LFCON,
 975                             pll_u_freq_table,
 976                             NULL);
 977         clk_register_clkdev(clk, "pll_u", NULL);
 978         clks[pll_u] = clk;
 979
 980         tegra30_utmi_param_configure();
 981
 982         /* PLLD */
 983         clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
 984                             0, &pll_d_params, TEGRA_PLL_HAS_CPCON |
 985                             TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
 986                             pll_d_freq_table, &pll_d_lock);
 987         clk_register_clkdev(clk, "pll_d", NULL);
 988         clks[pll_d] = clk;
 989
 990         /* PLLD_OUT0 */
 991         clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
 992                                         CLK_SET_RATE_PARENT, 1, 2);
 993         clk_register_clkdev(clk, "pll_d_out0", NULL);
 994         clks[pll_d_out0] = clk;
 995
 996         /* PLLD2 */
 997         clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
 998                             0, &pll_d2_params, TEGRA_PLL_HAS_CPCON |
 999                             TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
1000                             pll_d_freq_table, NULL);
1001         clk_register_clkdev(clk, "pll_d2", NULL);
1002         clks[pll_d2] = clk;
1003
1004         /* PLLD2_OUT0 */
1005         clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1006                                         CLK_SET_RATE_PARENT, 1, 2);
1007         clk_register_clkdev(clk, "pll_d2_out0", NULL);
1008         clks[pll_d2_out0] = clk;
1009
1010         /* PLLA */
1011         clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc_base,
1012                             0, 0, &pll_a_params, TEGRA_PLL_HAS_CPCON |
1013                             TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL);
1014         clk_register_clkdev(clk, "pll_a", NULL);
1015         clks[pll_a] = clk;
1016
1017         /* PLLA_OUT0 */
1018         clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
1019                                 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1020                                 8, 8, 1, NULL);
1021         clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
1022                                 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
1023                                 CLK_SET_RATE_PARENT, 0, NULL);
1024         clk_register_clkdev(clk, "pll_a_out0", NULL);
1025         clks[pll_a_out0] = clk;
1026
1027         /* PLLE */
1028         clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
1029                                ARRAY_SIZE(pll_e_parents),
1030                                CLK_SET_RATE_NO_REPARENT,
1031                                clk_base + PLLE_AUX, 2, 1, 0, NULL);
1032         clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
1033                              CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params,
1034                              TEGRA_PLLE_CONFIGURE, pll_e_freq_table, NULL);
1035         clk_register_clkdev(clk, "pll_e", NULL);
1036         clks[pll_e] = clk;
1037 }
1038
1039 static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
1040         "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",};
1041 static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
1042                                           "clk_m_div4", "extern1", };
1043 static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
1044                                           "clk_m_div4", "extern2", };
1045 static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
1046                                           "clk_m_div4", "extern3", };
1047
1048 static void __init tegra30_audio_clk_init(void)
1049 {
1050         struct clk *clk;
1051
1052         /* spdif_in_sync */
1053         clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000,
1054                                              24000000);
1055         clk_register_clkdev(clk, "spdif_in_sync", NULL);
1056         clks[spdif_in_sync] = clk;
1057
1058         /* i2s0_sync */
1059         clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000);
1060         clk_register_clkdev(clk, "i2s0_sync", NULL);
1061         clks[i2s0_sync] = clk;
1062
1063         /* i2s1_sync */
1064         clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000);
1065         clk_register_clkdev(clk, "i2s1_sync", NULL);
1066         clks[i2s1_sync] = clk;
1067
1068         /* i2s2_sync */
1069         clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000);
1070         clk_register_clkdev(clk, "i2s2_sync", NULL);
1071         clks[i2s2_sync] = clk;
1072
1073         /* i2s3_sync */
1074         clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000);
1075         clk_register_clkdev(clk, "i2s3_sync", NULL);
1076         clks[i2s3_sync] = clk;
1077
1078         /* i2s4_sync */
1079         clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000);
1080         clk_register_clkdev(clk, "i2s4_sync", NULL);
1081         clks[i2s4_sync] = clk;
1082
1083         /* vimclk_sync */
1084         clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000);
1085         clk_register_clkdev(clk, "vimclk_sync", NULL);
1086         clks[vimclk_sync] = clk;
1087
1088         /* audio0 */
1089         clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1090                                 ARRAY_SIZE(mux_audio_sync_clk),
1091                                 CLK_SET_RATE_NO_REPARENT,
1092                                 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL);
1093         clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
1094                                 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
1095                                 CLK_GATE_SET_TO_DISABLE, NULL);
1096         clk_register_clkdev(clk, "audio0", NULL);
1097         clks[audio0] = clk;
1098
1099         /* audio1 */
1100         clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1101                                 ARRAY_SIZE(mux_audio_sync_clk),
1102                                 CLK_SET_RATE_NO_REPARENT,
1103                                 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL);
1104         clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
1105                                 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
1106                                 CLK_GATE_SET_TO_DISABLE, NULL);
1107         clk_register_clkdev(clk, "audio1", NULL);
1108         clks[audio1] = clk;
1109
1110         /* audio2 */
1111         clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1112                                 ARRAY_SIZE(mux_audio_sync_clk),
1113                                 CLK_SET_RATE_NO_REPARENT,
1114                                 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL);
1115         clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
1116                                 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
1117                                 CLK_GATE_SET_TO_DISABLE, NULL);
1118         clk_register_clkdev(clk, "audio2", NULL);
1119         clks[audio2] = clk;
1120
1121         /* audio3 */
1122         clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1123                                 ARRAY_SIZE(mux_audio_sync_clk),
1124                                 CLK_SET_RATE_NO_REPARENT,
1125                                 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL);
1126         clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
1127                                 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
1128                                 CLK_GATE_SET_TO_DISABLE, NULL);
1129         clk_register_clkdev(clk, "audio3", NULL);
1130         clks[audio3] = clk;
1131
1132         /* audio4 */
1133         clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1134                                 ARRAY_SIZE(mux_audio_sync_clk),
1135                                 CLK_SET_RATE_NO_REPARENT,
1136                                 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL);
1137         clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
1138                                 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
1139                                 CLK_GATE_SET_TO_DISABLE, NULL);
1140         clk_register_clkdev(clk, "audio4", NULL);
1141         clks[audio4] = clk;
1142
1143         /* spdif */
1144         clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1145                                 ARRAY_SIZE(mux_audio_sync_clk),
1146                                 CLK_SET_RATE_NO_REPARENT,
1147                                 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL);
1148         clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
1149                                 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
1150                                 CLK_GATE_SET_TO_DISABLE, NULL);
1151         clk_register_clkdev(clk, "spdif", NULL);
1152         clks[spdif] = clk;
1153
1154         /* audio0_2x */
1155         clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0",
1156                                         CLK_SET_RATE_PARENT, 2, 1);
1157         clk = tegra_clk_register_divider("audio0_div", "audio0_doubler",
1158                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 0,
1159                                 &clk_doubler_lock);
1160         clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
1161                                     TEGRA_PERIPH_NO_RESET, clk_base,
1162                                     CLK_SET_RATE_PARENT, 113, &periph_v_regs,
1163                                     periph_clk_enb_refcnt);
1164         clk_register_clkdev(clk, "audio0_2x", NULL);
1165         clks[audio0_2x] = clk;
1166
1167         /* audio1_2x */
1168         clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1",
1169                                         CLK_SET_RATE_PARENT, 2, 1);
1170         clk = tegra_clk_register_divider("audio1_div", "audio1_doubler",
1171                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 0,
1172                                 &clk_doubler_lock);
1173         clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
1174                                     TEGRA_PERIPH_NO_RESET, clk_base,
1175                                     CLK_SET_RATE_PARENT, 114, &periph_v_regs,
1176                                     periph_clk_enb_refcnt);
1177         clk_register_clkdev(clk, "audio1_2x", NULL);
1178         clks[audio1_2x] = clk;
1179
1180         /* audio2_2x */
1181         clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2",
1182                                         CLK_SET_RATE_PARENT, 2, 1);
1183         clk = tegra_clk_register_divider("audio2_div", "audio2_doubler",
1184                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 0,
1185                                 &clk_doubler_lock);
1186         clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
1187                                     TEGRA_PERIPH_NO_RESET, clk_base,
1188                                     CLK_SET_RATE_PARENT, 115, &periph_v_regs,
1189                                     periph_clk_enb_refcnt);
1190         clk_register_clkdev(clk, "audio2_2x", NULL);
1191         clks[audio2_2x] = clk;
1192
1193         /* audio3_2x */
1194         clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3",
1195                                         CLK_SET_RATE_PARENT, 2, 1);
1196         clk = tegra_clk_register_divider("audio3_div", "audio3_doubler",
1197                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 0,
1198                                 &clk_doubler_lock);
1199         clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
1200                                     TEGRA_PERIPH_NO_RESET, clk_base,
1201                                     CLK_SET_RATE_PARENT, 116, &periph_v_regs,
1202                                     periph_clk_enb_refcnt);
1203         clk_register_clkdev(clk, "audio3_2x", NULL);
1204         clks[audio3_2x] = clk;
1205
1206         /* audio4_2x */
1207         clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4",
1208                                         CLK_SET_RATE_PARENT, 2, 1);
1209         clk = tegra_clk_register_divider("audio4_div", "audio4_doubler",
1210                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 0,
1211                                 &clk_doubler_lock);
1212         clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
1213                                     TEGRA_PERIPH_NO_RESET, clk_base,
1214                                     CLK_SET_RATE_PARENT, 117, &periph_v_regs,
1215                                     periph_clk_enb_refcnt);
1216         clk_register_clkdev(clk, "audio4_2x", NULL);
1217         clks[audio4_2x] = clk;
1218
1219         /* spdif_2x */
1220         clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif",
1221                                         CLK_SET_RATE_PARENT, 2, 1);
1222         clk = tegra_clk_register_divider("spdif_div", "spdif_doubler",
1223                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 0,
1224                                 &clk_doubler_lock);
1225         clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
1226                                     TEGRA_PERIPH_NO_RESET, clk_base,
1227                                     CLK_SET_RATE_PARENT, 118, &periph_v_regs,
1228                                     periph_clk_enb_refcnt);
1229         clk_register_clkdev(clk, "spdif_2x", NULL);
1230         clks[spdif_2x] = clk;
1231 }
1232
1233 static void __init tegra30_pmc_clk_init(void)
1234 {
1235         struct clk *clk;
1236
1237         /* clk_out_1 */
1238         clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1239                                ARRAY_SIZE(clk_out1_parents),
1240                                CLK_SET_RATE_NO_REPARENT,
1241                                pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1242                                &clk_out_lock);
1243         clks[clk_out_1_mux] = clk;
1244         clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
1245                                 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
1246                                 &clk_out_lock);
1247         clk_register_clkdev(clk, "extern1", "clk_out_1");
1248         clks[clk_out_1] = clk;
1249
1250         /* clk_out_2 */
1251         clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1252                                ARRAY_SIZE(clk_out2_parents),
1253                                CLK_SET_RATE_NO_REPARENT,
1254                                pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1255                                &clk_out_lock);
1256         clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
1257                                 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
1258                                 &clk_out_lock);
1259         clk_register_clkdev(clk, "extern2", "clk_out_2");
1260         clks[clk_out_2] = clk;
1261
1262         /* clk_out_3 */
1263         clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1264                                ARRAY_SIZE(clk_out3_parents),
1265                                CLK_SET_RATE_NO_REPARENT,
1266                                pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1267                                &clk_out_lock);
1268         clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
1269                                 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
1270                                 &clk_out_lock);
1271         clk_register_clkdev(clk, "extern3", "clk_out_3");
1272         clks[clk_out_3] = clk;
1273
1274         /* blink */
1275         writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1276         clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1277                                 pmc_base + PMC_DPD_PADS_ORIDE,
1278                                 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1279         clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1280                                 pmc_base + PMC_CTRL,
1281                                 PMC_CTRL_BLINK_ENB, 0, NULL);
1282         clk_register_clkdev(clk, "blink", NULL);
1283         clks[blink] = clk;
1284
1285 }
1286
1287 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1288                                         "pll_p_cclkg", "pll_p_out4_cclkg",
1289                                         "pll_p_out3_cclkg", "unused", "pll_x" };
1290 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1291                                          "pll_p_cclklp", "pll_p_out4_cclklp",
1292                                          "pll_p_out3_cclklp", "unused", "pll_x",
1293                                          "pll_x_out0" };
1294 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
1295                                       "pll_p_out3", "pll_p_out2", "unused",
1296                                       "clk_32k", "pll_m_out1" };
1297
1298 static void __init tegra30_super_clk_init(void)
1299 {
1300         struct clk *clk;
1301
1302         /*
1303          * Clock input to cclk_g divided from pll_p using
1304          * U71 divider of cclk_g.
1305          */
1306         clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",
1307                                 clk_base + SUPER_CCLKG_DIVIDER, 0,
1308                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1309         clk_register_clkdev(clk, "pll_p_cclkg", NULL);
1310
1311         /*
1312          * Clock input to cclk_g divided from pll_p_out3 using
1313          * U71 divider of cclk_g.
1314          */
1315         clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",
1316                                 clk_base + SUPER_CCLKG_DIVIDER, 0,
1317                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1318         clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);
1319
1320         /*
1321          * Clock input to cclk_g divided from pll_p_out4 using
1322          * U71 divider of cclk_g.
1323          */
1324         clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",
1325                                 clk_base + SUPER_CCLKG_DIVIDER, 0,
1326                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1327         clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
1328
1329         /* CCLKG */
1330         clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
1331                                   ARRAY_SIZE(cclk_g_parents),
1332                                   CLK_SET_RATE_PARENT,
1333                                   clk_base + CCLKG_BURST_POLICY,
1334                                   0, 4, 0, 0, NULL);
1335         clk_register_clkdev(clk, "cclk_g", NULL);
1336         clks[cclk_g] = clk;
1337
1338         /*
1339          * Clock input to cclk_lp divided from pll_p using
1340          * U71 divider of cclk_lp.
1341          */
1342         clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p",
1343                                 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1344                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1345         clk_register_clkdev(clk, "pll_p_cclklp", NULL);
1346
1347         /*
1348          * Clock input to cclk_lp divided from pll_p_out3 using
1349          * U71 divider of cclk_lp.
1350          */
1351         clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
1352                                 clk_base + SUPER_CCLKG_DIVIDER, 0,
1353                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1354         clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
1355
1356         /*
1357          * Clock input to cclk_lp divided from pll_p_out4 using
1358          * U71 divider of cclk_lp.
1359          */
1360         clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4",
1361                                 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1362                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1363         clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL);
1364
1365         /* CCLKLP */
1366         clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
1367                                   ARRAY_SIZE(cclk_lp_parents),
1368                                   CLK_SET_RATE_PARENT,
1369                                   clk_base + CCLKLP_BURST_POLICY,
1370                                   TEGRA_DIVIDER_2, 4, 8, 9,
1371                               NULL);
1372         clk_register_clkdev(clk, "cclk_lp", NULL);
1373         clks[cclk_lp] = clk;
1374
1375         /* SCLK */
1376         clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1377                                   ARRAY_SIZE(sclk_parents),
1378                                   CLK_SET_RATE_PARENT,
1379                                   clk_base + SCLK_BURST_POLICY,
1380                                   0, 4, 0, 0, NULL);
1381         clk_register_clkdev(clk, "sclk", NULL);
1382         clks[sclk] = clk;
1383
1384         /* HCLK */
1385         clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
1386                                    clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
1387                                    &sysrate_lock);
1388         clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
1389                                 clk_base + SYSTEM_CLK_RATE, 7,
1390                                 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1391         clk_register_clkdev(clk, "hclk", NULL);
1392         clks[hclk] = clk;
1393
1394         /* PCLK */
1395         clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
1396                                    clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
1397                                    &sysrate_lock);
1398         clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
1399                                 clk_base + SYSTEM_CLK_RATE, 3,
1400                                 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1401         clk_register_clkdev(clk, "pclk", NULL);
1402         clks[pclk] = clk;
1403
1404         /* twd */
1405         clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
1406                                         CLK_SET_RATE_PARENT, 1, 2);
1407         clk_register_clkdev(clk, "twd", NULL);
1408         clks[twd] = clk;
1409 }
1410
1411 static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
1412                                          "clk_m" };
1413 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
1414 static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
1415 static const char *i2s0_parents[] = { "pll_a_out0", "audio0_2x", "pll_p",
1416                                       "clk_m" };
1417 static const char *i2s1_parents[] = { "pll_a_out0", "audio1_2x", "pll_p",
1418                                       "clk_m" };
1419 static const char *i2s2_parents[] = { "pll_a_out0", "audio2_2x", "pll_p",
1420                                       "clk_m" };
1421 static const char *i2s3_parents[] = { "pll_a_out0", "audio3_2x", "pll_p",
1422                                       "clk_m" };
1423 static const char *i2s4_parents[] = { "pll_a_out0", "audio4_2x", "pll_p",
1424                                       "clk_m" };
1425 static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
1426                                            "clk_m" };
1427 static const char *spdif_in_parents[] = { "pll_p", "pll_c", "pll_m" };
1428 static const char *mux_pllpc_clk32k_clkm[] = { "pll_p", "pll_c", "clk_32k",
1429                                                "clk_m" };
1430 static const char *mux_pllpc_clkm_clk32k[] = { "pll_p", "pll_c", "clk_m",
1431                                                "clk_32k" };
1432 static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
1433 static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",
1434                                          "clk_m" };
1435 static const char *mux_pllp_clkm[] = { "pll_p", "unused", "unused", "clk_m" };
1436 static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
1437                                              "pll_a_out0", "pll_c",
1438                                              "pll_d2_out0", "clk_m" };
1439 static const char *mux_plla_clk32k_pllp_clkm_plle[] = { "pll_a_out0",
1440                                                         "clk_32k", "pll_p",
1441                                                         "clk_m", "pll_e" };
1442 static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
1443                                                   "pll_d2_out0" };
1444
1445 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1446         TEGRA_INIT_DATA_MUX("i2s0",     NULL,           "tegra30-i2s.0",        i2s0_parents,           CLK_SOURCE_I2S0,        30,     &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0),
1447         TEGRA_INIT_DATA_MUX("i2s1",     NULL,           "tegra30-i2s.1",        i2s1_parents,           CLK_SOURCE_I2S1,        11,     &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1),
1448         TEGRA_INIT_DATA_MUX("i2s2",     NULL,           "tegra30-i2s.2",        i2s2_parents,           CLK_SOURCE_I2S2,        18,     &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2),
1449         TEGRA_INIT_DATA_MUX("i2s3",     NULL,           "tegra30-i2s.3",        i2s3_parents,           CLK_SOURCE_I2S3,        101,    &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3),
1450         TEGRA_INIT_DATA_MUX("i2s4",     NULL,           "tegra30-i2s.4",        i2s4_parents,           CLK_SOURCE_I2S4,        102,    &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4),
1451         TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out",   "tegra30-spdif",        spdif_out_parents,      CLK_SOURCE_SPDIF_OUT,   10,     &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out),
1452         TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in",     "tegra30-spdif",        spdif_in_parents,       CLK_SOURCE_SPDIF_IN,    10,     &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in),
1453         TEGRA_INIT_DATA_MUX("d_audio",  "d_audio",      "tegra30-ahub",         mux_pllacp_clkm,        CLK_SOURCE_D_AUDIO,     106,    &periph_v_regs, 0, d_audio),
1454         TEGRA_INIT_DATA_MUX("dam0",     NULL,           "tegra30-dam.0",        mux_pllacp_clkm,        CLK_SOURCE_DAM0,        108,    &periph_v_regs, 0, dam0),
1455         TEGRA_INIT_DATA_MUX("dam1",     NULL,           "tegra30-dam.1",        mux_pllacp_clkm,        CLK_SOURCE_DAM1,        109,    &periph_v_regs, 0, dam1),
1456         TEGRA_INIT_DATA_MUX("dam2",     NULL,           "tegra30-dam.2",        mux_pllacp_clkm,        CLK_SOURCE_DAM2,        110,    &periph_v_regs, 0, dam2),
1457         TEGRA_INIT_DATA_MUX("hda",      "hda",          "tegra30-hda",          mux_pllpcm_clkm,        CLK_SOURCE_HDA,         125,    &periph_v_regs, 0, hda),
1458         TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda",         mux_pllpcm_clkm,        CLK_SOURCE_HDA2CODEC_2X, 111,   &periph_v_regs, 0, hda2codec_2x),
1459         TEGRA_INIT_DATA_MUX("sbc1",     NULL,           "spi_tegra.0",          mux_pllpcm_clkm,        CLK_SOURCE_SBC1,        41,     &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
1460         TEGRA_INIT_DATA_MUX("sbc2",     NULL,           "spi_tegra.1",          mux_pllpcm_clkm,        CLK_SOURCE_SBC2,        44,     &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
1461         TEGRA_INIT_DATA_MUX("sbc3",     NULL,           "spi_tegra.2",          mux_pllpcm_clkm,        CLK_SOURCE_SBC3,        46,     &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
1462         TEGRA_INIT_DATA_MUX("sbc4",     NULL,           "spi_tegra.3",          mux_pllpcm_clkm,        CLK_SOURCE_SBC4,        68,     &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
1463         TEGRA_INIT_DATA_MUX("sbc5",     NULL,           "spi_tegra.4",          mux_pllpcm_clkm,        CLK_SOURCE_SBC5,        104,    &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
1464         TEGRA_INIT_DATA_MUX("sbc6",     NULL,           "spi_tegra.5",          mux_pllpcm_clkm,        CLK_SOURCE_SBC6,        105,    &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
1465         TEGRA_INIT_DATA_MUX("sata_oob", NULL,           "tegra_sata_oob",       mux_pllpcm_clkm,        CLK_SOURCE_SATA_OOB,    123,    &periph_v_regs, TEGRA_PERIPH_ON_APB, sata_oob),
1466         TEGRA_INIT_DATA_MUX("sata",     NULL,           "tegra_sata",           mux_pllpcm_clkm,        CLK_SOURCE_SATA,        124,    &periph_v_regs, TEGRA_PERIPH_ON_APB, sata),
1467         TEGRA_INIT_DATA_MUX("ndflash",  NULL,           "tegra_nand",           mux_pllpcm_clkm,        CLK_SOURCE_NDFLASH,     13,     &periph_l_regs, TEGRA_PERIPH_ON_APB, ndflash),
1468         TEGRA_INIT_DATA_MUX("ndspeed",  NULL,           "tegra_nand_speed",     mux_pllpcm_clkm,        CLK_SOURCE_NDSPEED,     80,     &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1469         TEGRA_INIT_DATA_MUX("vfir",     NULL,           "vfir",                 mux_pllpcm_clkm,        CLK_SOURCE_VFIR,        7,      &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
1470         TEGRA_INIT_DATA_MUX("csite",    NULL,           "csite",                mux_pllpcm_clkm,        CLK_SOURCE_CSITE,       73,     &periph_u_regs, TEGRA_PERIPH_ON_APB, csite),
1471         TEGRA_INIT_DATA_MUX("la",       NULL,           "la",                   mux_pllpcm_clkm,        CLK_SOURCE_LA,          76,     &periph_u_regs, TEGRA_PERIPH_ON_APB, la),
1472         TEGRA_INIT_DATA_MUX("owr",      NULL,           "tegra_w1",             mux_pllpcm_clkm,        CLK_SOURCE_OWR,         71,     &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
1473         TEGRA_INIT_DATA_MUX("mipi",     NULL,           "mipi",                 mux_pllpcm_clkm,        CLK_SOURCE_MIPI,        50,     &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
1474         TEGRA_INIT_DATA_MUX("tsensor",  NULL,           "tegra-tsensor",        mux_pllpc_clkm_clk32k,  CLK_SOURCE_TSENSOR,     100,    &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor),
1475         TEGRA_INIT_DATA_MUX("i2cslow",  NULL,           "i2cslow",              mux_pllpc_clk32k_clkm,  CLK_SOURCE_I2CSLOW,     81,     &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow),
1476         TEGRA_INIT_DATA_INT("vde",      NULL,           "vde",                  mux_pllpcm_clkm,        CLK_SOURCE_VDE,         61,     &periph_h_regs, 0, vde),
1477         TEGRA_INIT_DATA_INT("vi",       "vi",           "tegra_camera",         mux_pllmcpa,            CLK_SOURCE_VI,          20,     &periph_l_regs, 0, vi),
1478         TEGRA_INIT_DATA_INT("epp",      NULL,           "epp",                  mux_pllmcpa,            CLK_SOURCE_EPP,         19,     &periph_l_regs, 0, epp),
1479         TEGRA_INIT_DATA_INT("mpe",      NULL,           "mpe",                  mux_pllmcpa,            CLK_SOURCE_MPE,         60,     &periph_h_regs, 0, mpe),
1480         TEGRA_INIT_DATA_INT("host1x",   NULL,           "host1x",               mux_pllmcpa,            CLK_SOURCE_HOST1X,      28,     &periph_l_regs, 0, host1x),
1481         TEGRA_INIT_DATA_INT("3d",       NULL,           "3d",                   mux_pllmcpa,            CLK_SOURCE_3D,          24,     &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d),
1482         TEGRA_INIT_DATA_INT("3d2",      NULL,           "3d2",                  mux_pllmcpa,            CLK_SOURCE_3D2,         98,     &periph_v_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d2),
1483         TEGRA_INIT_DATA_INT("2d",       NULL,           "2d",                   mux_pllmcpa,            CLK_SOURCE_2D,          21,     &periph_l_regs, 0, gr2d),
1484         TEGRA_INIT_DATA_INT("se",       NULL,           "se",                   mux_pllpcm_clkm,        CLK_SOURCE_SE,          127,    &periph_v_regs, 0, se),
1485         TEGRA_INIT_DATA_MUX("mselect",  NULL,           "mselect",              mux_pllp_clkm,          CLK_SOURCE_MSELECT,     99,     &periph_v_regs, 0, mselect),
1486         TEGRA_INIT_DATA_MUX("nor",      NULL,           "tegra-nor",            mux_pllpcm_clkm,        CLK_SOURCE_NOR,         42,     &periph_h_regs, 0, nor),
1487         TEGRA_INIT_DATA_MUX("sdmmc1",   NULL,           "sdhci-tegra.0",        mux_pllpcm_clkm,        CLK_SOURCE_SDMMC1,      14,     &periph_l_regs, 0, sdmmc1),
1488         TEGRA_INIT_DATA_MUX("sdmmc2",   NULL,           "sdhci-tegra.1",        mux_pllpcm_clkm,        CLK_SOURCE_SDMMC2,      9,      &periph_l_regs, 0, sdmmc2),
1489         TEGRA_INIT_DATA_MUX("sdmmc3",   NULL,           "sdhci-tegra.2",        mux_pllpcm_clkm,        CLK_SOURCE_SDMMC3,      69,     &periph_u_regs, 0, sdmmc3),
1490         TEGRA_INIT_DATA_MUX("sdmmc4",   NULL,           "sdhci-tegra.3",        mux_pllpcm_clkm,        CLK_SOURCE_SDMMC4,      15,     &periph_l_regs, 0, sdmmc4),
1491         TEGRA_INIT_DATA_MUX("cve",      NULL,           "cve",                  mux_pllpdc_clkm,        CLK_SOURCE_CVE,         49,     &periph_h_regs, 0, cve),
1492         TEGRA_INIT_DATA_MUX("tvo",      NULL,           "tvo",                  mux_pllpdc_clkm,        CLK_SOURCE_TVO,         49,     &periph_h_regs, 0, tvo),
1493         TEGRA_INIT_DATA_MUX("tvdac",    NULL,           "tvdac",                mux_pllpdc_clkm,        CLK_SOURCE_TVDAC,       53,     &periph_h_regs, 0, tvdac),
1494         TEGRA_INIT_DATA_MUX("actmon",   NULL,           "actmon",               mux_pllpc_clk32k_clkm,  CLK_SOURCE_ACTMON,      119,    &periph_v_regs, 0, actmon),
1495         TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor",   "tegra_camera",         mux_pllmcpa,            CLK_SOURCE_VI_SENSOR,   20,     &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
1496         TEGRA_INIT_DATA_DIV16("i2c1",   "div-clk",      "tegra-i2c.0",          mux_pllp_clkm,          CLK_SOURCE_I2C1,        12,     &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1),
1497         TEGRA_INIT_DATA_DIV16("i2c2",   "div-clk",      "tegra-i2c.1",          mux_pllp_clkm,          CLK_SOURCE_I2C2,        54,     &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2),
1498         TEGRA_INIT_DATA_DIV16("i2c3",   "div-clk",      "tegra-i2c.2",          mux_pllp_clkm,          CLK_SOURCE_I2C3,        67,     &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3),
1499         TEGRA_INIT_DATA_DIV16("i2c4",   "div-clk",      "tegra-i2c.3",          mux_pllp_clkm,          CLK_SOURCE_I2C4,        103,    &periph_v_regs, TEGRA_PERIPH_ON_APB, i2c4),
1500         TEGRA_INIT_DATA_DIV16("i2c5",   "div-clk",      "tegra-i2c.4",          mux_pllp_clkm,          CLK_SOURCE_I2C5,        47,     &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c5),
1501         TEGRA_INIT_DATA_UART("uarta",   NULL,           "tegra_uart.0",         mux_pllpcm_clkm,        CLK_SOURCE_UARTA,       6,      &periph_l_regs, uarta),
1502         TEGRA_INIT_DATA_UART("uartb",   NULL,           "tegra_uart.1",         mux_pllpcm_clkm,        CLK_SOURCE_UARTB,       7,      &periph_l_regs, uartb),
1503         TEGRA_INIT_DATA_UART("uartc",   NULL,           "tegra_uart.2",         mux_pllpcm_clkm,        CLK_SOURCE_UARTC,       55,     &periph_h_regs, uartc),
1504         TEGRA_INIT_DATA_UART("uartd",   NULL,           "tegra_uart.3",         mux_pllpcm_clkm,        CLK_SOURCE_UARTD,       65,     &periph_u_regs, uartd),
1505         TEGRA_INIT_DATA_UART("uarte",   NULL,           "tegra_uart.4",         mux_pllpcm_clkm,        CLK_SOURCE_UARTE,       66,     &periph_u_regs, uarte),
1506         TEGRA_INIT_DATA_MUX8("hdmi",    NULL,           "hdmi",                 mux_pllpmdacd2_clkm,    CLK_SOURCE_HDMI,        51,     &periph_h_regs, 0, hdmi),
1507         TEGRA_INIT_DATA_MUX8("extern1", NULL,           "extern1",              mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN1,     120,    &periph_v_regs, 0, extern1),
1508         TEGRA_INIT_DATA_MUX8("extern2", NULL,           "extern2",              mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN2,     121,    &periph_v_regs, 0, extern2),
1509         TEGRA_INIT_DATA_MUX8("extern3", NULL,           "extern3",              mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN3,     122,    &periph_v_regs, 0, extern3),
1510         TEGRA_INIT_DATA("pwm",          NULL,           "pwm",                  mux_pllpc_clk32k_clkm,  CLK_SOURCE_PWM,         28, 2, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, 0, pwm),
1511 };
1512
1513 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1514         TEGRA_INIT_DATA_NODIV("disp1",  NULL, "tegradc.0", mux_pllpmdacd2_clkm,      CLK_SOURCE_DISP1,  29, 3, 27, &periph_l_regs, 0, disp1),
1515         TEGRA_INIT_DATA_NODIV("disp2",  NULL, "tegradc.1", mux_pllpmdacd2_clkm,      CLK_SOURCE_DISP2,  29, 3, 26, &periph_l_regs, 0, disp2),
1516         TEGRA_INIT_DATA_NODIV("dsib",   NULL, "tegradc.1", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB,   25, 1, 82, &periph_u_regs, 0, dsib),
1517 };
1518
1519 static void __init tegra30_periph_clk_init(void)
1520 {
1521         struct tegra_periph_init_data *data;
1522         struct clk *clk;
1523         int i;
1524
1525         /* apbdma */
1526         clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 0, 34,
1527                                     &periph_h_regs, periph_clk_enb_refcnt);
1528         clk_register_clkdev(clk, NULL, "tegra-apbdma");
1529         clks[apbdma] = clk;
1530
1531         /* rtc */
1532         clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
1533                                     TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1534                                     clk_base, 0, 4, &periph_l_regs,
1535                                     periph_clk_enb_refcnt);
1536         clk_register_clkdev(clk, NULL, "rtc-tegra");
1537         clks[rtc] = clk;
1538
1539         /* timer */
1540         clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 0,
1541                                     5, &periph_l_regs, periph_clk_enb_refcnt);
1542         clk_register_clkdev(clk, NULL, "timer");
1543         clks[timer] = clk;
1544
1545         /* kbc */
1546         clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
1547                                     TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1548                                     clk_base, 0, 36, &periph_h_regs,
1549                                     periph_clk_enb_refcnt);
1550         clk_register_clkdev(clk, NULL, "tegra-kbc");
1551         clks[kbc] = clk;
1552
1553         /* csus */
1554         clk = tegra_clk_register_periph_gate("csus", "clk_m",
1555                                     TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1556                                     clk_base, 0, 92, &periph_u_regs,
1557                                     periph_clk_enb_refcnt);
1558         clk_register_clkdev(clk, "csus", "tengra_camera");
1559         clks[csus] = clk;
1560
1561         /* vcp */
1562         clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 29,
1563                                     &periph_l_regs, periph_clk_enb_refcnt);
1564         clk_register_clkdev(clk, "vcp", "tegra-avp");
1565         clks[vcp] = clk;
1566
1567         /* bsea */
1568         clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 0,
1569                                     62, &periph_h_regs, periph_clk_enb_refcnt);
1570         clk_register_clkdev(clk, "bsea", "tegra-avp");
1571         clks[bsea] = clk;
1572
1573         /* bsev */
1574         clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 0,
1575                                     63, &periph_h_regs, periph_clk_enb_refcnt);
1576         clk_register_clkdev(clk, "bsev", "tegra-aes");
1577         clks[bsev] = clk;
1578
1579         /* usbd */
1580         clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0,
1581                                     22, &periph_l_regs, periph_clk_enb_refcnt);
1582         clk_register_clkdev(clk, NULL, "fsl-tegra-udc");
1583         clks[usbd] = clk;
1584
1585         /* usb2 */
1586         clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0,
1587                                     58, &periph_h_regs, periph_clk_enb_refcnt);
1588         clk_register_clkdev(clk, NULL, "tegra-ehci.1");
1589         clks[usb2] = clk;
1590
1591         /* usb3 */
1592         clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0,
1593                                     59, &periph_h_regs, periph_clk_enb_refcnt);
1594         clk_register_clkdev(clk, NULL, "tegra-ehci.2");
1595         clks[usb3] = clk;
1596
1597         /* dsia */
1598         clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1599                                     0, 48, &periph_h_regs,
1600                                     periph_clk_enb_refcnt);
1601         clk_register_clkdev(clk, "dsia", "tegradc.0");
1602         clks[dsia] = clk;
1603
1604         /* csi */
1605         clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
1606                                     0, 52, &periph_h_regs,
1607                                     periph_clk_enb_refcnt);
1608         clk_register_clkdev(clk, "csi", "tegra_camera");
1609         clks[csi] = clk;
1610
1611         /* isp */
1612         clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23,
1613                                     &periph_l_regs, periph_clk_enb_refcnt);
1614         clk_register_clkdev(clk, "isp", "tegra_camera");
1615         clks[isp] = clk;
1616
1617         /* pcie */
1618         clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1619                                     70, &periph_u_regs, periph_clk_enb_refcnt);
1620         clk_register_clkdev(clk, "pcie", "tegra-pcie");
1621         clks[pcie] = clk;
1622
1623         /* afi */
1624         clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1625                                     &periph_u_regs, periph_clk_enb_refcnt);
1626         clk_register_clkdev(clk, "afi", "tegra-pcie");
1627         clks[afi] = clk;
1628
1629         /* pciex */
1630         clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0,
1631                                     74, &periph_u_regs, periph_clk_enb_refcnt);
1632         clk_register_clkdev(clk, "pciex", "tegra-pcie");
1633         clks[pciex] = clk;
1634
1635         /* kfuse */
1636         clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1637                                     TEGRA_PERIPH_ON_APB,
1638                                     clk_base, 0, 40, &periph_h_regs,
1639                                     periph_clk_enb_refcnt);
1640         clk_register_clkdev(clk, NULL, "kfuse-tegra");
1641         clks[kfuse] = clk;
1642
1643         /* fuse */
1644         clk = tegra_clk_register_periph_gate("fuse", "clk_m",
1645                                     TEGRA_PERIPH_ON_APB,
1646                                     clk_base, 0, 39, &periph_h_regs,
1647                                     periph_clk_enb_refcnt);
1648         clk_register_clkdev(clk, "fuse", "fuse-tegra");
1649         clks[fuse] = clk;
1650
1651         /* fuse_burn */
1652         clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
1653                                     TEGRA_PERIPH_ON_APB,
1654                                     clk_base, 0, 39, &periph_h_regs,
1655                                     periph_clk_enb_refcnt);
1656         clk_register_clkdev(clk, "fuse_burn", "fuse-tegra");
1657         clks[fuse_burn] = clk;
1658
1659         /* apbif */
1660         clk = tegra_clk_register_periph_gate("apbif", "clk_m", 0,
1661                                     clk_base, 0, 107, &periph_v_regs,
1662                                     periph_clk_enb_refcnt);
1663         clk_register_clkdev(clk, "apbif", "tegra30-ahub");
1664         clks[apbif] = clk;
1665
1666         /* hda2hdmi */
1667         clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
1668                                     TEGRA_PERIPH_ON_APB,
1669                                     clk_base, 0, 128, &periph_w_regs,
1670                                     periph_clk_enb_refcnt);
1671         clk_register_clkdev(clk, "hda2hdmi", "tegra30-hda");
1672         clks[hda2hdmi] = clk;
1673
1674         /* sata_cold */
1675         clk = tegra_clk_register_periph_gate("sata_cold", "clk_m",
1676                                     TEGRA_PERIPH_ON_APB,
1677                                     clk_base, 0, 129, &periph_w_regs,
1678                                     periph_clk_enb_refcnt);
1679         clk_register_clkdev(clk, NULL, "tegra_sata_cold");
1680         clks[sata_cold] = clk;
1681
1682         /* dtv */
1683         clk = tegra_clk_register_periph_gate("dtv", "clk_m",
1684                                     TEGRA_PERIPH_ON_APB,
1685                                     clk_base, 0, 79, &periph_u_regs,
1686                                     periph_clk_enb_refcnt);
1687         clk_register_clkdev(clk, NULL, "dtv");
1688         clks[dtv] = clk;
1689
1690         /* emc */
1691         clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1692                                ARRAY_SIZE(mux_pllmcp_clkm),
1693                                CLK_SET_RATE_NO_REPARENT,
1694                                clk_base + CLK_SOURCE_EMC,
1695                                30, 2, 0, NULL);
1696         clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
1697                                     57, &periph_h_regs, periph_clk_enb_refcnt);
1698         clk_register_clkdev(clk, "emc", NULL);
1699         clks[emc] = clk;
1700
1701         for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1702                 data = &tegra_periph_clk_list[i];
1703                 clk = tegra_clk_register_periph(data->name, data->parent_names,
1704                                 data->num_parents, &data->periph,
1705                                 clk_base, data->offset, data->flags);
1706                 clk_register_clkdev(clk, data->con_id, data->dev_id);
1707                 clks[data->clk_id] = clk;
1708         }
1709
1710         for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1711                 data = &tegra_periph_nodiv_clk_list[i];
1712                 clk = tegra_clk_register_periph_nodiv(data->name,
1713                                         data->parent_names,
1714                                         data->num_parents, &data->periph,
1715                                         clk_base, data->offset);
1716                 clk_register_clkdev(clk, data->con_id, data->dev_id);
1717                 clks[data->clk_id] = clk;
1718         }
1719 }
1720
1721 static void __init tegra30_fixed_clk_init(void)
1722 {
1723         struct clk *clk;
1724
1725         /* clk_32k */
1726         clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1727                                 32768);
1728         clk_register_clkdev(clk, "clk_32k", NULL);
1729         clks[clk_32k] = clk;
1730
1731         /* clk_m_div2 */
1732         clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
1733                                 CLK_SET_RATE_PARENT, 1, 2);
1734         clk_register_clkdev(clk, "clk_m_div2", NULL);
1735         clks[clk_m_div2] = clk;
1736
1737         /* clk_m_div4 */
1738         clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
1739                                 CLK_SET_RATE_PARENT, 1, 4);
1740         clk_register_clkdev(clk, "clk_m_div4", NULL);
1741         clks[clk_m_div4] = clk;
1742
1743         /* cml0 */
1744         clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1745                                 0, 0, &cml_lock);
1746         clk_register_clkdev(clk, "cml0", NULL);
1747         clks[cml0] = clk;
1748
1749         /* cml1 */
1750         clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1751                                 1, 0, &cml_lock);
1752         clk_register_clkdev(clk, "cml1", NULL);
1753         clks[cml1] = clk;
1754 }
1755
1756 static void __init tegra30_osc_clk_init(void)
1757 {
1758         struct clk *clk;
1759         unsigned int pll_ref_div;
1760
1761         tegra30_clk_measure_input_freq();
1762
1763         /* clk_m */
1764         clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
1765                                 input_freq);
1766         clk_register_clkdev(clk, "clk_m", NULL);
1767         clks[clk_m] = clk;
1768
1769         /* pll_ref */
1770         pll_ref_div = tegra30_get_pll_ref_div();
1771         clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1772                                 CLK_SET_RATE_PARENT, 1, pll_ref_div);
1773         clk_register_clkdev(clk, "pll_ref", NULL);
1774         clks[pll_ref] = clk;
1775 }
1776
1777 /* Tegra30 CPU clock and reset control functions */
1778 static void tegra30_wait_cpu_in_reset(u32 cpu)
1779 {
1780         unsigned int reg;
1781
1782         do {
1783                 reg = readl(clk_base +
1784                             TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1785                 cpu_relax();
1786         } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
1787
1788         return;
1789 }
1790
1791 static void tegra30_put_cpu_in_reset(u32 cpu)
1792 {
1793         writel(CPU_RESET(cpu),
1794                clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1795         dmb();
1796 }
1797
1798 static void tegra30_cpu_out_of_reset(u32 cpu)
1799 {
1800         writel(CPU_RESET(cpu),
1801                clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1802         wmb();
1803 }
1804
1805
1806 static void tegra30_enable_cpu_clock(u32 cpu)
1807 {
1808         unsigned int reg;
1809
1810         writel(CPU_CLOCK(cpu),
1811                clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1812         reg = readl(clk_base +
1813                     TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1814 }
1815
1816 static void tegra30_disable_cpu_clock(u32 cpu)
1817 {
1818
1819         unsigned int reg;
1820
1821         reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1822         writel(reg | CPU_CLOCK(cpu),
1823                clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1824 }
1825
1826 #ifdef CONFIG_PM_SLEEP
1827 static bool tegra30_cpu_rail_off_ready(void)
1828 {
1829         unsigned int cpu_rst_status;
1830         int cpu_pwr_status;
1831
1832         cpu_rst_status = readl(clk_base +
1833                                 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1834         cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
1835                          tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
1836                          tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
1837
1838         if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
1839                 return false;
1840
1841         return true;
1842 }
1843
1844 static void tegra30_cpu_clock_suspend(void)
1845 {
1846         /* switch coresite to clk_m, save off original source */
1847         tegra30_cpu_clk_sctx.clk_csite_src =
1848                                 readl(clk_base + CLK_RESET_SOURCE_CSITE);
1849         writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE);
1850
1851         tegra30_cpu_clk_sctx.cpu_burst =
1852                                 readl(clk_base + CLK_RESET_CCLK_BURST);
1853         tegra30_cpu_clk_sctx.pllx_base =
1854                                 readl(clk_base + CLK_RESET_PLLX_BASE);
1855         tegra30_cpu_clk_sctx.pllx_misc =
1856                                 readl(clk_base + CLK_RESET_PLLX_MISC);
1857         tegra30_cpu_clk_sctx.cclk_divider =
1858                                 readl(clk_base + CLK_RESET_CCLK_DIVIDER);
1859 }
1860
1861 static void tegra30_cpu_clock_resume(void)
1862 {
1863         unsigned int reg, policy;
1864
1865         /* Is CPU complex already running on PLLX? */
1866         reg = readl(clk_base + CLK_RESET_CCLK_BURST);
1867         policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
1868
1869         if (policy == CLK_RESET_CCLK_IDLE_POLICY)
1870                 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
1871         else if (policy == CLK_RESET_CCLK_RUN_POLICY)
1872                 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
1873         else
1874                 BUG();
1875
1876         if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
1877                 /* restore PLLX settings if CPU is on different PLL */
1878                 writel(tegra30_cpu_clk_sctx.pllx_misc,
1879                                         clk_base + CLK_RESET_PLLX_MISC);
1880                 writel(tegra30_cpu_clk_sctx.pllx_base,
1881                                         clk_base + CLK_RESET_PLLX_BASE);
1882
1883                 /* wait for PLL stabilization if PLLX was enabled */
1884                 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
1885                         udelay(300);
1886         }
1887
1888         /*
1889          * Restore original burst policy setting for calls resulting from CPU
1890          * LP2 in idle or system suspend.
1891          */
1892         writel(tegra30_cpu_clk_sctx.cclk_divider,
1893                                         clk_base + CLK_RESET_CCLK_DIVIDER);
1894         writel(tegra30_cpu_clk_sctx.cpu_burst,
1895                                         clk_base + CLK_RESET_CCLK_BURST);
1896
1897         writel(tegra30_cpu_clk_sctx.clk_csite_src,
1898                                         clk_base + CLK_RESET_SOURCE_CSITE);
1899 }
1900 #endif
1901
1902 static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
1903         .wait_for_reset = tegra30_wait_cpu_in_reset,
1904         .put_in_reset   = tegra30_put_cpu_in_reset,
1905         .out_of_reset   = tegra30_cpu_out_of_reset,
1906         .enable_clock   = tegra30_enable_cpu_clock,
1907         .disable_clock  = tegra30_disable_cpu_clock,
1908 #ifdef CONFIG_PM_SLEEP
1909         .rail_off_ready = tegra30_cpu_rail_off_ready,
1910         .suspend        = tegra30_cpu_clock_suspend,
1911         .resume         = tegra30_cpu_clock_resume,
1912 #endif
1913 };
1914
1915 static struct tegra_clk_init_table init_table[] __initdata = {
1916         {uarta, pll_p, 408000000, 0},
1917         {uartb, pll_p, 408000000, 0},
1918         {uartc, pll_p, 408000000, 0},
1919         {uartd, pll_p, 408000000, 0},
1920         {uarte, pll_p, 408000000, 0},
1921         {pll_a, clk_max, 564480000, 1},
1922         {pll_a_out0, clk_max, 11289600, 1},
1923         {extern1, pll_a_out0, 0, 1},
1924         {clk_out_1_mux, extern1, 0, 0},
1925         {clk_out_1, clk_max, 0, 1},
1926         {blink, clk_max, 0, 1},
1927         {i2s0, pll_a_out0, 11289600, 0},
1928         {i2s1, pll_a_out0, 11289600, 0},
1929         {i2s2, pll_a_out0, 11289600, 0},
1930         {i2s3, pll_a_out0, 11289600, 0},
1931         {i2s4, pll_a_out0, 11289600, 0},
1932         {sdmmc1, pll_p, 48000000, 0},
1933         {sdmmc2, pll_p, 48000000, 0},
1934         {sdmmc3, pll_p, 48000000, 0},
1935         {pll_m, clk_max, 0, 1},
1936         {pclk, clk_max, 0, 1},
1937         {csite, clk_max, 0, 1},
1938         {emc, clk_max, 0, 1},
1939         {mselect, clk_max, 0, 1},
1940         {sbc1, pll_p, 100000000, 0},
1941         {sbc2, pll_p, 100000000, 0},
1942         {sbc3, pll_p, 100000000, 0},
1943         {sbc4, pll_p, 100000000, 0},
1944         {sbc5, pll_p, 100000000, 0},
1945         {sbc6, pll_p, 100000000, 0},
1946         {host1x, pll_c, 150000000, 0},
1947         {disp1, pll_p, 600000000, 0},
1948         {disp2, pll_p, 600000000, 0},
1949         {twd, clk_max, 0, 1},
1950         {gr2d, pll_c, 300000000, 0},
1951         {gr3d, pll_c, 300000000, 0},
1952         {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
1953 };
1954
1955 static void __init tegra30_clock_apply_init_table(void)
1956 {
1957         tegra_init_from_table(init_table, clks, clk_max);
1958 }
1959
1960 /*
1961  * Some clocks may be used by different drivers depending on the board
1962  * configuration.  List those here to register them twice in the clock lookup
1963  * table under two names.
1964  */
1965 static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1966         TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL),
1967         TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL),
1968         TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL),
1969         TEGRA_CLK_DUPLICATE(bsev, "tegra-avp", "bsev"),
1970         TEGRA_CLK_DUPLICATE(bsev, "nvavp", "bsev"),
1971         TEGRA_CLK_DUPLICATE(vde, "tegra-aes", "vde"),
1972         TEGRA_CLK_DUPLICATE(bsea, "tegra-aes", "bsea"),
1973         TEGRA_CLK_DUPLICATE(bsea, "nvavp", "bsea"),
1974         TEGRA_CLK_DUPLICATE(cml1, "tegra_sata_cml", NULL),
1975         TEGRA_CLK_DUPLICATE(cml0, "tegra_pcie", "cml"),
1976         TEGRA_CLK_DUPLICATE(pciex, "tegra_pcie", "pciex"),
1977         TEGRA_CLK_DUPLICATE(vcp, "nvavp", "vcp"),
1978         TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* MUST be the last entry */
1979 };
1980
1981 static const struct of_device_id pmc_match[] __initconst = {
1982         { .compatible = "nvidia,tegra30-pmc" },
1983         {},
1984 };
1985
1986 static void __init tegra30_clock_init(struct device_node *np)
1987 {
1988         struct device_node *node;
1989         int i;
1990
1991         clk_base = of_iomap(np, 0);
1992         if (!clk_base) {
1993                 pr_err("ioremap tegra30 CAR failed\n");
1994                 return;
1995         }
1996
1997         node = of_find_matching_node(NULL, pmc_match);
1998         if (!node) {
1999                 pr_err("Failed to find pmc node\n");
2000                 BUG();
2001         }
2002
2003         pmc_base = of_iomap(node, 0);
2004         if (!pmc_base) {
2005                 pr_err("Can't map pmc registers\n");
2006                 BUG();
2007         }
2008
2009         tegra30_osc_clk_init();
2010         tegra30_fixed_clk_init();
2011         tegra30_pll_init();
2012         tegra30_super_clk_init();
2013         tegra30_periph_clk_init();
2014         tegra30_audio_clk_init();
2015         tegra30_pmc_clk_init();
2016
2017         for (i = 0; i < ARRAY_SIZE(clks); i++) {
2018                 if (IS_ERR(clks[i])) {
2019                         pr_err("Tegra30 clk %d: register failed with %ld\n",
2020                                i, PTR_ERR(clks[i]));
2021                         BUG();
2022                 }
2023                 if (!clks[i])
2024                         clks[i] = ERR_PTR(-EINVAL);
2025         }
2026
2027         tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max);
2028
2029         clk_data.clks = clks;
2030         clk_data.clk_num = ARRAY_SIZE(clks);
2031         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
2032
2033         tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
2034
2035         tegra_cpu_car_ops = &tegra30_cpu_car_ops;
2036 }
2037 CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init);