2 * OMAP DPLL clock support
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Tero Kristo <t-kristo@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
26 #define pr_fmt(fmt) "%s: " fmt, __func__
28 #define DPLL_HAS_AUTOIDLE 0x1
30 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
31 defined(CONFIG_SOC_DRA7XX)
32 static const struct clk_ops dpll_m4xen_ck_ops = {
33 .enable = &omap3_noncore_dpll_enable,
34 .disable = &omap3_noncore_dpll_disable,
35 .recalc_rate = &omap4_dpll_regm4xen_recalc,
36 .round_rate = &omap4_dpll_regm4xen_round_rate,
37 .set_rate = &omap3_noncore_dpll_set_rate,
38 .get_parent = &omap2_init_dpll_parent,
42 static const struct clk_ops dpll_core_ck_ops = {
43 .recalc_rate = &omap3_dpll_recalc,
44 .get_parent = &omap2_init_dpll_parent,
47 #ifdef CONFIG_ARCH_OMAP3
48 static const struct clk_ops omap3_dpll_core_ck_ops = {
49 .get_parent = &omap2_init_dpll_parent,
50 .recalc_rate = &omap3_dpll_recalc,
51 .round_rate = &omap2_dpll_round_rate,
55 static const struct clk_ops dpll_ck_ops = {
56 .enable = &omap3_noncore_dpll_enable,
57 .disable = &omap3_noncore_dpll_disable,
58 .recalc_rate = &omap3_dpll_recalc,
59 .round_rate = &omap2_dpll_round_rate,
60 .set_rate = &omap3_noncore_dpll_set_rate,
61 .get_parent = &omap2_init_dpll_parent,
64 static const struct clk_ops dpll_no_gate_ck_ops = {
65 .recalc_rate = &omap3_dpll_recalc,
66 .get_parent = &omap2_init_dpll_parent,
67 .round_rate = &omap2_dpll_round_rate,
68 .set_rate = &omap3_noncore_dpll_set_rate,
71 #ifdef CONFIG_ARCH_OMAP3
72 static const struct clk_ops omap3_dpll_ck_ops = {
73 .enable = &omap3_noncore_dpll_enable,
74 .disable = &omap3_noncore_dpll_disable,
75 .get_parent = &omap2_init_dpll_parent,
76 .recalc_rate = &omap3_dpll_recalc,
77 .set_rate = &omap3_noncore_dpll_set_rate,
78 .round_rate = &omap2_dpll_round_rate,
81 static const struct clk_ops omap3_dpll_per_ck_ops = {
82 .enable = &omap3_noncore_dpll_enable,
83 .disable = &omap3_noncore_dpll_disable,
84 .get_parent = &omap2_init_dpll_parent,
85 .recalc_rate = &omap3_dpll_recalc,
86 .set_rate = &omap3_dpll4_set_rate,
87 .round_rate = &omap2_dpll_round_rate,
91 static const struct clk_ops dpll_x2_ck_ops = {
92 .recalc_rate = &omap3_clkoutx2_recalc,
96 * ti_clk_register_dpll - low level registration of a DPLL clock
97 * @hw: hardware clock definition for the clock
98 * @node: device node for the clock
100 * Finalizes DPLL registration process. In case a failure (clk-ref or
101 * clk-bypass is missing), the clock is added to retry list and
102 * the initialization is retried on later stage.
104 static void __init ti_clk_register_dpll(struct clk_hw *hw,
105 struct device_node *node)
107 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
108 struct dpll_data *dd = clk_hw->dpll_data;
111 dd->clk_ref = of_clk_get(node, 0);
112 dd->clk_bypass = of_clk_get(node, 1);
114 if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) {
115 pr_debug("clk-ref or clk-bypass missing for %s, retry later\n",
117 if (!ti_clk_retry_init(node, hw, ti_clk_register_dpll))
123 /* register the clock */
124 clk = clk_register(NULL, &clk_hw->hw);
127 omap2_init_clk_hw_omap_clocks(clk);
128 of_clk_add_provider(node, of_clk_src_simple_get, clk);
129 kfree(clk_hw->hw.init->parent_names);
130 kfree(clk_hw->hw.init);
135 kfree(clk_hw->dpll_data);
136 kfree(clk_hw->hw.init->parent_names);
137 kfree(clk_hw->hw.init);
141 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
142 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX)
144 * ti_clk_register_dpll_x2 - Registers a DPLLx2 clock
145 * @node: device node for this clock
146 * @ops: clk_ops for this clock
147 * @hw_ops: clk_hw_ops for this clock
149 * Initializes a DPLL x 2 clock from device tree data.
151 static void ti_clk_register_dpll_x2(struct device_node *node,
152 const struct clk_ops *ops,
153 const struct clk_hw_omap_ops *hw_ops)
156 struct clk_init_data init = { NULL };
157 struct clk_hw_omap *clk_hw;
158 const char *name = node->name;
159 const char *parent_name;
161 parent_name = of_clk_get_parent_name(node, 0);
163 pr_err("%s must have parent\n", node->name);
167 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
171 clk_hw->ops = hw_ops;
172 clk_hw->hw.init = &init;
176 init.parent_names = &parent_name;
177 init.num_parents = 1;
179 /* register the clock */
180 clk = clk_register(NULL, &clk_hw->hw);
185 omap2_init_clk_hw_omap_clocks(clk);
186 of_clk_add_provider(node, of_clk_src_simple_get, clk);
192 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
193 * @node: device node containing the DPLL info
194 * @ops: ops for the DPLL
195 * @ddt: DPLL data template to use
196 * @init_flags: flags for controlling init types
198 * Initializes a DPLL clock from device tree data.
200 static void __init of_ti_dpll_setup(struct device_node *node,
201 const struct clk_ops *ops,
202 const struct dpll_data *ddt,
205 struct clk_hw_omap *clk_hw = NULL;
206 struct clk_init_data *init = NULL;
207 const char **parent_names = NULL;
208 struct dpll_data *dd = NULL;
212 dd = kzalloc(sizeof(*dd), GFP_KERNEL);
213 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
214 init = kzalloc(sizeof(*init), GFP_KERNEL);
215 if (!dd || !clk_hw || !init)
218 memcpy(dd, ddt, sizeof(*dd));
220 clk_hw->dpll_data = dd;
221 clk_hw->ops = &clkhwops_omap3_dpll;
222 clk_hw->hw.init = init;
223 clk_hw->flags = MEMMAP_ADDRESSING;
225 init->name = node->name;
228 init->num_parents = of_clk_get_parent_count(node);
229 if (init->num_parents < 1) {
230 pr_err("%s must have parent(s)\n", node->name);
234 parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL);
238 for (i = 0; i < init->num_parents; i++)
239 parent_names[i] = of_clk_get_parent_name(node, i);
241 init->parent_names = parent_names;
243 dd->control_reg = ti_clk_get_reg_addr(node, 0);
244 dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
245 dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
247 if (!dd->control_reg || !dd->idlest_reg || !dd->mult_div1_reg)
250 if (init_flags & DPLL_HAS_AUTOIDLE) {
251 dd->autoidle_reg = ti_clk_get_reg_addr(node, 3);
252 if (!dd->autoidle_reg)
256 if (of_property_read_bool(node, "ti,low-power-stop"))
257 dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
259 if (of_property_read_bool(node, "ti,low-power-bypass"))
260 dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
262 if (of_property_read_bool(node, "ti,lock"))
263 dpll_mode |= 1 << DPLL_LOCKED;
266 dd->modes = dpll_mode;
268 ti_clk_register_dpll(&clk_hw->hw, node);
278 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
279 defined(CONFIG_SOC_DRA7XX)
280 static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
282 ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
284 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
285 of_ti_omap4_dpll_x2_setup);
288 #ifdef CONFIG_SOC_AM33XX
289 static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
291 ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
293 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
294 of_ti_am3_dpll_x2_setup);
297 #ifdef CONFIG_ARCH_OMAP3
298 static void __init of_ti_omap3_dpll_setup(struct device_node *node)
300 const struct dpll_data dd = {
303 .autoidle_mask = 0x7,
304 .mult_mask = 0x7ff << 8,
306 .max_multiplier = 2047,
309 .freqsel_mask = 0xf0,
310 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
313 of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
315 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
316 of_ti_omap3_dpll_setup);
318 static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
320 const struct dpll_data dd = {
323 .autoidle_mask = 0x7,
324 .mult_mask = 0x7ff << 16,
325 .div1_mask = 0x7f << 8,
326 .max_multiplier = 2047,
329 .freqsel_mask = 0xf0,
332 of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
334 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
335 of_ti_omap3_core_dpll_setup);
337 static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
339 const struct dpll_data dd = {
340 .idlest_mask = 0x1 << 1,
341 .enable_mask = 0x7 << 16,
342 .autoidle_mask = 0x7 << 3,
343 .mult_mask = 0x7ff << 8,
345 .max_multiplier = 2047,
348 .freqsel_mask = 0xf00000,
349 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
352 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
354 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
355 of_ti_omap3_per_dpll_setup);
357 static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
359 const struct dpll_data dd = {
360 .idlest_mask = 0x1 << 1,
361 .enable_mask = 0x7 << 16,
362 .autoidle_mask = 0x7 << 3,
363 .mult_mask = 0xfff << 8,
365 .max_multiplier = 4095,
368 .sddiv_mask = 0xff << 24,
369 .dco_mask = 0xe << 20,
370 .flags = DPLL_J_TYPE,
371 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
374 of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
376 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
377 of_ti_omap3_per_jtype_dpll_setup);
380 static void __init of_ti_omap4_dpll_setup(struct device_node *node)
382 const struct dpll_data dd = {
385 .autoidle_mask = 0x7,
386 .mult_mask = 0x7ff << 8,
388 .max_multiplier = 2047,
391 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
394 of_ti_dpll_setup(node, &dpll_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
396 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
397 of_ti_omap4_dpll_setup);
399 static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
401 const struct dpll_data dd = {
404 .autoidle_mask = 0x7,
405 .mult_mask = 0x7ff << 8,
407 .max_multiplier = 2047,
410 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
413 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
415 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
416 of_ti_omap4_core_dpll_setup);
418 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
419 defined(CONFIG_SOC_DRA7XX)
420 static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
422 const struct dpll_data dd = {
425 .autoidle_mask = 0x7,
426 .mult_mask = 0x7ff << 8,
428 .max_multiplier = 2047,
432 .lpmode_mask = 1 << 10,
433 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
436 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
438 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
439 of_ti_omap4_m4xen_dpll_setup);
441 static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
443 const struct dpll_data dd = {
446 .autoidle_mask = 0x7,
447 .mult_mask = 0xfff << 8,
449 .max_multiplier = 4095,
452 .sddiv_mask = 0xff << 24,
453 .flags = DPLL_J_TYPE,
454 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
457 of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd, DPLL_HAS_AUTOIDLE);
459 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
460 of_ti_omap4_jtype_dpll_setup);
463 static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
465 const struct dpll_data dd = {
468 .autoidle_mask = 0x7,
469 .mult_mask = 0x7ff << 8,
471 .max_multiplier = 2047,
474 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
477 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd, 0);
479 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
480 of_ti_am3_no_gate_dpll_setup);
482 static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
484 const struct dpll_data dd = {
487 .autoidle_mask = 0x7,
488 .mult_mask = 0x7ff << 8,
490 .max_multiplier = 4095,
493 .flags = DPLL_J_TYPE,
494 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
497 of_ti_dpll_setup(node, &dpll_ck_ops, &dd, 0);
499 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
500 of_ti_am3_jtype_dpll_setup);
502 static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
504 const struct dpll_data dd = {
507 .autoidle_mask = 0x7,
508 .mult_mask = 0x7ff << 8,
510 .max_multiplier = 2047,
513 .flags = DPLL_J_TYPE,
514 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
517 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd, 0);
519 CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
520 "ti,am3-dpll-no-gate-j-type-clock",
521 of_ti_am3_no_gate_jtype_dpll_setup);
523 static void __init of_ti_am3_dpll_setup(struct device_node *node)
525 const struct dpll_data dd = {
528 .autoidle_mask = 0x7,
529 .mult_mask = 0x7ff << 8,
531 .max_multiplier = 2047,
534 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
537 of_ti_dpll_setup(node, &dpll_ck_ops, &dd, 0);
539 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
541 static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
543 const struct dpll_data dd = {
546 .autoidle_mask = 0x7,
547 .mult_mask = 0x7ff << 8,
549 .max_multiplier = 2047,
552 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
555 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd, 0);
557 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
558 of_ti_am3_core_dpll_setup);