2 * Intel Atom platform clocks driver for BayTrail and CherryTrail SoCs
4 * Copyright (C) 2016, Intel Corporation
5 * Author: Irina Tirdea <irina.tirdea@intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/clk-provider.h>
18 #include <linux/clkdev.h>
19 #include <linux/err.h>
20 #include <linux/platform_data/x86/clk-pmc-atom.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
24 #define PLT_CLK_NAME_BASE "pmc_plt_clk"
26 #define PMC_CLK_CTL_OFFSET 0x60
27 #define PMC_CLK_CTL_SIZE 4
29 #define PMC_CLK_CTL_GATED_ON_D3 0x0
30 #define PMC_CLK_CTL_FORCE_ON 0x1
31 #define PMC_CLK_CTL_FORCE_OFF 0x2
32 #define PMC_CLK_CTL_RESERVED 0x3
33 #define PMC_MASK_CLK_CTL GENMASK(1, 0)
34 #define PMC_MASK_CLK_FREQ BIT(2)
35 #define PMC_CLK_FREQ_XTAL (0 << 2) /* 25 MHz */
36 #define PMC_CLK_FREQ_PLL (1 << 2) /* 19.2 MHz */
38 struct clk_plt_fixed {
40 struct clk_lookup *lookup;
46 struct clk_lookup *lookup;
47 /* protect access to PMC registers */
51 #define to_clk_plt(_hw) container_of(_hw, struct clk_plt, hw)
54 struct clk_plt_fixed **parents;
56 struct clk_plt *clks[PMC_CLK_NUM];
59 /* Return an index in parent table */
60 static inline int plt_reg_to_parent(int reg)
62 switch (reg & PMC_MASK_CLK_FREQ) {
64 case PMC_CLK_FREQ_XTAL:
66 case PMC_CLK_FREQ_PLL:
71 /* Return clk index of parent */
72 static inline int plt_parent_to_reg(int index)
77 return PMC_CLK_FREQ_XTAL;
79 return PMC_CLK_FREQ_PLL;
83 /* Abstract status in simpler enabled/disabled value */
84 static inline int plt_reg_to_enabled(int reg)
86 switch (reg & PMC_MASK_CLK_CTL) {
87 case PMC_CLK_CTL_GATED_ON_D3:
88 case PMC_CLK_CTL_FORCE_ON:
89 return 1; /* enabled */
90 case PMC_CLK_CTL_FORCE_OFF:
91 case PMC_CLK_CTL_RESERVED:
93 return 0; /* disabled */
97 static void plt_clk_reg_update(struct clk_plt *clk, u32 mask, u32 val)
102 spin_lock_irqsave(&clk->lock, flags);
104 tmp = readl(clk->reg);
105 tmp = (tmp & ~mask) | (val & mask);
106 writel(tmp, clk->reg);
108 spin_unlock_irqrestore(&clk->lock, flags);
111 static int plt_clk_set_parent(struct clk_hw *hw, u8 index)
113 struct clk_plt *clk = to_clk_plt(hw);
115 plt_clk_reg_update(clk, PMC_MASK_CLK_FREQ, plt_parent_to_reg(index));
120 static u8 plt_clk_get_parent(struct clk_hw *hw)
122 struct clk_plt *clk = to_clk_plt(hw);
125 value = readl(clk->reg);
127 return plt_reg_to_parent(value);
130 static int plt_clk_enable(struct clk_hw *hw)
132 struct clk_plt *clk = to_clk_plt(hw);
134 plt_clk_reg_update(clk, PMC_MASK_CLK_CTL, PMC_CLK_CTL_FORCE_ON);
139 static void plt_clk_disable(struct clk_hw *hw)
141 struct clk_plt *clk = to_clk_plt(hw);
143 plt_clk_reg_update(clk, PMC_MASK_CLK_CTL, PMC_CLK_CTL_FORCE_OFF);
146 static int plt_clk_is_enabled(struct clk_hw *hw)
148 struct clk_plt *clk = to_clk_plt(hw);
151 value = readl(clk->reg);
153 return plt_reg_to_enabled(value);
156 static const struct clk_ops plt_clk_ops = {
157 .enable = plt_clk_enable,
158 .disable = plt_clk_disable,
159 .is_enabled = plt_clk_is_enabled,
160 .get_parent = plt_clk_get_parent,
161 .set_parent = plt_clk_set_parent,
162 .determine_rate = __clk_mux_determine_rate,
165 static struct clk_plt *plt_clk_register(struct platform_device *pdev, int id,
167 const char **parent_names,
170 struct clk_plt *pclk;
171 struct clk_init_data init;
174 pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL);
176 return ERR_PTR(-ENOMEM);
178 init.name = kasprintf(GFP_KERNEL, "%s_%d", PLT_CLK_NAME_BASE, id);
179 init.ops = &plt_clk_ops;
181 init.parent_names = parent_names;
182 init.num_parents = num_parents;
184 pclk->hw.init = &init;
185 pclk->reg = base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE;
186 spin_lock_init(&pclk->lock);
188 ret = devm_clk_hw_register(&pdev->dev, &pclk->hw);
194 pclk->lookup = clkdev_hw_create(&pclk->hw, init.name, NULL);
196 pclk = ERR_PTR(-ENOMEM);
205 static void plt_clk_unregister(struct clk_plt *pclk)
207 clkdev_drop(pclk->lookup);
210 static struct clk_plt_fixed *plt_clk_register_fixed_rate(struct platform_device *pdev,
212 const char *parent_name,
213 unsigned long fixed_rate)
215 struct clk_plt_fixed *pclk;
217 pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL);
219 return ERR_PTR(-ENOMEM);
221 pclk->clk = clk_hw_register_fixed_rate(&pdev->dev, name, parent_name,
223 if (IS_ERR(pclk->clk))
224 return ERR_CAST(pclk->clk);
226 pclk->lookup = clkdev_hw_create(pclk->clk, name, NULL);
228 clk_hw_unregister_fixed_rate(pclk->clk);
229 return ERR_PTR(-ENOMEM);
235 static void plt_clk_unregister_fixed_rate(struct clk_plt_fixed *pclk)
237 clkdev_drop(pclk->lookup);
238 clk_hw_unregister_fixed_rate(pclk->clk);
241 static void plt_clk_unregister_fixed_rate_loop(struct clk_plt_data *data,
245 plt_clk_unregister_fixed_rate(data->parents[i]);
248 static void plt_clk_free_parent_names_loop(const char **parent_names,
252 kfree_const(parent_names[i]);
256 static void plt_clk_unregister_loop(struct clk_plt_data *data,
260 plt_clk_unregister(data->clks[i]);
263 static const char **plt_clk_register_parents(struct platform_device *pdev,
264 struct clk_plt_data *data,
265 const struct pmc_clk *clks)
267 const char **parent_names;
273 while (clks[nparents].name)
276 data->parents = devm_kcalloc(&pdev->dev, nparents,
277 sizeof(*data->parents), GFP_KERNEL);
279 return ERR_PTR(-ENOMEM);
281 parent_names = kcalloc(nparents, sizeof(*parent_names),
284 return ERR_PTR(-ENOMEM);
286 for (i = 0; i < nparents; i++) {
288 plt_clk_register_fixed_rate(pdev, clks[i].name,
291 if (IS_ERR(data->parents[i])) {
292 err = PTR_ERR(data->parents[i]);
295 parent_names[i] = kstrdup_const(clks[i].name, GFP_KERNEL);
298 data->nparents = nparents;
302 plt_clk_unregister_fixed_rate_loop(data, i);
303 plt_clk_free_parent_names_loop(parent_names, i);
307 static void plt_clk_unregister_parents(struct clk_plt_data *data)
309 plt_clk_unregister_fixed_rate_loop(data, data->nparents);
312 static int plt_clk_probe(struct platform_device *pdev)
314 const struct pmc_clk_data *pmc_data;
315 const char **parent_names;
316 struct clk_plt_data *data;
320 pmc_data = dev_get_platdata(&pdev->dev);
321 if (!pmc_data || !pmc_data->clks)
324 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
328 parent_names = plt_clk_register_parents(pdev, data, pmc_data->clks);
329 if (IS_ERR(parent_names))
330 return PTR_ERR(parent_names);
332 for (i = 0; i < PMC_CLK_NUM; i++) {
333 data->clks[i] = plt_clk_register(pdev, i, pmc_data->base,
334 parent_names, data->nparents);
335 if (IS_ERR(data->clks[i])) {
336 err = PTR_ERR(data->clks[i]);
337 goto err_unreg_clk_plt;
341 plt_clk_free_parent_names_loop(parent_names, data->nparents);
343 platform_set_drvdata(pdev, data);
347 plt_clk_unregister_loop(data, i);
348 plt_clk_unregister_parents(data);
349 plt_clk_free_parent_names_loop(parent_names, data->nparents);
353 static int plt_clk_remove(struct platform_device *pdev)
355 struct clk_plt_data *data;
357 data = platform_get_drvdata(pdev);
359 plt_clk_unregister_loop(data, PMC_CLK_NUM);
360 plt_clk_unregister_parents(data);
364 static struct platform_driver plt_clk_driver = {
366 .name = "clk-pmc-atom",
368 .probe = plt_clk_probe,
369 .remove = plt_clk_remove,
371 builtin_platform_driver(plt_clk_driver);