drivers/clk/zte/clk-zx296718.c

   1 /*
   2  * Copyright (C) 2015 - 2016 ZTE Corporation.
   3  * Copyright (C) 2016 Linaro Ltd.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9 #include <linux/clk-provider.h>
  10 #include <linux/device.h>
  11 #include <linux/kernel.h>
  12 #include <linux/of_address.h>
  13 #include <linux/of_device.h>
  14 #include <linux/platform_device.h>
  15
  16 #include <dt-bindings/clock/zx296718-clock.h>
  17 #include "clk.h"
  18
  19 /* TOP CRM */
  20 #define TOP_CLK_MUX0    0x04
  21 #define TOP_CLK_MUX1    0x08
  22 #define TOP_CLK_MUX2    0x0c
  23 #define TOP_CLK_MUX3    0x10
  24 #define TOP_CLK_MUX4    0x14
  25 #define TOP_CLK_MUX5    0x18
  26 #define TOP_CLK_MUX6    0x1c
  27 #define TOP_CLK_MUX7    0x20
  28 #define TOP_CLK_MUX9    0x28
  29
  30
  31 #define TOP_CLK_GATE0   0x34
  32 #define TOP_CLK_GATE1   0x38
  33 #define TOP_CLK_GATE2   0x3c
  34 #define TOP_CLK_GATE3   0x40
  35 #define TOP_CLK_GATE4   0x44
  36 #define TOP_CLK_GATE5   0x48
  37 #define TOP_CLK_GATE6   0x4c
  38
  39 #define TOP_CLK_DIV0    0x58
  40
  41 #define PLL_CPU_REG     0x80
  42 #define PLL_VGA_REG     0xb0
  43 #define PLL_DDR_REG     0xa0
  44
  45 /* LSP0 CRM */
  46 #define LSP0_TIMER3_CLK 0x4
  47 #define LSP0_TIMER4_CLK 0x8
  48 #define LSP0_TIMER5_CLK 0xc
  49 #define LSP0_UART3_CLK  0x10
  50 #define LSP0_UART1_CLK  0x14
  51 #define LSP0_UART2_CLK  0x18
  52 #define LSP0_SPIFC0_CLK 0x1c
  53 #define LSP0_I2C4_CLK   0x20
  54 #define LSP0_I2C5_CLK   0x24
  55 #define LSP0_SSP0_CLK   0x28
  56 #define LSP0_SSP1_CLK   0x2c
  57 #define LSP0_USIM0_CLK  0x30
  58 #define LSP0_GPIO_CLK   0x34
  59 #define LSP0_I2C3_CLK   0x38
  60
  61 /* LSP1 CRM */
  62 #define LSP1_UART4_CLK  0x08
  63 #define LSP1_UART5_CLK  0x0c
  64 #define LSP1_PWM_CLK    0x10
  65 #define LSP1_I2C2_CLK   0x14
  66 #define LSP1_SSP2_CLK   0x1c
  67 #define LSP1_SSP3_CLK   0x20
  68 #define LSP1_SSP4_CLK   0x24
  69 #define LSP1_USIM1_CLK  0x28
  70
  71 /* audio lsp */
  72 #define AUDIO_I2S0_DIV_CFG1     0x10
  73 #define AUDIO_I2S0_DIV_CFG2     0x14
  74 #define AUDIO_I2S0_CLK          0x18
  75 #define AUDIO_I2S1_DIV_CFG1     0x20
  76 #define AUDIO_I2S1_DIV_CFG2     0x24
  77 #define AUDIO_I2S1_CLK          0x28
  78 #define AUDIO_I2S2_DIV_CFG1     0x30
  79 #define AUDIO_I2S2_DIV_CFG2     0x34
  80 #define AUDIO_I2S2_CLK          0x38
  81 #define AUDIO_I2S3_DIV_CFG1     0x40
  82 #define AUDIO_I2S3_DIV_CFG2     0x44
  83 #define AUDIO_I2S3_CLK          0x48
  84 #define AUDIO_I2C0_CLK          0x50
  85 #define AUDIO_SPDIF0_DIV_CFG1   0x60
  86 #define AUDIO_SPDIF0_DIV_CFG2   0x64
  87 #define AUDIO_SPDIF0_CLK        0x68
  88 #define AUDIO_SPDIF1_DIV_CFG1   0x70
  89 #define AUDIO_SPDIF1_DIV_CFG2   0x74
  90 #define AUDIO_SPDIF1_CLK        0x78
  91 #define AUDIO_TIMER_CLK         0x80
  92 #define AUDIO_TDM_CLK           0x90
  93 #define AUDIO_TS_CLK            0xa0
  94
  95 static DEFINE_SPINLOCK(clk_lock);
  96
  97 static struct zx_pll_config pll_cpu_table[] = {
  98         PLL_RATE(1312000000, 0x00103621, 0x04aaaaaa),
  99         PLL_RATE(1407000000, 0x00103a21, 0x04aaaaaa),
 100         PLL_RATE(1503000000, 0x00103e21, 0x04aaaaaa),
 101         PLL_RATE(1600000000, 0x00104221, 0x04aaaaaa),
 102 };
 103
 104 PNAME(osc) = {
 105         "osc24m",
 106         "osc32k",
 107 };
 108
 109 PNAME(dbg_wclk_p) = {
 110         "clk334m",
 111         "clk466m",
 112         "clk396m",
 113         "clk250m",
 114 };
 115
 116 PNAME(a72_coreclk_p) = {
 117         "osc24m",
 118         "pll_mm0_1188m",
 119         "pll_mm1_1296m",
 120         "clk1000m",
 121         "clk648m",
 122         "clk1600m",
 123         "pll_audio_1800m",
 124         "pll_vga_1800m",
 125 };
 126
 127 PNAME(cpu_periclk_p) = {
 128         "osc24m",
 129         "clk500m",
 130         "clk594m",
 131         "clk466m",
 132         "clk294m",
 133         "clk334m",
 134         "clk250m",
 135         "clk125m",
 136 };
 137
 138 PNAME(a53_coreclk_p) = {
 139         "osc24m",
 140         "clk1000m",
 141         "pll_mm0_1188m",
 142         "clk648m",
 143         "clk500m",
 144         "clk800m",
 145         "clk1600m",
 146         "pll_audio_1800m",
 147 };
 148
 149 PNAME(sec_wclk_p) = {
 150         "osc24m",
 151         "clk396m",
 152         "clk334m",
 153         "clk297m",
 154         "clk250m",
 155         "clk198m",
 156         "clk148m5",
 157         "clk99m",
 158 };
 159
 160 PNAME(sd_nand_wclk_p) = {
 161         "osc24m",
 162         "clk49m5",
 163         "clk99m",
 164         "clk198m",
 165         "clk167m",
 166         "clk148m5",
 167         "clk125m",
 168         "clk216m",
 169 };
 170
 171 PNAME(emmc_wclk_p) = {
 172         "osc24m",
 173         "clk198m",
 174         "clk99m",
 175         "clk396m",
 176         "clk334m",
 177         "clk297m",
 178         "clk250m",
 179         "clk148m5",
 180 };
 181
 182 PNAME(clk32_p) = {
 183         "osc32k",
 184         "clk32k768",
 185 };
 186
 187 PNAME(usb_ref24m_p) = {
 188         "osc32k",
 189         "clk32k768",
 190 };
 191
 192 PNAME(sys_noc_alck_p) = {
 193         "osc24m",
 194         "clk250m",
 195         "clk198m",
 196         "clk148m5",
 197         "clk108m",
 198         "clk54m",
 199         "clk216m",
 200         "clk240m",
 201 };
 202
 203 PNAME(vde_aclk_p) = {
 204         "clk334m",
 205         "clk594m",
 206         "clk500m",
 207         "clk432m",
 208         "clk480m",
 209         "clk297m",
 210         "clk_vga",  /*600MHz*/
 211         "clk294m",
 212 };
 213
 214 PNAME(vce_aclk_p) = {
 215         "clk334m",
 216         "clk594m",
 217         "clk500m",
 218         "clk432m",
 219         "clk396m",
 220         "clk297m",
 221         "clk_vga",  /*600MHz*/
 222         "clk294m",
 223 };
 224
 225 PNAME(hde_aclk_p) = {
 226         "clk334m",
 227         "clk594m",
 228         "clk500m",
 229         "clk432m",
 230         "clk396m",
 231         "clk297m",
 232         "clk_vga",  /*600MHz*/
 233         "clk294m",
 234 };
 235
 236 PNAME(gpu_aclk_p) = {
 237         "clk334m",
 238         "clk648m",
 239         "clk594m",
 240         "clk500m",
 241         "clk396m",
 242         "clk297m",
 243         "clk_vga",  /*600MHz*/
 244         "clk294m",
 245 };
 246
 247 PNAME(sappu_aclk_p) = {
 248         "clk396m",
 249         "clk500m",
 250         "clk250m",
 251         "clk148m5",
 252 };
 253
 254 PNAME(sappu_wclk_p) = {
 255         "clk198m",
 256         "clk396m",
 257         "clk334m",
 258         "clk297m",
 259         "clk250m",
 260         "clk148m5",
 261         "clk125m",
 262         "clk99m",
 263 };
 264
 265 PNAME(vou_aclk_p) = {
 266         "clk334m",
 267         "clk594m",
 268         "clk500m",
 269         "clk432m",
 270         "clk396m",
 271         "clk297m",
 272         "clk_vga",  /*600MHz*/
 273         "clk294m",
 274 };
 275
 276 PNAME(vou_main_wclk_p) = {
 277         "clk108m",
 278         "clk594m",
 279         "clk297m",
 280         "clk148m5",
 281         "clk74m25",
 282         "clk54m",
 283         "clk27m",
 284         "clk_vga",
 285 };
 286
 287 PNAME(vou_aux_wclk_p) = {
 288         "clk108m",
 289         "clk148m5",
 290         "clk74m25",
 291         "clk54m",
 292         "clk27m",
 293         "clk_vga",
 294         "clk54m_mm0",
 295         "clk"
 296 };
 297
 298 PNAME(vou_ppu_wclk_p) = {
 299         "clk334m",
 300         "clk432m",
 301         "clk396m",
 302         "clk297m",
 303         "clk250m",
 304         "clk125m",
 305         "clk198m",
 306         "clk99m",
 307 };
 308
 309 PNAME(vga_i2c_wclk_p) = {
 310         "osc24m",
 311         "clk99m",
 312 };
 313
 314 PNAME(viu_m0_aclk_p) = {
 315         "clk334m",
 316         "clk432m",
 317         "clk396m",
 318         "clk297m",
 319         "clk250m",
 320         "clk125m",
 321         "clk198m",
 322         "osc24m",
 323 };
 324
 325 PNAME(viu_m1_aclk_p) = {
 326         "clk198m",
 327         "clk250m",
 328         "clk297m",
 329         "clk125m",
 330         "clk396m",
 331         "clk334m",
 332         "clk148m5",
 333         "osc24m",
 334 };
 335
 336 PNAME(viu_clk_p) = {
 337         "clk198m",
 338         "clk334m",
 339         "clk297m",
 340         "clk250m",
 341         "clk396m",
 342         "clk125m",
 343         "clk99m",
 344         "clk148m5",
 345 };
 346
 347 PNAME(viu_jpeg_clk_p) = {
 348         "clk334m",
 349         "clk480m",
 350         "clk432m",
 351         "clk396m",
 352         "clk297m",
 353         "clk250m",
 354         "clk125m",
 355         "clk198m",
 356 };
 357
 358 PNAME(ts_sys_clk_p) = {
 359         "clk192m",
 360         "clk167m",
 361         "clk125m",
 362         "clk99m",
 363 };
 364
 365 PNAME(wdt_ares_p) = {
 366         "osc24m",
 367         "clk32k"
 368 };
 369
 370 static struct clk_zx_pll zx296718_pll_clk[] = {
 371         ZX296718_PLL("pll_cpu", "osc24m",       PLL_CPU_REG,    pll_cpu_table),
 372 };
 373
 374 static struct zx_clk_fixed_factor top_ffactor_clk[] = {
 375         FFACTOR(0, "clk4m",             "osc24m", 1, 6,  0),
 376         FFACTOR(0, "clk2m",             "osc24m", 1, 12, 0),
 377         /* pll cpu */
 378         FFACTOR(0, "clk1600m",          "pll_cpu", 1, 1, CLK_SET_RATE_PARENT),
 379         FFACTOR(0, "clk800m",           "pll_cpu", 1, 2, CLK_SET_RATE_PARENT),
 380         /* pll mac */
 381         FFACTOR(0, "clk25m",            "pll_mac", 1, 40, 0),
 382         FFACTOR(0, "clk125m",           "pll_mac", 1, 8, 0),
 383         FFACTOR(0, "clk250m",           "pll_mac", 1, 4, 0),
 384         FFACTOR(0, "clk50m",            "pll_mac", 1, 20, 0),
 385         FFACTOR(0, "clk500m",           "pll_mac", 1, 2, 0),
 386         FFACTOR(0, "clk1000m",          "pll_mac", 1, 1, 0),
 387         FFACTOR(0, "clk334m",           "pll_mac", 1, 3, 0),
 388         FFACTOR(0, "clk167m",           "pll_mac", 1, 6, 0),
 389         /* pll mm */
 390         FFACTOR(0, "clk54m_mm0",        "pll_mm0", 1, 22, 0),
 391         FFACTOR(0, "clk74m25",          "pll_mm0", 1, 16, 0),
 392         FFACTOR(0, "clk148m5",          "pll_mm0", 1, 8, 0),
 393         FFACTOR(0, "clk297m",           "pll_mm0", 1, 4, 0),
 394         FFACTOR(0, "clk594m",           "pll_mm0", 1, 2, 0),
 395         FFACTOR(0, "pll_mm0_1188m",     "pll_mm0", 1, 1, 0),
 396         FFACTOR(0, "clk396m",           "pll_mm0", 1, 3, 0),
 397         FFACTOR(0, "clk198m",           "pll_mm0", 1, 6, 0),
 398         FFACTOR(0, "clk99m",            "pll_mm0", 1, 12, 0),
 399         FFACTOR(0, "clk49m5",           "pll_mm0", 1, 24, 0),
 400         /* pll mm */
 401         FFACTOR(0, "clk324m",           "pll_mm1", 1, 4, 0),
 402         FFACTOR(0, "clk648m",           "pll_mm1", 1, 2, 0),
 403         FFACTOR(0, "pll_mm1_1296m",     "pll_mm1", 1, 1, 0),
 404         FFACTOR(0, "clk216m",           "pll_mm1", 1, 6, 0),
 405         FFACTOR(0, "clk432m",           "pll_mm1", 1, 3, 0),
 406         FFACTOR(0, "clk108m",           "pll_mm1", 1, 12, 0),
 407         FFACTOR(0, "clk72m",            "pll_mm1", 1, 18, 0),
 408         FFACTOR(0, "clk27m",            "pll_mm1", 1, 48, 0),
 409         FFACTOR(0, "clk54m",            "pll_mm1", 1, 24, 0),
 410         /* vga */
 411         FFACTOR(0, "pll_vga_1800m",     "pll_vga", 1, 1, 0),
 412         FFACTOR(0, "clk_vga",           "pll_vga", 1, 2, 0),
 413         /* pll ddr */
 414         FFACTOR(0, "clk466m",           "pll_ddr", 1, 2, 0),
 415
 416         /* pll audio */
 417         FFACTOR(0, "pll_audio_1800m",   "pll_audio", 1, 1, 0),
 418         FFACTOR(0, "clk32k768",         "pll_audio", 1, 27000, 0),
 419         FFACTOR(0, "clk16m384",         "pll_audio", 1, 54, 0),
 420         FFACTOR(0, "clk294m",           "pll_audio", 1, 3, 0),
 421
 422         /* pll hsic*/
 423         FFACTOR(0, "clk240m",           "pll_hsic", 1, 4, 0),
 424         FFACTOR(0, "clk480m",           "pll_hsic", 1, 2, 0),
 425         FFACTOR(0, "clk192m",           "pll_hsic", 1, 5, 0),
 426         FFACTOR(0, "clk_pll_24m",       "pll_hsic", 1, 40, 0),
 427         FFACTOR(0, "emmc_mux_div2",     "emmc_mux", 1, 2, CLK_SET_RATE_PARENT),
 428 };
 429
 430 static struct clk_div_table noc_div_table[] = {
 431         { .val = 1, .div = 2, },
 432         { .val = 3, .div = 4, },
 433 };
 434 static struct zx_clk_div top_div_clk[] = {
 435         DIV_T(0, "sys_noc_hclk", "sys_noc_aclk", TOP_CLK_DIV0, 0, 2, 0, noc_div_table),
 436         DIV_T(0, "sys_noc_pclk", "sys_noc_aclk", TOP_CLK_DIV0, 4, 2, 0, noc_div_table),
 437 };
 438
 439 static struct zx_clk_mux top_mux_clk[] = {
 440         MUX(0, "dbg_mux",        dbg_wclk_p,      TOP_CLK_MUX0, 12, 2),
 441         MUX(0, "a72_mux",        a72_coreclk_p,   TOP_CLK_MUX0, 8, 3),
 442         MUX(0, "cpu_peri_mux",   cpu_periclk_p,   TOP_CLK_MUX0, 4, 3),
 443         MUX_F(0, "a53_mux",      a53_coreclk_p,   TOP_CLK_MUX0, 0, 3, CLK_SET_RATE_PARENT, 0),
 444         MUX(0, "sys_noc_aclk",   sys_noc_alck_p,  TOP_CLK_MUX1, 0, 3),
 445         MUX(0, "sec_mux",        sec_wclk_p,      TOP_CLK_MUX2, 16, 3),
 446         MUX(0, "sd1_mux",        sd_nand_wclk_p,  TOP_CLK_MUX2, 12, 3),
 447         MUX(0, "sd0_mux",        sd_nand_wclk_p,  TOP_CLK_MUX2, 8, 3),
 448         MUX(0, "emmc_mux",       emmc_wclk_p,     TOP_CLK_MUX2, 4, 3),
 449         MUX(0, "nand_mux",       sd_nand_wclk_p,  TOP_CLK_MUX2, 0, 3),
 450         MUX(0, "usb_ref24m_mux", usb_ref24m_p,    TOP_CLK_MUX9, 16, 1),
 451         MUX(0, "clk32k",         clk32_p,         TOP_CLK_MUX9, 12, 1),
 452         MUX_F(0, "wdt_mux",      wdt_ares_p,      TOP_CLK_MUX9, 8, 1, CLK_SET_RATE_PARENT, 0),
 453         MUX(0, "timer_mux",      osc,             TOP_CLK_MUX9, 4, 1),
 454         MUX(0, "vde_mux",        vde_aclk_p,      TOP_CLK_MUX4,  0, 3),
 455         MUX(0, "vce_mux",        vce_aclk_p,      TOP_CLK_MUX4,  4, 3),
 456         MUX(0, "hde_mux",        hde_aclk_p,      TOP_CLK_MUX4,  8, 3),
 457         MUX(0, "gpu_mux",        gpu_aclk_p,      TOP_CLK_MUX5,  0, 3),
 458         MUX(0, "sappu_a_mux",    sappu_aclk_p,    TOP_CLK_MUX5,  4, 2),
 459         MUX(0, "sappu_w_mux",    sappu_wclk_p,    TOP_CLK_MUX5,  8, 3),
 460         MUX(0, "vou_a_mux",      vou_aclk_p,      TOP_CLK_MUX7,  0, 3),
 461         MUX(0, "vou_main_w_mux", vou_main_wclk_p, TOP_CLK_MUX7,  4, 3),
 462         MUX(0, "vou_aux_w_mux",  vou_aux_wclk_p,  TOP_CLK_MUX7,  8, 3),
 463         MUX(0, "vou_ppu_w_mux",  vou_ppu_wclk_p,  TOP_CLK_MUX7, 12, 3),
 464         MUX(0, "vga_i2c_mux",    vga_i2c_wclk_p,  TOP_CLK_MUX7, 16, 1),
 465         MUX(0, "viu_m0_a_mux",   viu_m0_aclk_p,   TOP_CLK_MUX6,  0, 3),
 466         MUX(0, "viu_m1_a_mux",   viu_m1_aclk_p,   TOP_CLK_MUX6,  4, 3),
 467         MUX(0, "viu_w_mux",      viu_clk_p,       TOP_CLK_MUX6,  8, 3),
 468         MUX(0, "viu_jpeg_w_mux", viu_jpeg_clk_p,  TOP_CLK_MUX6, 12, 3),
 469         MUX(0, "ts_sys_mux",     ts_sys_clk_p,    TOP_CLK_MUX6, 16, 2),
 470 };
 471
 472 static struct zx_clk_gate top_gate_clk[] = {
 473         GATE(CPU_DBG_GATE,    "dbg_wclk",        "dbg_mux",        TOP_CLK_GATE0, 4, CLK_SET_RATE_PARENT, 0),
 474         GATE(A72_GATE,        "a72_coreclk",     "a72_mux",        TOP_CLK_GATE0, 3, CLK_SET_RATE_PARENT, 0),
 475         GATE(CPU_PERI_GATE,   "cpu_peri",        "cpu_peri_mux",   TOP_CLK_GATE0, 1, CLK_SET_RATE_PARENT, 0),
 476         GATE(A53_GATE,        "a53_coreclk",     "a53_mux",        TOP_CLK_GATE0, 0, CLK_SET_RATE_PARENT, 0),
 477         GATE(SD1_WCLK,        "sd1_wclk",        "sd1_mux",        TOP_CLK_GATE1, 13, CLK_SET_RATE_PARENT, 0),
 478         GATE(SD0_WCLK,        "sd0_wclk",        "sd0_mux",        TOP_CLK_GATE1, 9, CLK_SET_RATE_PARENT, 0),
 479         GATE(EMMC_WCLK,       "emmc_wclk",       "emmc_mux_div2",  TOP_CLK_GATE0, 5, CLK_SET_RATE_PARENT, 0),
 480         GATE(EMMC_NAND_AXI,   "emmc_nand_aclk",  "sys_noc_aclk",   TOP_CLK_GATE1, 4, CLK_SET_RATE_PARENT, 0),
 481         GATE(NAND_WCLK,       "nand_wclk",       "nand_mux",       TOP_CLK_GATE0, 1, CLK_SET_RATE_PARENT, 0),
 482         GATE(EMMC_NAND_AHB,   "emmc_nand_hclk",  "sys_noc_hclk",   TOP_CLK_GATE1, 0, CLK_SET_RATE_PARENT, 0),
 483         GATE(0,               "lsp1_pclk",       "sys_noc_pclk",   TOP_CLK_GATE2, 31, 0,                  0),
 484         GATE(LSP1_148M5,      "lsp1_148m5",      "clk148m5",       TOP_CLK_GATE2, 30, 0,                  0),
 485         GATE(LSP1_99M,        "lsp1_99m",        "clk99m",         TOP_CLK_GATE2, 29, 0,                  0),
 486         GATE(LSP1_24M,        "lsp1_24m",        "osc24m",         TOP_CLK_GATE2, 28, 0,                  0),
 487         GATE(LSP0_74M25,      "lsp0_74m25",      "clk74m25",       TOP_CLK_GATE2, 25, 0,                  0),
 488         GATE(0,               "lsp0_pclk",       "sys_noc_pclk",   TOP_CLK_GATE2, 24, 0,                  0),
 489         GATE(LSP0_32K,        "lsp0_32k",        "osc32k",         TOP_CLK_GATE2, 23, 0,                  0),
 490         GATE(LSP0_148M5,      "lsp0_148m5",      "clk148m5",       TOP_CLK_GATE2, 22, 0,                  0),
 491         GATE(LSP0_99M,        "lsp0_99m",        "clk99m",         TOP_CLK_GATE2, 21, 0,                  0),
 492         GATE(LSP0_24M,        "lsp0_24m",        "osc24m",         TOP_CLK_GATE2, 20, 0,                  0),
 493         GATE(AUDIO_99M,       "audio_99m",       "clk99m",         TOP_CLK_GATE5, 27, 0,                  0),
 494         GATE(AUDIO_24M,       "audio_24m",       "osc24m",         TOP_CLK_GATE5, 28, 0,                  0),
 495         GATE(AUDIO_16M384,    "audio_16m384",    "clk16m384",      TOP_CLK_GATE5, 29, 0,                  0),
 496         GATE(AUDIO_32K,       "audio_32k",       "clk32k",         TOP_CLK_GATE5, 30, 0,                  0),
 497         GATE(WDT_WCLK,        "wdt_wclk",        "wdt_mux",        TOP_CLK_GATE6, 9, CLK_SET_RATE_PARENT, 0),
 498         GATE(TIMER_WCLK,      "timer_wclk",      "timer_mux",      TOP_CLK_GATE6, 5, CLK_SET_RATE_PARENT, 0),
 499         GATE(VDE_ACLK,        "vde_aclk",        "vde_mux",        TOP_CLK_GATE3, 0,  CLK_SET_RATE_PARENT, 0),
 500         GATE(VCE_ACLK,        "vce_aclk",        "vce_mux",        TOP_CLK_GATE3, 4,  CLK_SET_RATE_PARENT, 0),
 501         GATE(HDE_ACLK,        "hde_aclk",        "hde_mux",        TOP_CLK_GATE3, 8,  CLK_SET_RATE_PARENT, 0),
 502         GATE(GPU_ACLK,        "gpu_aclk",        "gpu_mux",        TOP_CLK_GATE3, 16, CLK_SET_RATE_PARENT, 0),
 503         GATE(SAPPU_ACLK,      "sappu_aclk",      "sappu_a_mux",    TOP_CLK_GATE3, 20, CLK_SET_RATE_PARENT, 0),
 504         GATE(SAPPU_WCLK,      "sappu_wclk",      "sappu_w_mux",    TOP_CLK_GATE3, 22, CLK_SET_RATE_PARENT, 0),
 505         GATE(VOU_ACLK,        "vou_aclk",        "vou_a_mux",      TOP_CLK_GATE4, 16, CLK_SET_RATE_PARENT, 0),
 506         GATE(VOU_MAIN_WCLK,   "vou_main_wclk",   "vou_main_w_mux", TOP_CLK_GATE4, 18, CLK_SET_RATE_PARENT, 0),
 507         GATE(VOU_AUX_WCLK,    "vou_aux_wclk",    "vou_aux_w_mux",  TOP_CLK_GATE4, 19, CLK_SET_RATE_PARENT, 0),
 508         GATE(VOU_PPU_WCLK,    "vou_ppu_wclk",    "vou_ppu_w_mux",  TOP_CLK_GATE4, 20, CLK_SET_RATE_PARENT, 0),
 509         GATE(MIPI_CFG_CLK,    "mipi_cfg_clk",    "osc24m",         TOP_CLK_GATE4, 21, 0,                   0),
 510         GATE(VGA_I2C_WCLK,    "vga_i2c_wclk",    "vga_i2c_mux",    TOP_CLK_GATE4, 23, CLK_SET_RATE_PARENT, 0),
 511         GATE(MIPI_REF_CLK,    "mipi_ref_clk",    "clk27m",         TOP_CLK_GATE4, 24, 0,                   0),
 512         GATE(HDMI_OSC_CEC,    "hdmi_osc_cec",    "clk2m",          TOP_CLK_GATE4, 22, 0,                   0),
 513         GATE(HDMI_OSC_CLK,    "hdmi_osc_clk",    "clk240m",        TOP_CLK_GATE4, 25, 0,                   0),
 514         GATE(HDMI_XCLK,       "hdmi_xclk",       "osc24m",         TOP_CLK_GATE4, 26, 0,                   0),
 515         GATE(VIU_M0_ACLK,     "viu_m0_aclk",     "viu_m0_a_mux",   TOP_CLK_GATE4, 0,  CLK_SET_RATE_PARENT, 0),
 516         GATE(VIU_M1_ACLK,     "viu_m1_aclk",     "viu_m1_a_mux",   TOP_CLK_GATE4, 1,  CLK_SET_RATE_PARENT, 0),
 517         GATE(VIU_WCLK,        "viu_wclk",        "viu_w_mux",      TOP_CLK_GATE4, 2,  CLK_SET_RATE_PARENT, 0),
 518         GATE(VIU_JPEG_WCLK,   "viu_jpeg_wclk",   "viu_jpeg_w_mux", TOP_CLK_GATE4, 3,  CLK_SET_RATE_PARENT, 0),
 519         GATE(VIU_CFG_CLK,     "viu_cfg_clk",     "osc24m",         TOP_CLK_GATE4, 6,  0,                   0),
 520         GATE(TS_SYS_WCLK,     "ts_sys_wclk",     "ts_sys_mux",     TOP_CLK_GATE5, 2,  CLK_SET_RATE_PARENT, 0),
 521         GATE(TS_SYS_108M,     "ts_sys_108m",     "clk108m",        TOP_CLK_GATE5, 3,  0,                   0),
 522         GATE(USB20_HCLK,      "usb20_hclk",      "sys_noc_hclk",   TOP_CLK_GATE2, 12, 0,                   0),
 523         GATE(USB20_PHY_CLK,   "usb20_phy_clk",   "usb_ref24m_mux", TOP_CLK_GATE2, 13, 0,                   0),
 524         GATE(USB21_HCLK,      "usb21_hclk",      "sys_noc_hclk",   TOP_CLK_GATE2, 14, 0,                   0),
 525         GATE(USB21_PHY_CLK,   "usb21_phy_clk",   "usb_ref24m_mux", TOP_CLK_GATE2, 15, 0,                   0),
 526         GATE(GMAC_RMIICLK,    "gmac_rmii_clk",   "clk50m",         TOP_CLK_GATE2, 3, 0,                    0),
 527         GATE(GMAC_PCLK,       "gmac_pclk",       "clk198m",        TOP_CLK_GATE2, 1, 0,                    0),
 528         GATE(GMAC_ACLK,       "gmac_aclk",       "clk49m5",        TOP_CLK_GATE2, 0, 0,                    0),
 529         GATE(GMAC_RFCLK,      "gmac_refclk",     "clk25m",         TOP_CLK_GATE2, 4, 0,                    0),
 530         GATE(SD1_AHB,         "sd1_hclk",        "sys_noc_hclk",   TOP_CLK_GATE1, 12,  0,                  0),
 531         GATE(SD0_AHB,         "sd0_hclk",        "sys_noc_hclk",   TOP_CLK_GATE1, 8,  0,                   0),
 532         GATE(TEMPSENSOR_GATE, "tempsensor_gate", "clk4m",          TOP_CLK_GATE5, 31,  0,                  0),
 533 };
 534
 535 static struct clk_hw_onecell_data top_hw_onecell_data = {
 536         .num = TOP_NR_CLKS,
 537         .hws = {
 538                 [TOP_NR_CLKS - 1] = NULL,
 539         },
 540 };
 541
 542 static int __init top_clocks_init(struct device_node *np)
 543 {
 544         void __iomem *reg_base;
 545         int i, ret;
 546
 547         reg_base = of_iomap(np, 0);
 548         if (!reg_base) {
 549                 pr_err("%s: Unable to map clk base\n", __func__);
 550                 return -ENXIO;
 551         }
 552
 553         for (i = 0; i < ARRAY_SIZE(zx296718_pll_clk); i++) {
 554                 zx296718_pll_clk[i].reg_base += (uintptr_t)reg_base;
 555                 ret = clk_hw_register(NULL, &zx296718_pll_clk[i].hw);
 556                 if (ret) {
 557                         pr_warn("top clk %s init error!\n",
 558                                 zx296718_pll_clk[i].hw.init->name);
 559                 }
 560         }
 561
 562         for (i = 0; i < ARRAY_SIZE(top_ffactor_clk); i++) {
 563                 if (top_ffactor_clk[i].id)
 564                         top_hw_onecell_data.hws[top_ffactor_clk[i].id] =
 565                                         &top_ffactor_clk[i].factor.hw;
 566
 567                 ret = clk_hw_register(NULL, &top_ffactor_clk[i].factor.hw);
 568                 if (ret) {
 569                         pr_warn("top clk %s init error!\n",
 570                                 top_ffactor_clk[i].factor.hw.init->name);
 571                 }
 572         }
 573
 574         for (i = 0; i < ARRAY_SIZE(top_mux_clk); i++) {
 575                 if (top_mux_clk[i].id)
 576                         top_hw_onecell_data.hws[top_mux_clk[i].id] =
 577                                         &top_mux_clk[i].mux.hw;
 578
 579                 top_mux_clk[i].mux.reg += (uintptr_t)reg_base;
 580                 ret = clk_hw_register(NULL, &top_mux_clk[i].mux.hw);
 581                 if (ret) {
 582                         pr_warn("top clk %s init error!\n",
 583                                 top_mux_clk[i].mux.hw.init->name);
 584                 }
 585         }
 586
 587         for (i = 0; i < ARRAY_SIZE(top_gate_clk); i++) {
 588                 if (top_gate_clk[i].id)
 589                         top_hw_onecell_data.hws[top_gate_clk[i].id] =
 590                                         &top_gate_clk[i].gate.hw;
 591
 592                 top_gate_clk[i].gate.reg += (uintptr_t)reg_base;
 593                 ret = clk_hw_register(NULL, &top_gate_clk[i].gate.hw);
 594                 if (ret) {
 595                         pr_warn("top clk %s init error!\n",
 596                                 top_gate_clk[i].gate.hw.init->name);
 597                 }
 598         }
 599
 600         for (i = 0; i < ARRAY_SIZE(top_div_clk); i++) {
 601                 if (top_div_clk[i].id)
 602                         top_hw_onecell_data.hws[top_div_clk[i].id] =
 603                                         &top_div_clk[i].div.hw;
 604
 605                 top_div_clk[i].div.reg += (uintptr_t)reg_base;
 606                 ret = clk_hw_register(NULL, &top_div_clk[i].div.hw);
 607                 if (ret) {
 608                         pr_warn("top clk %s init error!\n",
 609                                 top_div_clk[i].div.hw.init->name);
 610                 }
 611         }
 612
 613         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
 614                                      &top_hw_onecell_data);
 615         if (ret) {
 616                 pr_err("failed to register top clk provider: %d\n", ret);
 617                 return ret;
 618         }
 619
 620         return 0;
 621 }
 622
 623 static struct clk_div_table common_even_div_table[] = {
 624         { .val = 0, .div = 1, },
 625         { .val = 1, .div = 2, },
 626         { .val = 3, .div = 4, },
 627         { .val = 5, .div = 6, },
 628         { .val = 7, .div = 8, },
 629         { .val = 9, .div = 10, },
 630         { .val = 11, .div = 12, },
 631         { .val = 13, .div = 14, },
 632         { .val = 15, .div = 16, },
 633 };
 634
 635 static struct clk_div_table common_div_table[] = {
 636         { .val = 0, .div = 1, },
 637         { .val = 1, .div = 2, },
 638         { .val = 2, .div = 3, },
 639         { .val = 3, .div = 4, },
 640         { .val = 4, .div = 5, },
 641         { .val = 5, .div = 6, },
 642         { .val = 6, .div = 7, },
 643         { .val = 7, .div = 8, },
 644         { .val = 8, .div = 9, },
 645         { .val = 9, .div = 10, },
 646         { .val = 10, .div = 11, },
 647         { .val = 11, .div = 12, },
 648         { .val = 12, .div = 13, },
 649         { .val = 13, .div = 14, },
 650         { .val = 14, .div = 15, },
 651         { .val = 15, .div = 16, },
 652 };
 653
 654 PNAME(lsp0_wclk_common_p) = {
 655         "lsp0_24m",
 656         "lsp0_99m",
 657 };
 658
 659 PNAME(lsp0_wclk_timer3_p) = {
 660         "timer3_div",
 661         "lsp0_32k"
 662 };
 663
 664 PNAME(lsp0_wclk_timer4_p) = {
 665         "timer4_div",
 666         "lsp0_32k"
 667 };
 668
 669 PNAME(lsp0_wclk_timer5_p) = {
 670         "timer5_div",
 671         "lsp0_32k"
 672 };
 673
 674 PNAME(lsp0_wclk_spifc0_p) = {
 675         "lsp0_148m5",
 676         "lsp0_24m",
 677         "lsp0_99m",
 678         "lsp0_74m25"
 679 };
 680
 681 PNAME(lsp0_wclk_ssp_p) = {
 682         "lsp0_148m5",
 683         "lsp0_99m",
 684         "lsp0_24m",
 685 };
 686
 687 static struct zx_clk_mux lsp0_mux_clk[] = {
 688         MUX(0, "timer3_wclk_mux", lsp0_wclk_timer3_p, LSP0_TIMER3_CLK, 4, 1),
 689         MUX(0, "timer4_wclk_mux", lsp0_wclk_timer4_p, LSP0_TIMER4_CLK, 4, 1),
 690         MUX(0, "timer5_wclk_mux", lsp0_wclk_timer5_p, LSP0_TIMER5_CLK, 4, 1),
 691         MUX(0, "uart3_wclk_mux",  lsp0_wclk_common_p, LSP0_UART3_CLK,  4, 1),
 692         MUX(0, "uart1_wclk_mux",  lsp0_wclk_common_p, LSP0_UART1_CLK,  4, 1),
 693         MUX(0, "uart2_wclk_mux",  lsp0_wclk_common_p, LSP0_UART2_CLK,  4, 1),
 694         MUX(0, "spifc0_wclk_mux", lsp0_wclk_spifc0_p, LSP0_SPIFC0_CLK, 4, 2),
 695         MUX(0, "i2c4_wclk_mux",   lsp0_wclk_common_p, LSP0_I2C4_CLK,   4, 1),
 696         MUX(0, "i2c5_wclk_mux",   lsp0_wclk_common_p, LSP0_I2C5_CLK,   4, 1),
 697         MUX(0, "ssp0_wclk_mux",   lsp0_wclk_ssp_p,    LSP0_SSP0_CLK,   4, 1),
 698         MUX(0, "ssp1_wclk_mux",   lsp0_wclk_ssp_p,    LSP0_SSP1_CLK,   4, 1),
 699         MUX(0, "i2c3_wclk_mux",   lsp0_wclk_common_p, LSP0_I2C3_CLK,   4, 1),
 700 };
 701
 702 static struct zx_clk_gate lsp0_gate_clk[] = {
 703         GATE(LSP0_TIMER3_WCLK, "timer3_wclk", "timer3_wclk_mux", LSP0_TIMER3_CLK, 1, CLK_SET_RATE_PARENT, 0),
 704         GATE(LSP0_TIMER4_WCLK, "timer4_wclk", "timer4_wclk_mux", LSP0_TIMER4_CLK, 1, CLK_SET_RATE_PARENT, 0),
 705         GATE(LSP0_TIMER5_WCLK, "timer5_wclk", "timer5_wclk_mux", LSP0_TIMER5_CLK, 1, CLK_SET_RATE_PARENT, 0),
 706         GATE(LSP0_UART3_WCLK,  "uart3_wclk",  "uart3_wclk_mux",  LSP0_UART3_CLK,  1, CLK_SET_RATE_PARENT, 0),
 707         GATE(LSP0_UART1_WCLK,  "uart1_wclk",  "uart1_wclk_mux",  LSP0_UART1_CLK,  1, CLK_SET_RATE_PARENT, 0),
 708         GATE(LSP0_UART2_WCLK,  "uart2_wclk",  "uart2_wclk_mux",  LSP0_UART2_CLK,  1, CLK_SET_RATE_PARENT, 0),
 709         GATE(LSP0_SPIFC0_WCLK, "spifc0_wclk", "spifc0_wclk_mux", LSP0_SPIFC0_CLK, 1, CLK_SET_RATE_PARENT, 0),
 710         GATE(LSP0_I2C4_WCLK,   "i2c4_wclk",   "i2c4_wclk_mux",   LSP0_I2C4_CLK,   1, CLK_SET_RATE_PARENT, 0),
 711         GATE(LSP0_I2C5_WCLK,   "i2c5_wclk",   "i2c5_wclk_mux",   LSP0_I2C5_CLK,   1, CLK_SET_RATE_PARENT, 0),
 712         GATE(LSP0_SSP0_WCLK,   "ssp0_wclk",   "ssp0_div",        LSP0_SSP0_CLK,   1, CLK_SET_RATE_PARENT, 0),
 713         GATE(LSP0_SSP1_WCLK,   "ssp1_wclk",   "ssp1_div",        LSP0_SSP1_CLK,   1, CLK_SET_RATE_PARENT, 0),
 714         GATE(LSP0_I2C3_WCLK,   "i2c3_wclk",   "i2c3_wclk_mux",   LSP0_I2C3_CLK,   1, CLK_SET_RATE_PARENT, 0),
 715 };
 716
 717 static struct zx_clk_div lsp0_div_clk[] = {
 718         DIV_T(0, "timer3_div", "lsp0_24m", LSP0_TIMER3_CLK,  12, 4, 0, common_even_div_table),
 719         DIV_T(0, "timer4_div", "lsp0_24m", LSP0_TIMER4_CLK,  12, 4, 0, common_even_div_table),
 720         DIV_T(0, "timer5_div", "lsp0_24m", LSP0_TIMER5_CLK,  12, 4, 0, common_even_div_table),
 721         DIV_T(0, "ssp0_div", "ssp0_wclk_mux", LSP0_SSP0_CLK, 12, 4, 0, common_even_div_table),
 722         DIV_T(0, "ssp1_div", "ssp1_wclk_mux", LSP0_SSP1_CLK, 12, 4, 0, common_even_div_table),
 723 };
 724
 725 static struct clk_hw_onecell_data lsp0_hw_onecell_data = {
 726         .num = LSP0_NR_CLKS,
 727         .hws = {
 728                 [LSP0_NR_CLKS - 1] = NULL,
 729         },
 730 };
 731
 732 static int __init lsp0_clocks_init(struct device_node *np)
 733 {
 734         void __iomem *reg_base;
 735         int i, ret;
 736
 737         reg_base = of_iomap(np, 0);
 738         if (!reg_base) {
 739                 pr_err("%s: Unable to map clk base\n", __func__);
 740                 return -ENXIO;
 741         }
 742
 743         for (i = 0; i < ARRAY_SIZE(lsp0_mux_clk); i++) {
 744                 if (lsp0_mux_clk[i].id)
 745                         lsp0_hw_onecell_data.hws[lsp0_mux_clk[i].id] =
 746                                         &lsp0_mux_clk[i].mux.hw;
 747
 748                 lsp0_mux_clk[i].mux.reg += (uintptr_t)reg_base;
 749                 ret = clk_hw_register(NULL, &lsp0_mux_clk[i].mux.hw);
 750                 if (ret) {
 751                         pr_warn("lsp0 clk %s init error!\n",
 752                                 lsp0_mux_clk[i].mux.hw.init->name);
 753                 }
 754         }
 755
 756         for (i = 0; i < ARRAY_SIZE(lsp0_gate_clk); i++) {
 757                 if (lsp0_gate_clk[i].id)
 758                         lsp0_hw_onecell_data.hws[lsp0_gate_clk[i].id] =
 759                                         &lsp0_gate_clk[i].gate.hw;
 760
 761                 lsp0_gate_clk[i].gate.reg += (uintptr_t)reg_base;
 762                 ret = clk_hw_register(NULL, &lsp0_gate_clk[i].gate.hw);
 763                 if (ret) {
 764                         pr_warn("lsp0 clk %s init error!\n",
 765                                 lsp0_gate_clk[i].gate.hw.init->name);
 766                 }
 767         }
 768
 769         for (i = 0; i < ARRAY_SIZE(lsp0_div_clk); i++) {
 770                 if (lsp0_div_clk[i].id)
 771                         lsp0_hw_onecell_data.hws[lsp0_div_clk[i].id] =
 772                                         &lsp0_div_clk[i].div.hw;
 773
 774                 lsp0_div_clk[i].div.reg += (uintptr_t)reg_base;
 775                 ret = clk_hw_register(NULL, &lsp0_div_clk[i].div.hw);
 776                 if (ret) {
 777                         pr_warn("lsp0 clk %s init error!\n",
 778                                 lsp0_div_clk[i].div.hw.init->name);
 779                 }
 780         }
 781
 782         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
 783                                      &lsp0_hw_onecell_data);
 784         if (ret) {
 785                 pr_err("failed to register lsp0 clk provider: %d\n", ret);
 786                 return ret;
 787         }
 788
 789         return 0;
 790 }
 791
 792 PNAME(lsp1_wclk_common_p) = {
 793         "lsp1_24m",
 794         "lsp1_99m",
 795 };
 796
 797 PNAME(lsp1_wclk_ssp_p) = {
 798         "lsp1_148m5",
 799         "lsp1_99m",
 800         "lsp1_24m",
 801 };
 802
 803 static struct zx_clk_mux lsp1_mux_clk[] = {
 804         MUX(0, "uart4_wclk_mux", lsp1_wclk_common_p, LSP1_UART4_CLK, 4, 1),
 805         MUX(0, "uart5_wclk_mux", lsp1_wclk_common_p, LSP1_UART5_CLK, 4, 1),
 806         MUX(0, "pwm_wclk_mux",   lsp1_wclk_common_p, LSP1_PWM_CLK,   4, 1),
 807         MUX(0, "i2c2_wclk_mux",  lsp1_wclk_common_p, LSP1_I2C2_CLK,  4, 1),
 808         MUX(0, "ssp2_wclk_mux",  lsp1_wclk_ssp_p,    LSP1_SSP2_CLK,  4, 2),
 809         MUX(0, "ssp3_wclk_mux",  lsp1_wclk_ssp_p,    LSP1_SSP3_CLK,  4, 2),
 810         MUX(0, "ssp4_wclk_mux",  lsp1_wclk_ssp_p,    LSP1_SSP4_CLK,  4, 2),
 811         MUX(0, "usim1_wclk_mux", lsp1_wclk_common_p, LSP1_USIM1_CLK, 4, 1),
 812 };
 813
 814 static struct zx_clk_div lsp1_div_clk[] = {
 815         DIV_T(0, "pwm_div",  "pwm_wclk_mux",  LSP1_PWM_CLK,  12, 4, CLK_SET_RATE_PARENT, common_div_table),
 816         DIV_T(0, "ssp2_div", "ssp2_wclk_mux", LSP1_SSP2_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_table),
 817         DIV_T(0, "ssp3_div", "ssp3_wclk_mux", LSP1_SSP3_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_table),
 818         DIV_T(0, "ssp4_div", "ssp4_wclk_mux", LSP1_SSP4_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_table),
 819 };
 820
 821 static struct zx_clk_gate lsp1_gate_clk[] = {
 822         GATE(LSP1_UART4_WCLK, "lsp1_uart4_wclk", "uart4_wclk_mux", LSP1_UART4_CLK, 1, CLK_SET_RATE_PARENT, 0),
 823         GATE(LSP1_UART5_WCLK, "lsp1_uart5_wclk", "uart5_wclk_mux", LSP1_UART5_CLK, 1, CLK_SET_RATE_PARENT, 0),
 824         GATE(LSP1_PWM_WCLK,   "lsp1_pwm_wclk",   "pwm_div",        LSP1_PWM_CLK,   1, CLK_SET_RATE_PARENT, 0),
 825         GATE(LSP1_PWM_PCLK,   "lsp1_pwm_pclk",   "lsp1_pclk",      LSP1_PWM_CLK,   0, 0,                   0),
 826         GATE(LSP1_I2C2_WCLK,  "lsp1_i2c2_wclk",  "i2c2_wclk_mux",  LSP1_I2C2_CLK,  1, CLK_SET_RATE_PARENT, 0),
 827         GATE(LSP1_SSP2_WCLK,  "lsp1_ssp2_wclk",  "ssp2_div",       LSP1_SSP2_CLK,  1, CLK_SET_RATE_PARENT, 0),
 828         GATE(LSP1_SSP3_WCLK,  "lsp1_ssp3_wclk",  "ssp3_div",       LSP1_SSP3_CLK,  1, CLK_SET_RATE_PARENT, 0),
 829         GATE(LSP1_SSP4_WCLK,  "lsp1_ssp4_wclk",  "ssp4_div",       LSP1_SSP4_CLK,  1, CLK_SET_RATE_PARENT, 0),
 830         GATE(LSP1_USIM1_WCLK, "lsp1_usim1_wclk", "usim1_wclk_mux", LSP1_USIM1_CLK, 1, CLK_SET_RATE_PARENT, 0),
 831 };
 832
 833 static struct clk_hw_onecell_data lsp1_hw_onecell_data = {
 834         .num = LSP1_NR_CLKS,
 835         .hws = {
 836                 [LSP1_NR_CLKS - 1] = NULL,
 837         },
 838 };
 839
 840 static int __init lsp1_clocks_init(struct device_node *np)
 841 {
 842         void __iomem *reg_base;
 843         int i, ret;
 844
 845         reg_base = of_iomap(np, 0);
 846         if (!reg_base) {
 847                 pr_err("%s: Unable to map clk base\n", __func__);
 848                 return -ENXIO;
 849         }
 850
 851         for (i = 0; i < ARRAY_SIZE(lsp1_mux_clk); i++) {
 852                 if (lsp1_mux_clk[i].id)
 853                         lsp1_hw_onecell_data.hws[lsp1_mux_clk[i].id] =
 854                                         &lsp0_mux_clk[i].mux.hw;
 855
 856                 lsp1_mux_clk[i].mux.reg += (uintptr_t)reg_base;
 857                 ret = clk_hw_register(NULL, &lsp1_mux_clk[i].mux.hw);
 858                 if (ret) {
 859                         pr_warn("lsp1 clk %s init error!\n",
 860                                 lsp1_mux_clk[i].mux.hw.init->name);
 861                 }
 862         }
 863
 864         for (i = 0; i < ARRAY_SIZE(lsp1_gate_clk); i++) {
 865                 if (lsp1_gate_clk[i].id)
 866                         lsp1_hw_onecell_data.hws[lsp1_gate_clk[i].id] =
 867                                         &lsp1_gate_clk[i].gate.hw;
 868
 869                 lsp1_gate_clk[i].gate.reg += (uintptr_t)reg_base;
 870                 ret = clk_hw_register(NULL, &lsp1_gate_clk[i].gate.hw);
 871                 if (ret) {
 872                         pr_warn("lsp1 clk %s init error!\n",
 873                                 lsp1_gate_clk[i].gate.hw.init->name);
 874                 }
 875         }
 876
 877         for (i = 0; i < ARRAY_SIZE(lsp1_div_clk); i++) {
 878                 if (lsp1_div_clk[i].id)
 879                         lsp1_hw_onecell_data.hws[lsp1_div_clk[i].id] =
 880                                         &lsp1_div_clk[i].div.hw;
 881
 882                 lsp1_div_clk[i].div.reg += (uintptr_t)reg_base;
 883                 ret = clk_hw_register(NULL, &lsp1_div_clk[i].div.hw);
 884                 if (ret) {
 885                         pr_warn("lsp1 clk %s init error!\n",
 886                                 lsp1_div_clk[i].div.hw.init->name);
 887                 }
 888         }
 889
 890         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
 891                                      &lsp1_hw_onecell_data);
 892         if (ret) {
 893                 pr_err("failed to register lsp1 clk provider: %d\n", ret);
 894                 return ret;
 895         }
 896
 897         return 0;
 898 }
 899
 900 PNAME(audio_wclk_common_p) = {
 901         "audio_99m",
 902         "audio_24m",
 903 };
 904
 905 PNAME(audio_timer_p) = {
 906         "audio_24m",
 907         "audio_32k",
 908 };
 909
 910 static struct zx_clk_mux audio_mux_clk[] = {
 911         MUX(0, "i2s0_wclk_mux", audio_wclk_common_p, AUDIO_I2S0_CLK, 0, 1),
 912         MUX(0, "i2s1_wclk_mux", audio_wclk_common_p, AUDIO_I2S1_CLK, 0, 1),
 913         MUX(0, "i2s2_wclk_mux", audio_wclk_common_p, AUDIO_I2S2_CLK, 0, 1),
 914         MUX(0, "i2s3_wclk_mux", audio_wclk_common_p, AUDIO_I2S3_CLK, 0, 1),
 915         MUX(0, "i2c0_wclk_mux", audio_wclk_common_p, AUDIO_I2C0_CLK, 0, 1),
 916         MUX(0, "spdif0_wclk_mux", audio_wclk_common_p, AUDIO_SPDIF0_CLK, 0, 1),
 917         MUX(0, "spdif1_wclk_mux", audio_wclk_common_p, AUDIO_SPDIF1_CLK, 0, 1),
 918         MUX(0, "timer_wclk_mux", audio_timer_p, AUDIO_TIMER_CLK, 0, 1),
 919 };
 920
 921 static struct clk_zx_audio_divider audio_adiv_clk[] = {
 922         AUDIO_DIV(0, "i2s0_wclk_div", "i2s0_wclk_mux", AUDIO_I2S0_DIV_CFG1),
 923         AUDIO_DIV(0, "i2s1_wclk_div", "i2s1_wclk_mux", AUDIO_I2S1_DIV_CFG1),
 924         AUDIO_DIV(0, "i2s2_wclk_div", "i2s2_wclk_mux", AUDIO_I2S2_DIV_CFG1),
 925         AUDIO_DIV(0, "i2s3_wclk_div", "i2s3_wclk_mux", AUDIO_I2S3_DIV_CFG1),
 926         AUDIO_DIV(0, "spdif0_wclk_div", "spdif0_wclk_mux", AUDIO_SPDIF0_DIV_CFG1),
 927         AUDIO_DIV(0, "spdif1_wclk_div", "spdif1_wclk_mux", AUDIO_SPDIF1_DIV_CFG1),
 928 };
 929
 930 static struct zx_clk_div audio_div_clk[] = {
 931         DIV_T(0, "tdm_wclk_div", "audio_16m384", AUDIO_TDM_CLK, 8, 4, 0, common_div_table),
 932 };
 933
 934 static struct zx_clk_gate audio_gate_clk[] = {
 935         GATE(AUDIO_I2S0_WCLK, "i2s0_wclk", "i2s0_wclk_div", AUDIO_I2S0_CLK, 9, CLK_SET_RATE_PARENT, 0),
 936         GATE(AUDIO_I2S1_WCLK, "i2s1_wclk", "i2s1_wclk_div", AUDIO_I2S1_CLK, 9, CLK_SET_RATE_PARENT, 0),
 937         GATE(AUDIO_I2S2_WCLK, "i2s2_wclk", "i2s2_wclk_div", AUDIO_I2S2_CLK, 9, CLK_SET_RATE_PARENT, 0),
 938         GATE(AUDIO_I2S3_WCLK, "i2s3_wclk", "i2s3_wclk_div", AUDIO_I2S3_CLK, 9, CLK_SET_RATE_PARENT, 0),
 939         GATE(AUDIO_I2S0_PCLK, "i2s0_pclk", "clk49m5", AUDIO_I2S0_CLK, 8, 0, 0),
 940         GATE(AUDIO_I2S1_PCLK, "i2s1_pclk", "clk49m5", AUDIO_I2S1_CLK, 8, 0, 0),
 941         GATE(AUDIO_I2S2_PCLK, "i2s2_pclk", "clk49m5", AUDIO_I2S2_CLK, 8, 0, 0),
 942         GATE(AUDIO_I2S3_PCLK, "i2s3_pclk", "clk49m5", AUDIO_I2S3_CLK, 8, 0, 0),
 943         GATE(AUDIO_I2C0_WCLK, "i2c0_wclk", "i2c0_wclk_mux", AUDIO_I2C0_CLK, 9, CLK_SET_RATE_PARENT, 0),
 944         GATE(AUDIO_SPDIF0_WCLK, "spdif0_wclk", "spdif0_wclk_div", AUDIO_SPDIF0_CLK, 9, CLK_SET_RATE_PARENT, 0),
 945         GATE(AUDIO_SPDIF1_WCLK, "spdif1_wclk", "spdif1_wclk_div", AUDIO_SPDIF1_CLK, 9, CLK_SET_RATE_PARENT, 0),
 946         GATE(AUDIO_TDM_WCLK, "tdm_wclk", "tdm_wclk_div", AUDIO_TDM_CLK, 17, CLK_SET_RATE_PARENT, 0),
 947         GATE(AUDIO_TS_PCLK, "tempsensor_pclk", "clk49m5", AUDIO_TS_CLK, 1, 0, 0),
 948 };
 949
 950 static struct clk_hw_onecell_data audio_hw_onecell_data = {
 951         .num = AUDIO_NR_CLKS,
 952         .hws = {
 953                 [AUDIO_NR_CLKS - 1] = NULL,
 954         },
 955 };
 956
 957 static int __init audio_clocks_init(struct device_node *np)
 958 {
 959         void __iomem *reg_base;
 960         int i, ret;
 961
 962         reg_base = of_iomap(np, 0);
 963         if (!reg_base) {
 964                 pr_err("%s: Unable to map audio clk base\n", __func__);
 965                 return -ENXIO;
 966         }
 967
 968         for (i = 0; i < ARRAY_SIZE(audio_mux_clk); i++) {
 969                 if (audio_mux_clk[i].id)
 970                         audio_hw_onecell_data.hws[audio_mux_clk[i].id] =
 971                                         &audio_mux_clk[i].mux.hw;
 972
 973                 audio_mux_clk[i].mux.reg += (uintptr_t)reg_base;
 974                 ret = clk_hw_register(NULL, &audio_mux_clk[i].mux.hw);
 975                 if (ret) {
 976                         pr_warn("audio clk %s init error!\n",
 977                                 audio_mux_clk[i].mux.hw.init->name);
 978                 }
 979         }
 980
 981         for (i = 0; i < ARRAY_SIZE(audio_adiv_clk); i++) {
 982                 if (audio_adiv_clk[i].id)
 983                         audio_hw_onecell_data.hws[audio_adiv_clk[i].id] =
 984                                         &audio_adiv_clk[i].hw;
 985
 986                 audio_adiv_clk[i].reg_base += (uintptr_t)reg_base;
 987                 ret = clk_hw_register(NULL, &audio_adiv_clk[i].hw);
 988                 if (ret) {
 989                         pr_warn("audio clk %s init error!\n",
 990                                 audio_adiv_clk[i].hw.init->name);
 991                 }
 992         }
 993
 994         for (i = 0; i < ARRAY_SIZE(audio_div_clk); i++) {
 995                 if (audio_div_clk[i].id)
 996                         audio_hw_onecell_data.hws[audio_div_clk[i].id] =
 997                                         &audio_div_clk[i].div.hw;
 998
 999                 audio_div_clk[i].div.reg += (uintptr_t)reg_base;
1000                 ret = clk_hw_register(NULL, &audio_div_clk[i].div.hw);
1001                 if (ret) {
1002                         pr_warn("audio clk %s init error!\n",
1003                                 audio_div_clk[i].div.hw.init->name);
1004                 }
1005         }
1006
1007         for (i = 0; i < ARRAY_SIZE(audio_gate_clk); i++) {
1008                 if (audio_gate_clk[i].id)
1009                         audio_hw_onecell_data.hws[audio_gate_clk[i].id] =
1010                                         &audio_gate_clk[i].gate.hw;
1011
1012                 audio_gate_clk[i].gate.reg += (uintptr_t)reg_base;
1013                 ret = clk_hw_register(NULL, &audio_gate_clk[i].gate.hw);
1014                 if (ret) {
1015                         pr_warn("audio clk %s init error!\n",
1016                                 audio_gate_clk[i].gate.hw.init->name);
1017                 }
1018         }
1019
1020         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
1021                                      &audio_hw_onecell_data);
1022         if (ret) {
1023                 pr_err("failed to register audio clk provider: %d\n", ret);
1024                 return ret;
1025         }
1026
1027         return 0;
1028 }
1029
1030 static const struct of_device_id zx_clkc_match_table[] = {
1031         { .compatible = "zte,zx296718-topcrm", .data = &top_clocks_init },
1032         { .compatible = "zte,zx296718-lsp0crm", .data = &lsp0_clocks_init },
1033         { .compatible = "zte,zx296718-lsp1crm", .data = &lsp1_clocks_init },
1034         { .compatible = "zte,zx296718-audiocrm", .data = &audio_clocks_init },
1035         { }
1036 };
1037
1038 static int zx_clkc_probe(struct platform_device *pdev)
1039 {
1040         int (*init_fn)(struct device_node *np);
1041         struct device_node *np = pdev->dev.of_node;
1042
1043         init_fn = of_device_get_match_data(&pdev->dev);
1044         if (!init_fn) {
1045                 dev_err(&pdev->dev, "Error: No device match found\n");
1046                 return -ENODEV;
1047         }
1048
1049         return init_fn(np);
1050 }
1051
1052 static struct platform_driver zx_clk_driver = {
1053         .probe          = zx_clkc_probe,
1054         .driver         = {
1055                 .name   = "zx296718-clkc",
1056                 .of_match_table = zx_clkc_match_table,
1057         },
1058 };
1059
1060 static int __init zx_clk_init(void)
1061 {
1062         return platform_driver_register(&zx_clk_driver);
1063 }
1064 core_initcall(zx_clk_init);