drivers/clk/zynq/clkc.c

   1 /*
   2  * Zynq clock controller
   3  *
   4  *  Copyright (C) 2012 - 2013 Xilinx
   5  *
   6  *  Sören Brinkmann <soren.brinkmann@xilinx.com>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License v2 as published by
  10  * the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <linux/clk/zynq.h>
  22 #include <linux/clk-provider.h>
  23 #include <linux/of.h>
  24 #include <linux/slab.h>
  25 #include <linux/string.h>
  26 #include <linux/io.h>
  27
  28 static void __iomem *zynq_slcr_base_priv;
  29
  30 #define SLCR_ARMPLL_CTRL                (zynq_slcr_base_priv + 0x100)
  31 #define SLCR_DDRPLL_CTRL                (zynq_slcr_base_priv + 0x104)
  32 #define SLCR_IOPLL_CTRL                 (zynq_slcr_base_priv + 0x108)
  33 #define SLCR_PLL_STATUS                 (zynq_slcr_base_priv + 0x10c)
  34 #define SLCR_ARM_CLK_CTRL               (zynq_slcr_base_priv + 0x120)
  35 #define SLCR_DDR_CLK_CTRL               (zynq_slcr_base_priv + 0x124)
  36 #define SLCR_DCI_CLK_CTRL               (zynq_slcr_base_priv + 0x128)
  37 #define SLCR_APER_CLK_CTRL              (zynq_slcr_base_priv + 0x12c)
  38 #define SLCR_GEM0_CLK_CTRL              (zynq_slcr_base_priv + 0x140)
  39 #define SLCR_GEM1_CLK_CTRL              (zynq_slcr_base_priv + 0x144)
  40 #define SLCR_SMC_CLK_CTRL               (zynq_slcr_base_priv + 0x148)
  41 #define SLCR_LQSPI_CLK_CTRL             (zynq_slcr_base_priv + 0x14c)
  42 #define SLCR_SDIO_CLK_CTRL              (zynq_slcr_base_priv + 0x150)
  43 #define SLCR_UART_CLK_CTRL              (zynq_slcr_base_priv + 0x154)
  44 #define SLCR_SPI_CLK_CTRL               (zynq_slcr_base_priv + 0x158)
  45 #define SLCR_CAN_CLK_CTRL               (zynq_slcr_base_priv + 0x15c)
  46 #define SLCR_CAN_MIOCLK_CTRL            (zynq_slcr_base_priv + 0x160)
  47 #define SLCR_DBG_CLK_CTRL               (zynq_slcr_base_priv + 0x164)
  48 #define SLCR_PCAP_CLK_CTRL              (zynq_slcr_base_priv + 0x168)
  49 #define SLCR_FPGA0_CLK_CTRL             (zynq_slcr_base_priv + 0x170)
  50 #define SLCR_621_TRUE                   (zynq_slcr_base_priv + 0x1c4)
  51 #define SLCR_SWDT_CLK_SEL               (zynq_slcr_base_priv + 0x304)
  52
  53 #define NUM_MIO_PINS    54
  54
  55 enum zynq_clk {
  56         armpll, ddrpll, iopll,
  57         cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
  58         ddr2x, ddr3x, dci,
  59         lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,
  60         sdio0, sdio1, uart0, uart1, spi0, spi1, dma,
  61         usb0_aper, usb1_aper, gem0_aper, gem1_aper,
  62         sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper,
  63         i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper,
  64         smc_aper, swdt, dbg_trc, dbg_apb, clk_max};
  65
  66 static struct clk *ps_clk;
  67 static struct clk *clks[clk_max];
  68 static struct clk_onecell_data clk_data;
  69
  70 static DEFINE_SPINLOCK(armpll_lock);
  71 static DEFINE_SPINLOCK(ddrpll_lock);
  72 static DEFINE_SPINLOCK(iopll_lock);
  73 static DEFINE_SPINLOCK(armclk_lock);
  74 static DEFINE_SPINLOCK(swdtclk_lock);
  75 static DEFINE_SPINLOCK(ddrclk_lock);
  76 static DEFINE_SPINLOCK(dciclk_lock);
  77 static DEFINE_SPINLOCK(gem0clk_lock);
  78 static DEFINE_SPINLOCK(gem1clk_lock);
  79 static DEFINE_SPINLOCK(canclk_lock);
  80 static DEFINE_SPINLOCK(canmioclk_lock);
  81 static DEFINE_SPINLOCK(dbgclk_lock);
  82 static DEFINE_SPINLOCK(aperclk_lock);
  83
  84 static const char dummy_nm[] __initconst = "dummy_name";
  85
  86 static const char *armpll_parents[] __initdata = {"armpll_int", "ps_clk"};
  87 static const char *ddrpll_parents[] __initdata = {"ddrpll_int", "ps_clk"};
  88 static const char *iopll_parents[] __initdata = {"iopll_int", "ps_clk"};
  89 static const char *gem0_mux_parents[] __initdata = {"gem0_div1", dummy_nm};
  90 static const char *gem1_mux_parents[] __initdata = {"gem1_div1", dummy_nm};
  91 static const char *can0_mio_mux2_parents[] __initdata = {"can0_gate",
  92         "can0_mio_mux"};
  93 static const char *can1_mio_mux2_parents[] __initdata = {"can1_gate",
  94         "can1_mio_mux"};
  95 static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div",
  96         dummy_nm};
  97
  98 static const char *dbgtrc_emio_input_names[] __initdata = {"trace_emio_clk"};
  99 static const char *gem0_emio_input_names[] __initdata = {"gem0_emio_clk"};
 100 static const char *gem1_emio_input_names[] __initdata = {"gem1_emio_clk"};
 101 static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"};
 102
 103 static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
 104                 const char *clk_name, void __iomem *fclk_ctrl_reg,
 105                 const char **parents, int enable)
 106 {
 107         struct clk *clk;
 108         u32 enable_reg;
 109         char *mux_name;
 110         char *div0_name;
 111         char *div1_name;
 112         spinlock_t *fclk_lock;
 113         spinlock_t *fclk_gate_lock;
 114         void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8;
 115
 116         fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL);
 117         if (!fclk_lock)
 118                 goto err;
 119         fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL);
 120         if (!fclk_gate_lock)
 121                 goto err_fclk_gate_lock;
 122         spin_lock_init(fclk_lock);
 123         spin_lock_init(fclk_gate_lock);
 124
 125         mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name);
 126         if (!mux_name)
 127                 goto err_mux_name;
 128         div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
 129         if (!div0_name)
 130                 goto err_div0_name;
 131         div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
 132         if (!div1_name)
 133                 goto err_div1_name;
 134
 135         clk = clk_register_mux(NULL, mux_name, parents, 4,
 136                         CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
 137                         fclk_lock);
 138
 139         clk = clk_register_divider(NULL, div0_name, mux_name,
 140                         0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
 141                         CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
 142
 143         clk = clk_register_divider(NULL, div1_name, div0_name,
 144                         CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
 145                         CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
 146                         fclk_lock);
 147
 148         clks[fclk] = clk_register_gate(NULL, clk_name,
 149                         div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
 150                         0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
 151         enable_reg = readl(fclk_gate_reg) & 1;
 152         if (enable && !enable_reg) {
 153                 if (clk_prepare_enable(clks[fclk]))
 154                         pr_warn("%s: FCLK%u enable failed\n", __func__,
 155                                         fclk - fclk0);
 156         }
 157         kfree(mux_name);
 158         kfree(div0_name);
 159         kfree(div1_name);
 160
 161         return;
 162
 163 err_div1_name:
 164         kfree(div0_name);
 165 err_div0_name:
 166         kfree(mux_name);
 167 err_mux_name:
 168         kfree(fclk_gate_lock);
 169 err_fclk_gate_lock:
 170         kfree(fclk_lock);
 171 err:
 172         clks[fclk] = ERR_PTR(-ENOMEM);
 173 }
 174
 175 static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
 176                 enum zynq_clk clk1, const char *clk_name0,
 177                 const char *clk_name1, void __iomem *clk_ctrl,
 178                 const char **parents, unsigned int two_gates)
 179 {
 180         struct clk *clk;
 181         char *mux_name;
 182         char *div_name;
 183         spinlock_t *lock;
 184
 185         lock = kmalloc(sizeof(*lock), GFP_KERNEL);
 186         if (!lock)
 187                 goto err;
 188         spin_lock_init(lock);
 189
 190         mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
 191         div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
 192
 193         clk = clk_register_mux(NULL, mux_name, parents, 4,
 194                         CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
 195
 196         clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
 197                         CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
 198
 199         clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
 200                         CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);
 201         if (two_gates)
 202                 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,
 203                                 CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);
 204
 205         kfree(mux_name);
 206         kfree(div_name);
 207
 208         return;
 209
 210 err:
 211         clks[clk0] = ERR_PTR(-ENOMEM);
 212         if (two_gates)
 213                 clks[clk1] = ERR_PTR(-ENOMEM);
 214 }
 215
 216 static void __init zynq_clk_setup(struct device_node *np)
 217 {
 218         int i;
 219         u32 tmp;
 220         int ret;
 221         struct clk *clk;
 222         char *clk_name;
 223         unsigned int fclk_enable = 0;
 224         const char *clk_output_name[clk_max];
 225         const char *cpu_parents[4];
 226         const char *periph_parents[4];
 227         const char *swdt_ext_clk_mux_parents[2];
 228         const char *can_mio_mux_parents[NUM_MIO_PINS];
 229
 230         pr_info("Zynq clock init\n");
 231
 232         /* get clock output names from DT */
 233         for (i = 0; i < clk_max; i++) {
 234                 if (of_property_read_string_index(np, "clock-output-names",
 235                                   i, &clk_output_name[i])) {
 236                         pr_err("%s: clock output name not in DT\n", __func__);
 237                         BUG();
 238                 }
 239         }
 240         cpu_parents[0] = clk_output_name[armpll];
 241         cpu_parents[1] = clk_output_name[armpll];
 242         cpu_parents[2] = clk_output_name[ddrpll];
 243         cpu_parents[3] = clk_output_name[iopll];
 244         periph_parents[0] = clk_output_name[iopll];
 245         periph_parents[1] = clk_output_name[iopll];
 246         periph_parents[2] = clk_output_name[armpll];
 247         periph_parents[3] = clk_output_name[ddrpll];
 248
 249         of_property_read_u32(np, "fclk-enable", &fclk_enable);
 250
 251         /* ps_clk */
 252         ret = of_property_read_u32(np, "ps-clk-frequency", &tmp);
 253         if (ret) {
 254                 pr_warn("ps_clk frequency not specified, using 33 MHz.\n");
 255                 tmp = 33333333;
 256         }
 257         ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT,
 258                         tmp);
 259
 260         /* PLLs */
 261         clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
 262                         SLCR_PLL_STATUS, 0, &armpll_lock);
 263         clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
 264                         armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
 265                         SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
 266
 267         clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
 268                         SLCR_PLL_STATUS, 1, &ddrpll_lock);
 269         clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
 270                         ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
 271                         SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
 272
 273         clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
 274                         SLCR_PLL_STATUS, 2, &iopll_lock);
 275         clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
 276                         iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
 277                         SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
 278
 279         /* CPU clocks */
 280         tmp = readl(SLCR_621_TRUE) & 1;
 281         clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
 282                         CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
 283                         &armclk_lock);
 284         clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
 285                         SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
 286                         CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
 287
 288         clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],
 289                         "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
 290                         SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
 291
 292         clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
 293                         1, 2);
 294         clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
 295                         "cpu_3or2x_div", CLK_IGNORE_UNUSED,
 296                         SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
 297
 298         clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
 299                         2 + tmp);
 300         clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
 301                         "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
 302                         26, 0, &armclk_lock);
 303
 304         clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
 305                         4 + 2 * tmp);
 306         clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
 307                         "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
 308                         0, &armclk_lock);
 309
 310         /* Timers */
 311         swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x];
 312         for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) {
 313                 int idx = of_property_match_string(np, "clock-names",
 314                                 swdt_ext_clk_input_names[i]);
 315                 if (idx >= 0)
 316                         swdt_ext_clk_mux_parents[i + 1] =
 317                                 of_clk_get_parent_name(np, idx);
 318                 else
 319                         swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
 320         }
 321         clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
 322                         swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |
 323                         CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0,
 324                         &swdtclk_lock);
 325
 326         /* DDR clocks */
 327         clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
 328                         SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
 329                         CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
 330         clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
 331                         "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
 332         clk_prepare_enable(clks[ddr2x]);
 333         clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
 334                         SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
 335                         CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
 336         clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
 337                         "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
 338         clk_prepare_enable(clks[ddr3x]);
 339
 340         clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
 341                         SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
 342                         CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
 343         clk = clk_register_divider(NULL, "dci_div1", "dci_div0",
 344                         CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
 345                         CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
 346                         &dciclk_lock);
 347         clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1",
 348                         CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0,
 349                         &dciclk_lock);
 350         clk_prepare_enable(clks[dci]);
 351
 352         /* Peripheral clocks */
 353         for (i = fclk0; i <= fclk3; i++) {
 354                 int enable = !!(fclk_enable & BIT(i - fclk0));
 355                 zynq_clk_register_fclk(i, clk_output_name[i],
 356                                 SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
 357                                 periph_parents, enable);
 358         }
 359
 360         zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
 361                         SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
 362
 363         zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,
 364                         SLCR_SMC_CLK_CTRL, periph_parents, 0);
 365
 366         zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,
 367                         SLCR_PCAP_CLK_CTRL, periph_parents, 0);
 368
 369         zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
 370                         clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,
 371                         periph_parents, 1);
 372
 373         zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0],
 374                         clk_output_name[uart1], SLCR_UART_CLK_CTRL,
 375                         periph_parents, 1);
 376
 377         zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0],
 378                         clk_output_name[spi1], SLCR_SPI_CLK_CTRL,
 379                         periph_parents, 1);
 380
 381         for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) {
 382                 int idx = of_property_match_string(np, "clock-names",
 383                                 gem0_emio_input_names[i]);
 384                 if (idx >= 0)
 385                         gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
 386                                         idx);
 387         }
 388         clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
 389                         CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
 390                         &gem0clk_lock);
 391         clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
 392                         SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
 393                         CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
 394         clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",
 395                         CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
 396                         CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
 397                         &gem0clk_lock);
 398         clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
 399                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 400                         SLCR_GEM0_CLK_CTRL, 6, 1, 0,
 401                         &gem0clk_lock);
 402         clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
 403                         "gem0_emio_mux", CLK_SET_RATE_PARENT,
 404                         SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
 405
 406         for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) {
 407                 int idx = of_property_match_string(np, "clock-names",
 408                                 gem1_emio_input_names[i]);
 409                 if (idx >= 0)
 410                         gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
 411                                         idx);
 412         }
 413         clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
 414                         CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
 415                         &gem1clk_lock);
 416         clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
 417                         SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
 418                         CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
 419         clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",
 420                         CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
 421                         CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
 422                         &gem1clk_lock);
 423         clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
 424                         CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 425                         SLCR_GEM1_CLK_CTRL, 6, 1, 0,
 426                         &gem1clk_lock);
 427         clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
 428                         "gem1_emio_mux", CLK_SET_RATE_PARENT,
 429                         SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);
 430
 431         tmp = strlen("mio_clk_00x");
 432         clk_name = kmalloc(tmp, GFP_KERNEL);
 433         for (i = 0; i < NUM_MIO_PINS; i++) {
 434                 int idx;
 435
 436                 snprintf(clk_name, tmp, "mio_clk_%2.2d", i);
 437                 idx = of_property_match_string(np, "clock-names", clk_name);
 438                 if (idx >= 0)
 439                         can_mio_mux_parents[i] = of_clk_get_parent_name(np,
 440                                                 idx);
 441                 else
 442                         can_mio_mux_parents[i] = dummy_nm;
 443         }
 444         kfree(clk_name);
 445         clk = clk_register_mux(NULL, "can_mux", periph_parents, 4,
 446                         CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
 447                         &canclk_lock);
 448         clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
 449                         SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
 450                         CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
 451         clk = clk_register_divider(NULL, "can_div1", "can_div0",
 452                         CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
 453                         CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
 454                         &canclk_lock);
 455         clk = clk_register_gate(NULL, "can0_gate", "can_div1",
 456                         CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
 457                         &canclk_lock);
 458         clk = clk_register_gate(NULL, "can1_gate", "can_div1",
 459                         CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
 460                         &canclk_lock);
 461         clk = clk_register_mux(NULL, "can0_mio_mux",
 462                         can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
 463                         CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
 464                         &canmioclk_lock);
 465         clk = clk_register_mux(NULL, "can1_mio_mux",
 466                         can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
 467                         CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
 468                         0, &canmioclk_lock);
 469         clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
 470                         can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
 471                         CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0,
 472                         &canmioclk_lock);
 473         clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
 474                         can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
 475                         CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1,
 476                         0, &canmioclk_lock);
 477
 478         for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
 479                 int idx = of_property_match_string(np, "clock-names",
 480                                 dbgtrc_emio_input_names[i]);
 481                 if (idx >= 0)
 482                         dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
 483                                         idx);
 484         }
 485         clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
 486                         CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
 487                         &dbgclk_lock);
 488         clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
 489                         SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
 490                         CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
 491         clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
 492                         CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
 493                         &dbgclk_lock);
 494         clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
 495                         "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
 496                         0, 0, &dbgclk_lock);
 497         clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb],
 498                         clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0,
 499                         &dbgclk_lock);
 500
 501         /* One gated clock for all APER clocks. */
 502         clks[dma] = clk_register_gate(NULL, clk_output_name[dma],
 503                         clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0,
 504                         &aperclk_lock);
 505         clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper],
 506                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0,
 507                         &aperclk_lock);
 508         clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper],
 509                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0,
 510                         &aperclk_lock);
 511         clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper],
 512                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0,
 513                         &aperclk_lock);
 514         clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper],
 515                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0,
 516                         &aperclk_lock);
 517         clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper],
 518                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0,
 519                         &aperclk_lock);
 520         clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper],
 521                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0,
 522                         &aperclk_lock);
 523         clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper],
 524                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0,
 525                         &aperclk_lock);
 526         clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper],
 527                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0,
 528                         &aperclk_lock);
 529         clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper],
 530                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0,
 531                         &aperclk_lock);
 532         clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper],
 533                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0,
 534                         &aperclk_lock);
 535         clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper],
 536                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0,
 537                         &aperclk_lock);
 538         clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper],
 539                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0,
 540                         &aperclk_lock);
 541         clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper],
 542                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0,
 543                         &aperclk_lock);
 544         clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper],
 545                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0,
 546                         &aperclk_lock);
 547         clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper],
 548                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0,
 549                         &aperclk_lock);
 550         clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper],
 551                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0,
 552                         &aperclk_lock);
 553         clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper],
 554                         clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0,
 555                         &aperclk_lock);
 556
 557         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 558                 if (IS_ERR(clks[i])) {
 559                         pr_err("Zynq clk %d: register failed with %ld\n",
 560                                i, PTR_ERR(clks[i]));
 561                         BUG();
 562                 }
 563         }
 564
 565         clk_data.clks = clks;
 566         clk_data.clk_num = ARRAY_SIZE(clks);
 567         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 568 }
 569
 570 CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
 571
 572 void __init zynq_clock_init(void __iomem *slcr_base)
 573 {
 574         zynq_slcr_base_priv = slcr_base;
 575         of_clk_init(NULL);
 576 }