drivers/clocksource/h8300_timer8.c

   1 /*
   2  *  linux/arch/h8300/kernel/cpu/timer/timer8.c
   3  *
   4  *  Yoshinori Sato <ysato@users.sourcefoge.jp>
   5  *
   6  *  8bit Timer driver
   7  *
   8  */
   9
  10 #include <linux/errno.h>
  11 #include <linux/kernel.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/init.h>
  14 #include <linux/clockchips.h>
  15 #include <linux/clk.h>
  16 #include <linux/io.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20
  21 #define _8TCR   0
  22 #define _8TCSR  2
  23 #define TCORA   4
  24 #define TCORB   6
  25 #define _8TCNT  8
  26
  27 #define FLAG_STARTED (1 << 3)
  28
  29 #define SCALE 64
  30
  31 struct timer8_priv {
  32         struct clock_event_device ced;
  33         void __iomem *mapbase;
  34         unsigned long flags;
  35         unsigned int rate;
  36 };
  37
  38 static irqreturn_t timer8_interrupt(int irq, void *dev_id)
  39 {
  40         struct timer8_priv *p = dev_id;
  41
  42         if (clockevent_state_oneshot(&p->ced))
  43                 writew(0x0000, p->mapbase + _8TCR);
  44
  45         p->ced.event_handler(&p->ced);
  46
  47         writeb(readb(p->mapbase + _8TCSR) & ~0x40,
  48                   p->mapbase + _8TCSR);
  49
  50         return IRQ_HANDLED;
  51 }
  52
  53 static void timer8_set_next(struct timer8_priv *p, unsigned long delta)
  54 {
  55         if (delta >= 0x10000)
  56                 pr_warn("delta out of range\n");
  57         writeb(readb(p->mapbase + _8TCR) & ~0x40, p->mapbase + _8TCR);
  58         writew(0, p->mapbase + _8TCNT);
  59         writew(delta, p->mapbase + TCORA);
  60         writeb(readb(p->mapbase + _8TCR) | 0x40, p->mapbase + _8TCR);
  61 }
  62
  63 static int timer8_enable(struct timer8_priv *p)
  64 {
  65         writew(0xffff, p->mapbase + TCORA);
  66         writew(0x0000, p->mapbase + _8TCNT);
  67         writew(0x0c02, p->mapbase + _8TCR);
  68
  69         return 0;
  70 }
  71
  72 static int timer8_start(struct timer8_priv *p)
  73 {
  74         int ret;
  75
  76         if ((p->flags & FLAG_STARTED))
  77                 return 0;
  78
  79         ret = timer8_enable(p);
  80         if (!ret)
  81                 p->flags |= FLAG_STARTED;
  82
  83         return ret;
  84 }
  85
  86 static void timer8_stop(struct timer8_priv *p)
  87 {
  88         writew(0x0000, p->mapbase + _8TCR);
  89 }
  90
  91 static inline struct timer8_priv *ced_to_priv(struct clock_event_device *ced)
  92 {
  93         return container_of(ced, struct timer8_priv, ced);
  94 }
  95
  96 static void timer8_clock_event_start(struct timer8_priv *p, unsigned long delta)
  97 {
  98         struct clock_event_device *ced = &p->ced;
  99
 100         timer8_start(p);
 101
 102         ced->shift = 32;
 103         ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
 104         ced->max_delta_ns = clockevent_delta2ns(0xffff, ced);
 105         ced->min_delta_ns = clockevent_delta2ns(0x0001, ced);
 106
 107         timer8_set_next(p, delta);
 108 }
 109
 110 static int timer8_clock_event_shutdown(struct clock_event_device *ced)
 111 {
 112         timer8_stop(ced_to_priv(ced));
 113         return 0;
 114 }
 115
 116 static int timer8_clock_event_periodic(struct clock_event_device *ced)
 117 {
 118         struct timer8_priv *p = ced_to_priv(ced);
 119
 120         pr_info("%s: used for periodic clock events\n", ced->name);
 121         timer8_stop(p);
 122         timer8_clock_event_start(p, (p->rate + HZ/2) / HZ);
 123
 124         return 0;
 125 }
 126
 127 static int timer8_clock_event_oneshot(struct clock_event_device *ced)
 128 {
 129         struct timer8_priv *p = ced_to_priv(ced);
 130
 131         pr_info("%s: used for oneshot clock events\n", ced->name);
 132         timer8_stop(p);
 133         timer8_clock_event_start(p, 0x10000);
 134
 135         return 0;
 136 }
 137
 138 static int timer8_clock_event_next(unsigned long delta,
 139                                    struct clock_event_device *ced)
 140 {
 141         struct timer8_priv *p = ced_to_priv(ced);
 142
 143         BUG_ON(!clockevent_state_oneshot(ced));
 144         timer8_set_next(p, delta - 1);
 145
 146         return 0;
 147 }
 148
 149 static struct timer8_priv timer8_priv = {
 150         .ced = {
 151                 .name = "h8300_8timer",
 152                 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 153                 .rating = 200,
 154                 .set_next_event = timer8_clock_event_next,
 155                 .set_state_shutdown = timer8_clock_event_shutdown,
 156                 .set_state_periodic = timer8_clock_event_periodic,
 157                 .set_state_oneshot = timer8_clock_event_oneshot,
 158         },
 159 };
 160
 161 static void __init h8300_8timer_init(struct device_node *node)
 162 {
 163         void __iomem *base;
 164         int irq;
 165         struct clk *clk;
 166
 167         clk = of_clk_get(node, 0);
 168         if (IS_ERR(clk)) {
 169                 pr_err("failed to get clock for clockevent\n");
 170                 return;
 171         }
 172
 173         base = of_iomap(node, 0);
 174         if (!base) {
 175                 pr_err("failed to map registers for clockevent\n");
 176                 goto free_clk;
 177         }
 178
 179         irq = irq_of_parse_and_map(node, 0);
 180         if (!irq) {
 181                 pr_err("failed to get irq for clockevent\n");
 182                 goto unmap_reg;
 183         }
 184
 185         timer8_priv.mapbase = base;
 186
 187         timer8_priv.rate = clk_get_rate(clk) / SCALE;
 188         if (!timer8_priv.rate) {
 189                 pr_err("Failed to get rate for the clocksource\n");
 190                 goto unmap_reg;
 191         }
 192
 193         if (request_irq(irq, timer8_interrupt, IRQF_TIMER,
 194                         timer8_priv.ced.name, &timer8_priv) < 0) {
 195                 pr_err("failed to request irq %d for clockevent\n", irq);
 196                 goto unmap_reg;
 197         }
 198
 199         clockevents_config_and_register(&timer8_priv.ced,
 200                                         timer8_priv.rate, 1, 0x0000ffff);
 201
 202         return;
 203 unmap_reg:
 204         iounmap(base);
 205 free_clk:
 206         clk_put(clk);
 207 }
 208
 209 CLOCKSOURCE_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);