2 * SuperH Timer Support - CMT
4 * Copyright (C) 2008 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
26 #include <linux/clk.h>
27 #include <linux/irq.h>
28 #include <linux/err.h>
29 #include <linux/delay.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/sh_timer.h>
33 #include <linux/slab.h>
36 void __iomem *mapbase;
38 unsigned long width; /* 16 or 32 bit version of hardware block */
39 unsigned long overflow_bit;
40 unsigned long clear_bits;
41 struct irqaction irqaction;
42 struct platform_device *pdev;
45 unsigned long match_value;
46 unsigned long next_match_value;
47 unsigned long max_match_value;
50 struct clock_event_device ced;
51 struct clocksource cs;
52 unsigned long total_cycles;
55 static DEFINE_SPINLOCK(sh_cmt_lock);
57 #define CMSTR -1 /* shared register */
58 #define CMCSR 0 /* channel register */
59 #define CMCNT 1 /* channel register */
60 #define CMCOR 2 /* channel register */
62 static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
64 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
65 void __iomem *base = p->mapbase;
68 if (reg_nr == CMSTR) {
70 base -= cfg->channel_offset;
78 if ((reg_nr == CMCNT) || (reg_nr == CMCOR))
79 return ioread32(base + offs);
82 return ioread16(base + offs);
85 static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
88 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
89 void __iomem *base = p->mapbase;
92 if (reg_nr == CMSTR) {
94 base -= cfg->channel_offset;
102 if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) {
103 iowrite32(value, base + offs);
108 iowrite16(value, base + offs);
111 static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
114 unsigned long v1, v2, v3;
117 o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
119 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
122 v1 = sh_cmt_read(p, CMCNT);
123 v2 = sh_cmt_read(p, CMCNT);
124 v3 = sh_cmt_read(p, CMCNT);
125 o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
126 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
127 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
134 static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
136 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
137 unsigned long flags, value;
139 /* start stop register shared by multiple timer channels */
140 spin_lock_irqsave(&sh_cmt_lock, flags);
141 value = sh_cmt_read(p, CMSTR);
144 value |= 1 << cfg->timer_bit;
146 value &= ~(1 << cfg->timer_bit);
148 sh_cmt_write(p, CMSTR, value);
149 spin_unlock_irqrestore(&sh_cmt_lock, flags);
152 static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
157 ret = clk_enable(p->clk);
159 dev_err(&p->pdev->dev, "cannot enable clock\n");
163 /* make sure channel is disabled */
164 sh_cmt_start_stop_ch(p, 0);
166 /* configure channel, periodic mode and maximum timeout */
167 if (p->width == 16) {
168 *rate = clk_get_rate(p->clk) / 512;
169 sh_cmt_write(p, CMCSR, 0x43);
171 *rate = clk_get_rate(p->clk) / 8;
172 sh_cmt_write(p, CMCSR, 0x01a4);
175 sh_cmt_write(p, CMCOR, 0xffffffff);
176 sh_cmt_write(p, CMCNT, 0);
179 * According to the sh73a0 user's manual, as CMCNT can be operated
180 * only by the RCLK (Pseudo 32 KHz), there's one restriction on
181 * modifying CMCNT register; two RCLK cycles are necessary before
182 * this register is either read or any modification of the value
183 * it holds is reflected in the LSI's actual operation.
185 * While at it, we're supposed to clear out the CMCNT as of this
186 * moment, so make sure it's processed properly here. This will
187 * take RCLKx2 at maximum.
189 for (k = 0; k < 100; k++) {
190 if (!sh_cmt_read(p, CMCNT))
195 if (sh_cmt_read(p, CMCNT)) {
196 dev_err(&p->pdev->dev, "cannot clear CMCNT\n");
202 sh_cmt_start_stop_ch(p, 1);
212 static void sh_cmt_disable(struct sh_cmt_priv *p)
214 /* disable channel */
215 sh_cmt_start_stop_ch(p, 0);
217 /* disable interrupts in CMT block */
218 sh_cmt_write(p, CMCSR, 0);
225 #define FLAG_CLOCKEVENT (1 << 0)
226 #define FLAG_CLOCKSOURCE (1 << 1)
227 #define FLAG_REPROGRAM (1 << 2)
228 #define FLAG_SKIPEVENT (1 << 3)
229 #define FLAG_IRQCONTEXT (1 << 4)
231 static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
234 unsigned long new_match;
235 unsigned long value = p->next_match_value;
236 unsigned long delay = 0;
237 unsigned long now = 0;
240 now = sh_cmt_get_counter(p, &has_wrapped);
241 p->flags |= FLAG_REPROGRAM; /* force reprogram */
244 /* we're competing with the interrupt handler.
245 * -> let the interrupt handler reprogram the timer.
246 * -> interrupt number two handles the event.
248 p->flags |= FLAG_SKIPEVENT;
256 /* reprogram the timer hardware,
257 * but don't save the new match value yet.
259 new_match = now + value + delay;
260 if (new_match > p->max_match_value)
261 new_match = p->max_match_value;
263 sh_cmt_write(p, CMCOR, new_match);
265 now = sh_cmt_get_counter(p, &has_wrapped);
266 if (has_wrapped && (new_match > p->match_value)) {
267 /* we are changing to a greater match value,
268 * so this wrap must be caused by the counter
269 * matching the old value.
270 * -> first interrupt reprograms the timer.
271 * -> interrupt number two handles the event.
273 p->flags |= FLAG_SKIPEVENT;
278 /* we are changing to a smaller match value,
279 * so the wrap must be caused by the counter
280 * matching the new value.
281 * -> save programmed match value.
282 * -> let isr handle the event.
284 p->match_value = new_match;
288 /* be safe: verify hardware settings */
289 if (now < new_match) {
290 /* timer value is below match value, all good.
291 * this makes sure we won't miss any match events.
292 * -> save programmed match value.
293 * -> let isr handle the event.
295 p->match_value = new_match;
299 /* the counter has reached a value greater
300 * than our new match value. and since the
301 * has_wrapped flag isn't set we must have
302 * programmed a too close event.
303 * -> increase delay and retry.
311 dev_warn(&p->pdev->dev, "too long delay\n");
316 static void __sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
318 if (delta > p->max_match_value)
319 dev_warn(&p->pdev->dev, "delta out of range\n");
321 p->next_match_value = delta;
322 sh_cmt_clock_event_program_verify(p, 0);
325 static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
329 spin_lock_irqsave(&p->lock, flags);
330 __sh_cmt_set_next(p, delta);
331 spin_unlock_irqrestore(&p->lock, flags);
334 static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
336 struct sh_cmt_priv *p = dev_id;
339 sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits);
341 /* update clock source counter to begin with if enabled
342 * the wrap flag should be cleared by the timer specific
343 * isr before we end up here.
345 if (p->flags & FLAG_CLOCKSOURCE)
346 p->total_cycles += p->match_value + 1;
348 if (!(p->flags & FLAG_REPROGRAM))
349 p->next_match_value = p->max_match_value;
351 p->flags |= FLAG_IRQCONTEXT;
353 if (p->flags & FLAG_CLOCKEVENT) {
354 if (!(p->flags & FLAG_SKIPEVENT)) {
355 if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
356 p->next_match_value = p->max_match_value;
357 p->flags |= FLAG_REPROGRAM;
360 p->ced.event_handler(&p->ced);
364 p->flags &= ~FLAG_SKIPEVENT;
366 if (p->flags & FLAG_REPROGRAM) {
367 p->flags &= ~FLAG_REPROGRAM;
368 sh_cmt_clock_event_program_verify(p, 1);
370 if (p->flags & FLAG_CLOCKEVENT)
371 if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
372 || (p->match_value == p->next_match_value))
373 p->flags &= ~FLAG_REPROGRAM;
376 p->flags &= ~FLAG_IRQCONTEXT;
381 static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag)
386 spin_lock_irqsave(&p->lock, flags);
388 if (!(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
389 ret = sh_cmt_enable(p, &p->rate);
395 /* setup timeout if no clockevent */
396 if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT)))
397 __sh_cmt_set_next(p, p->max_match_value);
399 spin_unlock_irqrestore(&p->lock, flags);
404 static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag)
409 spin_lock_irqsave(&p->lock, flags);
411 f = p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
414 if (f && !(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
417 /* adjust the timeout to maximum if only clocksource left */
418 if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE))
419 __sh_cmt_set_next(p, p->max_match_value);
421 spin_unlock_irqrestore(&p->lock, flags);
424 static struct sh_cmt_priv *cs_to_sh_cmt(struct clocksource *cs)
426 return container_of(cs, struct sh_cmt_priv, cs);
429 static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
431 struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
432 unsigned long flags, raw;
436 spin_lock_irqsave(&p->lock, flags);
437 value = p->total_cycles;
438 raw = sh_cmt_get_counter(p, &has_wrapped);
440 if (unlikely(has_wrapped))
441 raw += p->match_value + 1;
442 spin_unlock_irqrestore(&p->lock, flags);
447 static int sh_cmt_clocksource_enable(struct clocksource *cs)
450 struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
454 ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
456 __clocksource_updatefreq_hz(cs, p->rate);
460 static void sh_cmt_clocksource_disable(struct clocksource *cs)
462 sh_cmt_stop(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
465 static void sh_cmt_clocksource_resume(struct clocksource *cs)
467 sh_cmt_start(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
470 static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
471 char *name, unsigned long rating)
473 struct clocksource *cs = &p->cs;
477 cs->read = sh_cmt_clocksource_read;
478 cs->enable = sh_cmt_clocksource_enable;
479 cs->disable = sh_cmt_clocksource_disable;
480 cs->suspend = sh_cmt_clocksource_disable;
481 cs->resume = sh_cmt_clocksource_resume;
482 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
483 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
485 dev_info(&p->pdev->dev, "used as clock source\n");
487 /* Register with dummy 1 Hz value, gets updated in ->enable() */
488 clocksource_register_hz(cs, 1);
492 static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced)
494 return container_of(ced, struct sh_cmt_priv, ced);
497 static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic)
499 struct clock_event_device *ced = &p->ced;
501 sh_cmt_start(p, FLAG_CLOCKEVENT);
503 /* TODO: calculate good shift from rate and counter bit width */
506 ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
507 ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced);
508 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
511 sh_cmt_set_next(p, ((p->rate + HZ/2) / HZ) - 1);
513 sh_cmt_set_next(p, p->max_match_value);
516 static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
517 struct clock_event_device *ced)
519 struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
521 /* deal with old setting first */
523 case CLOCK_EVT_MODE_PERIODIC:
524 case CLOCK_EVT_MODE_ONESHOT:
525 sh_cmt_stop(p, FLAG_CLOCKEVENT);
532 case CLOCK_EVT_MODE_PERIODIC:
533 dev_info(&p->pdev->dev, "used for periodic clock events\n");
534 sh_cmt_clock_event_start(p, 1);
536 case CLOCK_EVT_MODE_ONESHOT:
537 dev_info(&p->pdev->dev, "used for oneshot clock events\n");
538 sh_cmt_clock_event_start(p, 0);
540 case CLOCK_EVT_MODE_SHUTDOWN:
541 case CLOCK_EVT_MODE_UNUSED:
542 sh_cmt_stop(p, FLAG_CLOCKEVENT);
549 static int sh_cmt_clock_event_next(unsigned long delta,
550 struct clock_event_device *ced)
552 struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
554 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
555 if (likely(p->flags & FLAG_IRQCONTEXT))
556 p->next_match_value = delta - 1;
558 sh_cmt_set_next(p, delta - 1);
563 static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
564 char *name, unsigned long rating)
566 struct clock_event_device *ced = &p->ced;
568 memset(ced, 0, sizeof(*ced));
571 ced->features = CLOCK_EVT_FEAT_PERIODIC;
572 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
573 ced->rating = rating;
574 ced->cpumask = cpumask_of(0);
575 ced->set_next_event = sh_cmt_clock_event_next;
576 ced->set_mode = sh_cmt_clock_event_mode;
578 dev_info(&p->pdev->dev, "used for clock events\n");
579 clockevents_register_device(ced);
582 static int sh_cmt_register(struct sh_cmt_priv *p, char *name,
583 unsigned long clockevent_rating,
584 unsigned long clocksource_rating)
586 if (p->width == (sizeof(p->max_match_value) * 8))
587 p->max_match_value = ~0;
589 p->max_match_value = (1 << p->width) - 1;
591 p->match_value = p->max_match_value;
592 spin_lock_init(&p->lock);
594 if (clockevent_rating)
595 sh_cmt_register_clockevent(p, name, clockevent_rating);
597 if (clocksource_rating)
598 sh_cmt_register_clocksource(p, name, clocksource_rating);
603 static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
605 struct sh_timer_config *cfg = pdev->dev.platform_data;
606 struct resource *res;
610 memset(p, 0, sizeof(*p));
614 dev_err(&p->pdev->dev, "missing platform data\n");
618 platform_set_drvdata(pdev, p);
620 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
622 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
626 irq = platform_get_irq(p->pdev, 0);
628 dev_err(&p->pdev->dev, "failed to get irq\n");
632 /* map memory, let mapbase point to our channel */
633 p->mapbase = ioremap_nocache(res->start, resource_size(res));
634 if (p->mapbase == NULL) {
635 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
639 /* request irq using setup_irq() (too early for request_irq()) */
640 p->irqaction.name = dev_name(&p->pdev->dev);
641 p->irqaction.handler = sh_cmt_interrupt;
642 p->irqaction.dev_id = p;
643 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
644 IRQF_IRQPOLL | IRQF_NOBALANCING;
646 /* get hold of clock */
647 p->clk = clk_get(&p->pdev->dev, "cmt_fck");
648 if (IS_ERR(p->clk)) {
649 dev_err(&p->pdev->dev, "cannot get clock\n");
650 ret = PTR_ERR(p->clk);
654 if (resource_size(res) == 6) {
656 p->overflow_bit = 0x80;
657 p->clear_bits = ~0x80;
660 p->overflow_bit = 0x8000;
661 p->clear_bits = ~0xc000;
664 ret = sh_cmt_register(p, (char *)dev_name(&p->pdev->dev),
665 cfg->clockevent_rating,
666 cfg->clocksource_rating);
668 dev_err(&p->pdev->dev, "registration failed\n");
672 ret = setup_irq(irq, &p->irqaction);
674 dev_err(&p->pdev->dev, "failed to request irq %d\n", irq);
686 static int __devinit sh_cmt_probe(struct platform_device *pdev)
688 struct sh_cmt_priv *p = platform_get_drvdata(pdev);
692 dev_info(&pdev->dev, "kept as earlytimer\n");
696 p = kmalloc(sizeof(*p), GFP_KERNEL);
698 dev_err(&pdev->dev, "failed to allocate driver data\n");
702 ret = sh_cmt_setup(p, pdev);
705 platform_set_drvdata(pdev, NULL);
710 static int __devexit sh_cmt_remove(struct platform_device *pdev)
712 return -EBUSY; /* cannot unregister clockevent and clocksource */
715 static struct platform_driver sh_cmt_device_driver = {
716 .probe = sh_cmt_probe,
717 .remove = __devexit_p(sh_cmt_remove),
723 static int __init sh_cmt_init(void)
725 return platform_driver_register(&sh_cmt_device_driver);
728 static void __exit sh_cmt_exit(void)
730 platform_driver_unregister(&sh_cmt_device_driver);
733 early_platform_init("earlytimer", &sh_cmt_device_driver);
734 module_init(sh_cmt_init);
735 module_exit(sh_cmt_exit);
737 MODULE_AUTHOR("Magnus Damm");
738 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
739 MODULE_LICENSE("GPL v2");