1 #include <linux/init.h>
2 #include <linux/clocksource.h>
3 #include <linux/clockchips.h>
4 #include <linux/interrupt.h>
9 #include <linux/ioport.h>
11 #include <linux/platform_device.h>
12 #include <linux/atmel_tc.h>
16 * We're configured to use a specific TC block, one that's not hooked
17 * up to external hardware, to provide a time solution:
19 * - Two channels combine to create a free-running 32 bit counter
20 * with a base rate of 5+ MHz, packaged as a clocksource (with
21 * resolution better than 200 nsec).
22 * - Some chips support 32 bit counter. A single channel is used for
23 * this 32 bit free-running counter. the second channel is not used.
25 * - The third channel may be used to provide a 16-bit clockevent
26 * source, used in either periodic or oneshot mode. This runs
27 * at 32 KiHZ, and can handle delays of up to two seconds.
29 * A boot clocksource and clockevent source are also currently needed,
30 * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
31 * this code can be used when init_timers() is called, well before most
32 * devices are set up. (Some low end AT91 parts, which can run uClinux,
33 * have only the timers in one TC block... they currently don't support
34 * the tclib code, because of that initialization issue.)
36 * REVISIT behavior during system suspend states... we should disable
37 * all clocks and save the power. Easily done for clockevent devices,
38 * but clocksources won't necessarily get the needed notifications.
39 * For deeper system sleep states, this will be mandatory...
42 static void __iomem *tcaddr;
44 static cycle_t tc_get_cycles(struct clocksource *cs)
49 raw_local_irq_save(flags);
51 upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
52 lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
53 } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
55 raw_local_irq_restore(flags);
56 return (upper << 16) | lower;
59 static cycle_t tc_get_cycles32(struct clocksource *cs)
61 return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
64 static struct clocksource clksrc = {
67 .read = tc_get_cycles,
68 .mask = CLOCKSOURCE_MASK(32),
69 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
72 #ifdef CONFIG_GENERIC_CLOCKEVENTS
74 struct tc_clkevt_device {
75 struct clock_event_device clkevt;
80 static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
82 return container_of(clkevt, struct tc_clkevt_device, clkevt);
85 /* For now, we always use the 32K clock ... this optimizes for NO_HZ,
86 * because using one of the divided clocks would usually mean the
87 * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
89 * A divided clock could be good for high resolution timers, since
90 * 30.5 usec resolution can seem "low".
92 static u32 timer_clock;
94 static int tc_shutdown(struct clock_event_device *d)
96 struct tc_clkevt_device *tcd = to_tc_clkevt(d);
97 void __iomem *regs = tcd->regs;
99 __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
100 __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
101 clk_disable(tcd->clk);
106 static int tc_set_oneshot(struct clock_event_device *d)
108 struct tc_clkevt_device *tcd = to_tc_clkevt(d);
109 void __iomem *regs = tcd->regs;
111 if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
114 clk_enable(tcd->clk);
116 /* slow clock, count up to RC, then irq and stop */
117 __raw_writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |
118 ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
119 __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
121 /* set_next_event() configures and starts the timer */
125 static int tc_set_periodic(struct clock_event_device *d)
127 struct tc_clkevt_device *tcd = to_tc_clkevt(d);
128 void __iomem *regs = tcd->regs;
130 if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
133 /* By not making the gentime core emulate periodic mode on top
134 * of oneshot, we get lower overhead and improved accuracy.
136 clk_enable(tcd->clk);
138 /* slow clock, count up to RC, then irq and restart */
139 __raw_writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
140 regs + ATMEL_TC_REG(2, CMR));
141 __raw_writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
143 /* Enable clock and interrupts on RC compare */
144 __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
147 __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs +
148 ATMEL_TC_REG(2, CCR));
152 static int tc_next_event(unsigned long delta, struct clock_event_device *d)
154 __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
157 __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
158 tcaddr + ATMEL_TC_REG(2, CCR));
162 static struct tc_clkevt_device clkevt = {
165 .features = CLOCK_EVT_FEAT_PERIODIC |
166 CLOCK_EVT_FEAT_ONESHOT,
167 /* Should be lower than at91rm9200's system timer */
169 .set_next_event = tc_next_event,
170 .set_state_shutdown = tc_shutdown,
171 .set_state_periodic = tc_set_periodic,
172 .set_state_oneshot = tc_set_oneshot,
176 static irqreturn_t ch2_irq(int irq, void *handle)
178 struct tc_clkevt_device *dev = handle;
181 sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
182 if (sr & ATMEL_TC_CPCS) {
183 dev->clkevt.event_handler(&dev->clkevt);
190 static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
193 struct clk *t2_clk = tc->clk[2];
194 int irq = tc->irq[2];
196 /* try to enable t2 clk to avoid future errors in mode change */
197 ret = clk_prepare_enable(t2_clk);
202 clkevt.regs = tc->regs;
205 timer_clock = clk32k_divisor_idx;
207 clkevt.clkevt.cpumask = cpumask_of(0);
209 ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
211 clk_disable_unprepare(t2_clk);
215 clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);
220 #else /* !CONFIG_GENERIC_CLOCKEVENTS */
222 static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
230 static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
232 /* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */
233 __raw_writel(mck_divisor_idx /* likely divide-by-8 */
235 | ATMEL_TC_WAVESEL_UP /* free-run */
236 | ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */
237 | ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */
238 tcaddr + ATMEL_TC_REG(0, CMR));
239 __raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
240 __raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
241 __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
242 __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
244 /* channel 1: waveform mode, input TIOA0 */
245 __raw_writel(ATMEL_TC_XC1 /* input: TIOA0 */
247 | ATMEL_TC_WAVESEL_UP, /* free-run */
248 tcaddr + ATMEL_TC_REG(1, CMR));
249 __raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
250 __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
252 /* chain channel 0 to channel 1*/
253 __raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
254 /* then reset all the timers */
255 __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
258 static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
260 /* channel 0: waveform mode, input mclk/8 */
261 __raw_writel(mck_divisor_idx /* likely divide-by-8 */
263 | ATMEL_TC_WAVESEL_UP, /* free-run */
264 tcaddr + ATMEL_TC_REG(0, CMR));
265 __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
266 __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
268 /* then reset all the timers */
269 __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
272 static int __init tcb_clksrc_init(void)
274 static char bootinfo[] __initdata
275 = KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
277 struct platform_device *pdev;
280 u32 rate, divided_rate = 0;
281 int best_divisor_idx = -1;
282 int clk32k_divisor_idx = -1;
286 tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK);
288 pr_debug("can't alloc TC for clocksource\n");
295 ret = clk_prepare_enable(t0_clk);
297 pr_debug("can't enable T0 clk\n");
301 /* How fast will we be counting? Pick something over 5 MHz. */
302 rate = (u32) clk_get_rate(t0_clk);
303 for (i = 0; i < 5; i++) {
304 unsigned divisor = atmel_tc_divisors[i];
307 /* remember 32 KiHz clock for later */
309 clk32k_divisor_idx = i;
313 tmp = rate / divisor;
314 pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
315 if (best_divisor_idx > 0) {
316 if (tmp < 5 * 1000 * 1000)
320 best_divisor_idx = i;
324 printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
325 divided_rate / 1000000,
326 ((divided_rate + 500000) % 1000000) / 1000);
328 if (tc->tcb_config && tc->tcb_config->counter_width == 32) {
329 /* use apropriate function to read 32 bit counter */
330 clksrc.read = tc_get_cycles32;
331 /* setup ony channel 0 */
332 tcb_setup_single_chan(tc, best_divisor_idx);
334 /* tclib will give us three clocks no matter what the
335 * underlying platform supports.
337 ret = clk_prepare_enable(tc->clk[1]);
339 pr_debug("can't enable T1 clk\n");
342 /* setup both channel 0 & 1 */
343 tcb_setup_dual_chan(tc, best_divisor_idx);
346 /* and away we go! */
347 ret = clocksource_register_hz(&clksrc, divided_rate);
351 /* channel 2: periodic and oneshot timer support */
352 ret = setup_clkevents(tc, clk32k_divisor_idx);
354 goto err_unregister_clksrc;
358 err_unregister_clksrc:
359 clocksource_unregister(&clksrc);
362 if (!tc->tcb_config || tc->tcb_config->counter_width != 32)
363 clk_disable_unprepare(tc->clk[1]);
366 clk_disable_unprepare(t0_clk);
372 arch_initcall(tcb_clksrc_init);