2 * Faraday Technology FTTMR010 timer driver
3 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
5 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
6 * Copyright (C) 2001-2006 Storlink, Corp.
7 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
9 #include <linux/interrupt.h>
12 #include <linux/of_address.h>
13 #include <linux/of_irq.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/regmap.h>
16 #include <linux/clockchips.h>
17 #include <linux/clocksource.h>
18 #include <linux/sched_clock.h>
19 #include <linux/clk.h>
22 * Register definitions for the timers
24 #define TIMER1_COUNT (0x00)
25 #define TIMER1_LOAD (0x04)
26 #define TIMER1_MATCH1 (0x08)
27 #define TIMER1_MATCH2 (0x0c)
28 #define TIMER2_COUNT (0x10)
29 #define TIMER2_LOAD (0x14)
30 #define TIMER2_MATCH1 (0x18)
31 #define TIMER2_MATCH2 (0x1c)
32 #define TIMER3_COUNT (0x20)
33 #define TIMER3_LOAD (0x24)
34 #define TIMER3_MATCH1 (0x28)
35 #define TIMER3_MATCH2 (0x2c)
36 #define TIMER_CR (0x30)
37 #define TIMER_INTR_STATE (0x34)
38 #define TIMER_INTR_MASK (0x38)
40 #define TIMER_1_CR_ENABLE (1 << 0)
41 #define TIMER_1_CR_CLOCK (1 << 1)
42 #define TIMER_1_CR_INT (1 << 2)
43 #define TIMER_2_CR_ENABLE (1 << 3)
44 #define TIMER_2_CR_CLOCK (1 << 4)
45 #define TIMER_2_CR_INT (1 << 5)
46 #define TIMER_3_CR_ENABLE (1 << 6)
47 #define TIMER_3_CR_CLOCK (1 << 7)
48 #define TIMER_3_CR_INT (1 << 8)
49 #define TIMER_1_CR_UPDOWN (1 << 9)
50 #define TIMER_2_CR_UPDOWN (1 << 10)
51 #define TIMER_3_CR_UPDOWN (1 << 11)
52 #define TIMER_DEFAULT_FLAGS (TIMER_1_CR_UPDOWN | \
56 #define TIMER_1_INT_MATCH1 (1 << 0)
57 #define TIMER_1_INT_MATCH2 (1 << 1)
58 #define TIMER_1_INT_OVERFLOW (1 << 2)
59 #define TIMER_2_INT_MATCH1 (1 << 3)
60 #define TIMER_2_INT_MATCH2 (1 << 4)
61 #define TIMER_2_INT_OVERFLOW (1 << 5)
62 #define TIMER_3_INT_MATCH1 (1 << 6)
63 #define TIMER_3_INT_MATCH2 (1 << 7)
64 #define TIMER_3_INT_OVERFLOW (1 << 8)
65 #define TIMER_INT_ALL_MASK 0x1ff
67 static unsigned int tick_rate;
68 static void __iomem *base;
70 static u64 notrace fttmr010_read_sched_clock(void)
72 return readl(base + TIMER3_COUNT);
75 static int fttmr010_timer_set_next_event(unsigned long cycles,
76 struct clock_event_device *evt)
80 /* Setup the match register */
81 cr = readl(base + TIMER1_COUNT);
82 writel(cr + cycles, base + TIMER1_MATCH1);
83 if (readl(base + TIMER1_COUNT) - cr > cycles)
89 static int fttmr010_timer_shutdown(struct clock_event_device *evt)
94 * Disable also for oneshot: the set_next() call will arm the timer
97 /* Stop timer and interrupt. */
98 cr = readl(base + TIMER_CR);
99 cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
100 writel(cr, base + TIMER_CR);
102 /* Setup counter start from 0 */
103 writel(0, base + TIMER1_COUNT);
104 writel(0, base + TIMER1_LOAD);
106 /* enable interrupt */
107 cr = readl(base + TIMER_INTR_MASK);
108 cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
109 cr |= TIMER_1_INT_MATCH1;
110 writel(cr, base + TIMER_INTR_MASK);
112 /* start the timer */
113 cr = readl(base + TIMER_CR);
114 cr |= TIMER_1_CR_ENABLE;
115 writel(cr, base + TIMER_CR);
120 static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
122 u32 period = DIV_ROUND_CLOSEST(tick_rate, HZ);
125 /* Stop timer and interrupt */
126 cr = readl(base + TIMER_CR);
127 cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
128 writel(cr, base + TIMER_CR);
130 /* Setup timer to fire at 1/HT intervals. */
131 cr = 0xffffffff - (period - 1);
132 writel(cr, base + TIMER1_COUNT);
133 writel(cr, base + TIMER1_LOAD);
135 /* enable interrupt on overflow */
136 cr = readl(base + TIMER_INTR_MASK);
137 cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
138 cr |= TIMER_1_INT_OVERFLOW;
139 writel(cr, base + TIMER_INTR_MASK);
141 /* Start the timer */
142 cr = readl(base + TIMER_CR);
143 cr |= TIMER_1_CR_ENABLE;
144 cr |= TIMER_1_CR_INT;
145 writel(cr, base + TIMER_CR);
150 /* Use TIMER1 as clock event */
151 static struct clock_event_device fttmr010_clockevent = {
153 /* Reasonably fast and accurate clock event */
156 .features = CLOCK_EVT_FEAT_PERIODIC |
157 CLOCK_EVT_FEAT_ONESHOT,
158 .set_next_event = fttmr010_timer_set_next_event,
159 .set_state_shutdown = fttmr010_timer_shutdown,
160 .set_state_periodic = fttmr010_timer_set_periodic,
161 .set_state_oneshot = fttmr010_timer_shutdown,
162 .tick_resume = fttmr010_timer_shutdown,
166 * IRQ handler for the timer
168 static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
170 struct clock_event_device *evt = &fttmr010_clockevent;
172 evt->event_handler(evt);
176 static struct irqaction fttmr010_timer_irq = {
177 .name = "Faraday FTTMR010 Timer Tick",
179 .handler = fttmr010_timer_interrupt,
182 static int __init fttmr010_timer_common_init(struct device_node *np)
186 base = of_iomap(np, 0);
188 pr_err("Can't remap registers");
191 /* IRQ for timer 1 */
192 irq = irq_of_parse_and_map(np, 0);
194 pr_err("Can't parse IRQ");
199 * Reset the interrupt mask and status
201 writel(TIMER_INT_ALL_MASK, base + TIMER_INTR_MASK);
202 writel(0, base + TIMER_INTR_STATE);
203 writel(TIMER_DEFAULT_FLAGS, base + TIMER_CR);
206 * Setup free-running clocksource timer (interrupts
209 writel(0, base + TIMER3_COUNT);
210 writel(0, base + TIMER3_LOAD);
211 writel(0, base + TIMER3_MATCH1);
212 writel(0, base + TIMER3_MATCH2);
213 clocksource_mmio_init(base + TIMER3_COUNT,
214 "fttmr010_clocksource", tick_rate,
215 300, 32, clocksource_mmio_readl_up);
216 sched_clock_register(fttmr010_read_sched_clock, 32, tick_rate);
219 * Setup clockevent timer (interrupt-driven.)
221 writel(0, base + TIMER1_COUNT);
222 writel(0, base + TIMER1_LOAD);
223 writel(0, base + TIMER1_MATCH1);
224 writel(0, base + TIMER1_MATCH2);
225 setup_irq(irq, &fttmr010_timer_irq);
226 fttmr010_clockevent.cpumask = cpumask_of(0);
227 clockevents_config_and_register(&fttmr010_clockevent, tick_rate,
233 static int __init fttmr010_timer_of_init(struct device_node *np)
236 * These implementations require a clock reference.
237 * FIXME: we currently only support clocking using PCLK
238 * and using EXTCLK is not supported in the driver.
242 clk = of_clk_get_by_name(np, "PCLK");
244 pr_err("could not get PCLK");
247 tick_rate = clk_get_rate(clk);
249 return fttmr010_timer_common_init(np);
251 CLOCKSOURCE_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_of_init);
254 * Gemini-specific: relevant registers in the global syscon
256 #define GLOBAL_STATUS 0x04
257 #define CPU_AHB_RATIO_MASK (0x3 << 18)
258 #define CPU_AHB_1_1 (0x0 << 18)
259 #define CPU_AHB_3_2 (0x1 << 18)
260 #define CPU_AHB_24_13 (0x2 << 18)
261 #define CPU_AHB_2_1 (0x3 << 18)
262 #define REG_TO_AHB_SPEED(reg) ((((reg) >> 15) & 0x7) * 10 + 130)
264 static int __init gemini_timer_of_init(struct device_node *np)
266 static struct regmap *map;
270 map = syscon_regmap_lookup_by_phandle(np, "syscon");
272 pr_err("Can't get regmap for syscon handle\n");
275 ret = regmap_read(map, GLOBAL_STATUS, &val);
277 pr_err("Can't read syscon status register\n");
281 tick_rate = REG_TO_AHB_SPEED(val) * 1000000;
282 pr_info("Bus: %dMHz ", tick_rate / 1000000);
284 tick_rate /= 6; /* APB bus run AHB*(1/6) */
286 switch (val & CPU_AHB_RATIO_MASK) {
294 pr_cont("(24/13)\n");
301 return fttmr010_timer_common_init(np);
303 CLOCKSOURCE_OF_DECLARE(gemini, "cortina,gemini-timer", gemini_timer_of_init);