2 * Allwinner SoCs hstimer driver.
4 * Copyright (C) 2013 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/clk.h>
14 #include <linux/clockchips.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/irqreturn.h>
19 #include <linux/reset.h>
20 #include <linux/slab.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
25 #define TIMER_IRQ_EN_REG 0x00
26 #define TIMER_IRQ_EN(val) BIT(val)
27 #define TIMER_IRQ_ST_REG 0x04
28 #define TIMER_CTL_REG(val) (0x20 * (val) + 0x10)
29 #define TIMER_CTL_ENABLE BIT(0)
30 #define TIMER_CTL_RELOAD BIT(1)
31 #define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
32 #define TIMER_CTL_ONESHOT BIT(7)
33 #define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14)
34 #define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18)
35 #define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c)
36 #define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20)
38 #define TIMER_SYNC_TICKS 3
43 struct notifier_block clk_rate_cb;
47 #define to_sun5i_timer(x) \
48 container_of(x, struct sun5i_timer, clk_rate_cb)
50 struct sun5i_timer_clksrc {
51 struct sun5i_timer timer;
52 struct clocksource clksrc;
55 #define to_sun5i_timer_clksrc(x) \
56 container_of(x, struct sun5i_timer_clksrc, clksrc)
58 struct sun5i_timer_clkevt {
59 struct sun5i_timer timer;
60 struct clock_event_device clkevt;
63 #define to_sun5i_timer_clkevt(x) \
64 container_of(x, struct sun5i_timer_clkevt, clkevt)
67 * When we disable a timer, we need to wait at least for 2 cycles of
68 * the timer source clock. We will use for that the clocksource timer
69 * that is already setup and runs at the same frequency than the other
70 * timers, and we never will be disabled.
72 static void sun5i_clkevt_sync(struct sun5i_timer_clkevt *ce)
74 u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1));
76 while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
80 static void sun5i_clkevt_time_stop(struct sun5i_timer_clkevt *ce, u8 timer)
82 u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
83 writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer));
85 sun5i_clkevt_sync(ce);
88 static void sun5i_clkevt_time_setup(struct sun5i_timer_clkevt *ce, u8 timer, u32 delay)
90 writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer));
93 static void sun5i_clkevt_time_start(struct sun5i_timer_clkevt *ce, u8 timer, bool periodic)
95 u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
98 val &= ~TIMER_CTL_ONESHOT;
100 val |= TIMER_CTL_ONESHOT;
102 writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
103 ce->timer.base + TIMER_CTL_REG(timer));
106 static void sun5i_clkevt_mode(enum clock_event_mode mode,
107 struct clock_event_device *clkevt)
109 struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
112 case CLOCK_EVT_MODE_PERIODIC:
113 sun5i_clkevt_time_stop(ce, 0);
114 sun5i_clkevt_time_setup(ce, 0, ce->timer.ticks_per_jiffy);
115 sun5i_clkevt_time_start(ce, 0, true);
117 case CLOCK_EVT_MODE_ONESHOT:
118 sun5i_clkevt_time_stop(ce, 0);
119 sun5i_clkevt_time_start(ce, 0, false);
121 case CLOCK_EVT_MODE_UNUSED:
122 case CLOCK_EVT_MODE_SHUTDOWN:
124 sun5i_clkevt_time_stop(ce, 0);
129 static int sun5i_clkevt_next_event(unsigned long evt,
130 struct clock_event_device *clkevt)
132 struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
134 sun5i_clkevt_time_stop(ce, 0);
135 sun5i_clkevt_time_setup(ce, 0, evt - TIMER_SYNC_TICKS);
136 sun5i_clkevt_time_start(ce, 0, false);
141 static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
143 struct sun5i_timer_clkevt *ce = (struct sun5i_timer_clkevt *)dev_id;
145 writel(0x1, ce->timer.base + TIMER_IRQ_ST_REG);
146 ce->clkevt.event_handler(&ce->clkevt);
151 static cycle_t sun5i_clksrc_read(struct clocksource *clksrc)
153 struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc);
155 return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1));
158 static int sun5i_rate_cb_clksrc(struct notifier_block *nb,
159 unsigned long event, void *data)
161 struct clk_notifier_data *ndata = data;
162 struct sun5i_timer *timer = to_sun5i_timer(nb);
163 struct sun5i_timer_clksrc *cs = container_of(timer, struct sun5i_timer_clksrc, timer);
166 case PRE_RATE_CHANGE:
167 clocksource_unregister(&cs->clksrc);
170 case POST_RATE_CHANGE:
171 clocksource_register_hz(&cs->clksrc, ndata->new_rate);
181 static int __init sun5i_setup_clocksource(struct device_node *node,
183 struct clk *clk, int irq)
185 struct sun5i_timer_clksrc *cs;
189 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
193 ret = clk_prepare_enable(clk);
195 pr_err("Couldn't enable parent clock\n");
199 rate = clk_get_rate(clk);
201 cs->timer.base = base;
203 cs->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clksrc;
204 cs->timer.clk_rate_cb.next = NULL;
206 ret = clk_notifier_register(clk, &cs->timer.clk_rate_cb);
208 pr_err("Unable to register clock notifier.\n");
209 goto err_disable_clk;
212 writel(~0, base + TIMER_INTVAL_LO_REG(1));
213 writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
214 base + TIMER_CTL_REG(1));
216 cs->clksrc.name = node->name;
217 cs->clksrc.rating = 340;
218 cs->clksrc.read = sun5i_clksrc_read;
219 cs->clksrc.mask = CLOCKSOURCE_MASK(32);
220 cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
222 ret = clocksource_register_hz(&cs->clksrc, rate);
224 pr_err("Couldn't register clock source.\n");
225 goto err_remove_notifier;
231 clk_notifier_unregister(clk, &cs->timer.clk_rate_cb);
233 clk_disable_unprepare(clk);
239 static int sun5i_rate_cb_clkevt(struct notifier_block *nb,
240 unsigned long event, void *data)
242 struct clk_notifier_data *ndata = data;
243 struct sun5i_timer *timer = to_sun5i_timer(nb);
244 struct sun5i_timer_clkevt *ce = container_of(timer, struct sun5i_timer_clkevt, timer);
246 if (event == POST_RATE_CHANGE) {
247 clockevents_update_freq(&ce->clkevt, ndata->new_rate);
248 ce->timer.ticks_per_jiffy = DIV_ROUND_UP(ndata->new_rate, HZ);
254 static int __init sun5i_setup_clockevent(struct device_node *node, void __iomem *base,
255 struct clk *clk, int irq)
257 struct sun5i_timer_clkevt *ce;
262 ce = kzalloc(sizeof(*ce), GFP_KERNEL);
266 ret = clk_prepare_enable(clk);
268 pr_err("Couldn't enable parent clock\n");
272 rate = clk_get_rate(clk);
274 ce->timer.base = base;
275 ce->timer.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
277 ce->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clkevt;
278 ce->timer.clk_rate_cb.next = NULL;
280 ret = clk_notifier_register(clk, &ce->timer.clk_rate_cb);
282 pr_err("Unable to register clock notifier.\n");
283 goto err_disable_clk;
286 ce->clkevt.name = node->name;
287 ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
288 ce->clkevt.set_next_event = sun5i_clkevt_next_event;
289 ce->clkevt.set_mode = sun5i_clkevt_mode;
290 ce->clkevt.rating = 340;
291 ce->clkevt.irq = irq;
292 ce->clkevt.cpumask = cpu_possible_mask;
294 /* Enable timer0 interrupt */
295 val = readl(base + TIMER_IRQ_EN_REG);
296 writel(val | TIMER_IRQ_EN(0), base + TIMER_IRQ_EN_REG);
298 clockevents_config_and_register(&ce->clkevt, rate,
299 TIMER_SYNC_TICKS, 0xffffffff);
301 ret = request_irq(irq, sun5i_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
304 pr_err("Unable to register interrupt\n");
305 goto err_remove_notifier;
311 clk_notifier_unregister(clk, &ce->timer.clk_rate_cb);
313 clk_disable_unprepare(clk);
319 static void __init sun5i_timer_init(struct device_node *node)
321 struct reset_control *rstc;
322 void __iomem *timer_base;
326 timer_base = of_io_request_and_map(node, 0, of_node_full_name(node));
328 panic("Can't map registers");
330 irq = irq_of_parse_and_map(node, 0);
332 panic("Can't parse IRQ");
334 clk = of_clk_get(node, 0);
336 panic("Can't get timer clock");
338 rstc = of_reset_control_get(node, NULL);
340 reset_control_deassert(rstc);
342 sun5i_setup_clocksource(node, timer_base, clk, irq);
343 sun5i_setup_clockevent(node, timer_base, clk, irq);
345 CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
347 CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",