drivers/cpufreq/exynos4210-cpufreq.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS4210 - CPU frequency scaling support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/err.h>
  15 #include <linux/clk.h>
  16 #include <linux/io.h>
  17 #include <linux/slab.h>
  18 #include <linux/cpufreq.h>
  19
  20 #include <mach/regs-clock.h>
  21 #include <mach/cpufreq.h>
  22
  23 #define CPUFREQ_LEVEL_END       L5
  24
  25 static struct clk *cpu_clk;
  26 static struct clk *moutcore;
  27 static struct clk *mout_mpll;
  28 static struct clk *mout_apll;
  29
  30 struct cpufreq_clkdiv {
  31         unsigned int index;
  32         unsigned int clkdiv;
  33 };
  34
  35 static unsigned int exynos4210_volt_table[CPUFREQ_LEVEL_END] = {
  36         1250000, 1150000, 1050000, 975000, 950000,
  37 };
  38
  39
  40 static struct cpufreq_clkdiv exynos4210_clkdiv_table[CPUFREQ_LEVEL_END];
  41
  42 static struct cpufreq_frequency_table exynos4210_freq_table[] = {
  43         {L0, 1200*1000},
  44         {L1, 1000*1000},
  45         {L2, 800*1000},
  46         {L3, 500*1000},
  47         {L4, 200*1000},
  48         {0, CPUFREQ_TABLE_END},
  49 };
  50
  51 static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
  52         /*
  53          * Clock divider value for following
  54          * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
  55          *              DIVATB, DIVPCLK_DBG, DIVAPLL }
  56          */
  57
  58         /* ARM L0: 1200MHz */
  59         { 0, 3, 7, 3, 4, 1, 7 },
  60
  61         /* ARM L1: 1000MHz */
  62         { 0, 3, 7, 3, 4, 1, 7 },
  63
  64         /* ARM L2: 800MHz */
  65         { 0, 3, 7, 3, 3, 1, 7 },
  66
  67         /* ARM L3: 500MHz */
  68         { 0, 3, 7, 3, 3, 1, 7 },
  69
  70         /* ARM L4: 200MHz */
  71         { 0, 1, 3, 1, 3, 1, 0 },
  72 };
  73
  74 static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
  75         /*
  76          * Clock divider value for following
  77          * { DIVCOPY, DIVHPM }
  78          */
  79
  80         /* ARM L0: 1200MHz */
  81         { 5, 0 },
  82
  83         /* ARM L1: 1000MHz */
  84         { 4, 0 },
  85
  86         /* ARM L2: 800MHz */
  87         { 3, 0 },
  88
  89         /* ARM L3: 500MHz */
  90         { 3, 0 },
  91
  92         /* ARM L4: 200MHz */
  93         { 3, 0 },
  94 };
  95
  96 static unsigned int exynos4210_apll_pms_table[CPUFREQ_LEVEL_END] = {
  97         /* APLL FOUT L0: 1200MHz */
  98         ((150 << 16) | (3 << 8) | 1),
  99
 100         /* APLL FOUT L1: 1000MHz */
 101         ((250 << 16) | (6 << 8) | 1),
 102
 103         /* APLL FOUT L2: 800MHz */
 104         ((200 << 16) | (6 << 8) | 1),
 105
 106         /* APLL FOUT L3: 500MHz */
 107         ((250 << 16) | (6 << 8) | 2),
 108
 109         /* APLL FOUT L4: 200MHz */
 110         ((200 << 16) | (6 << 8) | 3),
 111 };
 112
 113 static void exynos4210_set_clkdiv(unsigned int div_index)
 114 {
 115         unsigned int tmp;
 116
 117         /* Change Divider - CPU0 */
 118
 119         tmp = exynos4210_clkdiv_table[div_index].clkdiv;
 120
 121         __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
 122
 123         do {
 124                 tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
 125         } while (tmp & 0x1111111);
 126
 127         /* Change Divider - CPU1 */
 128
 129         tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1);
 130
 131         tmp &= ~((0x7 << 4) | 0x7);
 132
 133         tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
 134                 (clkdiv_cpu1[div_index][1] << 0));
 135
 136         __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
 137
 138         do {
 139                 tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
 140         } while (tmp & 0x11);
 141 }
 142
 143 static void exynos4210_set_apll(unsigned int index)
 144 {
 145         unsigned int tmp;
 146
 147         /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
 148         clk_set_parent(moutcore, mout_mpll);
 149
 150         do {
 151                 tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
 152                         >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
 153                 tmp &= 0x7;
 154         } while (tmp != 0x2);
 155
 156         /* 2. Set APLL Lock time */
 157         __raw_writel(EXYNOS4_APLL_LOCKTIME, EXYNOS4_APLL_LOCK);
 158
 159         /* 3. Change PLL PMS values */
 160         tmp = __raw_readl(EXYNOS4_APLL_CON0);
 161         tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
 162         tmp |= exynos4210_apll_pms_table[index];
 163         __raw_writel(tmp, EXYNOS4_APLL_CON0);
 164
 165         /* 4. wait_lock_time */
 166         do {
 167                 tmp = __raw_readl(EXYNOS4_APLL_CON0);
 168         } while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT)));
 169
 170         /* 5. MUX_CORE_SEL = APLL */
 171         clk_set_parent(moutcore, mout_apll);
 172
 173         do {
 174                 tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
 175                 tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
 176         } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
 177 }
 178
 179 bool exynos4210_pms_change(unsigned int old_index, unsigned int new_index)
 180 {
 181         unsigned int old_pm = (exynos4210_apll_pms_table[old_index] >> 8);
 182         unsigned int new_pm = (exynos4210_apll_pms_table[new_index] >> 8);
 183
 184         return (old_pm == new_pm) ? 0 : 1;
 185 }
 186
 187 static void exynos4210_set_frequency(unsigned int old_index,
 188                                      unsigned int new_index)
 189 {
 190         unsigned int tmp;
 191
 192         if (old_index > new_index) {
 193                 if (!exynos4210_pms_change(old_index, new_index)) {
 194                         /* 1. Change the system clock divider values */
 195                         exynos4210_set_clkdiv(new_index);
 196
 197                         /* 2. Change just s value in apll m,p,s value */
 198                         tmp = __raw_readl(EXYNOS4_APLL_CON0);
 199                         tmp &= ~(0x7 << 0);
 200                         tmp |= (exynos4210_apll_pms_table[new_index] & 0x7);
 201                         __raw_writel(tmp, EXYNOS4_APLL_CON0);
 202                 } else {
 203                         /* Clock Configuration Procedure */
 204                         /* 1. Change the system clock divider values */
 205                         exynos4210_set_clkdiv(new_index);
 206                         /* 2. Change the apll m,p,s value */
 207                         exynos4210_set_apll(new_index);
 208                 }
 209         } else if (old_index < new_index) {
 210                 if (!exynos4210_pms_change(old_index, new_index)) {
 211                         /* 1. Change just s value in apll m,p,s value */
 212                         tmp = __raw_readl(EXYNOS4_APLL_CON0);
 213                         tmp &= ~(0x7 << 0);
 214                         tmp |= (exynos4210_apll_pms_table[new_index] & 0x7);
 215                         __raw_writel(tmp, EXYNOS4_APLL_CON0);
 216
 217                         /* 2. Change the system clock divider values */
 218                         exynos4210_set_clkdiv(new_index);
 219                 } else {
 220                         /* Clock Configuration Procedure */
 221                         /* 1. Change the apll m,p,s value */
 222                         exynos4210_set_apll(new_index);
 223                         /* 2. Change the system clock divider values */
 224                         exynos4210_set_clkdiv(new_index);
 225                 }
 226         }
 227 }
 228
 229 int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
 230 {
 231         int i;
 232         unsigned int tmp;
 233         unsigned long rate;
 234
 235         cpu_clk = clk_get(NULL, "armclk");
 236         if (IS_ERR(cpu_clk))
 237                 return PTR_ERR(cpu_clk);
 238
 239         moutcore = clk_get(NULL, "moutcore");
 240         if (IS_ERR(moutcore))
 241                 goto err_moutcore;
 242
 243         mout_mpll = clk_get(NULL, "mout_mpll");
 244         if (IS_ERR(mout_mpll))
 245                 goto err_mout_mpll;
 246
 247         rate = clk_get_rate(mout_mpll) / 1000;
 248
 249         mout_apll = clk_get(NULL, "mout_apll");
 250         if (IS_ERR(mout_apll))
 251                 goto err_mout_apll;
 252
 253         tmp = __raw_readl(EXYNOS4_CLKDIV_CPU);
 254
 255         for (i = L0; i <  CPUFREQ_LEVEL_END; i++) {
 256                 tmp &= ~(EXYNOS4_CLKDIV_CPU0_CORE_MASK |
 257                         EXYNOS4_CLKDIV_CPU0_COREM0_MASK |
 258                         EXYNOS4_CLKDIV_CPU0_COREM1_MASK |
 259                         EXYNOS4_CLKDIV_CPU0_PERIPH_MASK |
 260                         EXYNOS4_CLKDIV_CPU0_ATB_MASK |
 261                         EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK |
 262                         EXYNOS4_CLKDIV_CPU0_APLL_MASK);
 263
 264                 tmp |= ((clkdiv_cpu0[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
 265                         (clkdiv_cpu0[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
 266                         (clkdiv_cpu0[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
 267                         (clkdiv_cpu0[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
 268                         (clkdiv_cpu0[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
 269                         (clkdiv_cpu0[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
 270                         (clkdiv_cpu0[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT));
 271
 272                 exynos4210_clkdiv_table[i].clkdiv = tmp;
 273         }
 274
 275         info->mpll_freq_khz = rate;
 276         info->pll_safe_idx = L2;
 277         info->cpu_clk = cpu_clk;
 278         info->volt_table = exynos4210_volt_table;
 279         info->freq_table = exynos4210_freq_table;
 280         info->set_freq = exynos4210_set_frequency;
 281         info->need_apll_change = exynos4210_pms_change;
 282
 283         return 0;
 284
 285 err_mout_apll:
 286         clk_put(mout_mpll);
 287 err_mout_mpll:
 288         clk_put(moutcore);
 289 err_moutcore:
 290         clk_put(cpu_clk);
 291
 292         pr_debug("%s: failed initialization\n", __func__);
 293         return -EINVAL;
 294 }
 295 EXPORT_SYMBOL(exynos4210_cpufreq_init);