2 * Copyright (c) 2010-20122Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS5250 - CPU frequency scaling support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/err.h>
15 #include <linux/clk.h>
17 #include <linux/slab.h>
18 #include <linux/cpufreq.h>
20 #include <linux/of_address.h>
22 #include "exynos-cpufreq.h"
24 static struct clk *cpu_clk;
25 static struct clk *moutcore;
26 static struct clk *mout_mpll;
27 static struct clk *mout_apll;
28 static struct exynos_dvfs_info *cpufreq;
30 static unsigned int exynos5250_volt_table[] = {
31 1300000, 1250000, 1225000, 1200000, 1150000,
32 1125000, 1100000, 1075000, 1050000, 1025000,
33 1012500, 1000000, 975000, 950000, 937500,
37 static struct cpufreq_frequency_table exynos5250_freq_table[] = {
54 {0, 0, CPUFREQ_TABLE_END},
57 static struct apll_freq apll_freq_5250[] = {
61 * clock divider for ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2
62 * clock divider for COPY, HPM, RESERVED
65 APLL_FREQ(1700, 0, 3, 7, 7, 7, 3, 5, 0, 0, 2, 0, 425, 6, 0),
66 APLL_FREQ(1600, 0, 3, 7, 7, 7, 1, 4, 0, 0, 2, 0, 200, 3, 0),
67 APLL_FREQ(1500, 0, 2, 7, 7, 7, 1, 4, 0, 0, 2, 0, 250, 4, 0),
68 APLL_FREQ(1400, 0, 2, 7, 7, 6, 1, 4, 0, 0, 2, 0, 175, 3, 0),
69 APLL_FREQ(1300, 0, 2, 7, 7, 6, 1, 3, 0, 0, 2, 0, 325, 6, 0),
70 APLL_FREQ(1200, 0, 2, 7, 7, 5, 1, 3, 0, 0, 2, 0, 200, 4, 0),
71 APLL_FREQ(1100, 0, 3, 7, 7, 5, 1, 3, 0, 0, 2, 0, 275, 6, 0),
72 APLL_FREQ(1000, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 125, 3, 0),
73 APLL_FREQ(900, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 150, 4, 0),
74 APLL_FREQ(800, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 100, 3, 0),
75 APLL_FREQ(700, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 175, 3, 1),
76 APLL_FREQ(600, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 200, 4, 1),
77 APLL_FREQ(500, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 125, 3, 1),
78 APLL_FREQ(400, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 100, 3, 1),
79 APLL_FREQ(300, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 200, 4, 2),
80 APLL_FREQ(200, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 100, 3, 2),
83 static void set_clkdiv(unsigned int div_index)
87 /* Change Divider - CPU0 */
89 tmp = apll_freq_5250[div_index].clk_div_cpu0;
91 __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU0);
93 while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU0)
97 /* Change Divider - CPU1 */
98 tmp = apll_freq_5250[div_index].clk_div_cpu1;
100 __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU1);
102 while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU1) & 0x11)
106 static void set_apll(unsigned int index)
109 unsigned int freq = apll_freq_5250[index].freq;
111 /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
112 clk_set_parent(moutcore, mout_mpll);
116 tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU)
119 } while (tmp != 0x2);
121 clk_set_rate(mout_apll, freq * 1000);
123 /* MUX_CORE_SEL = APLL */
124 clk_set_parent(moutcore, mout_apll);
128 tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU);
130 } while (tmp != (0x1 << 16));
133 static void exynos5250_set_frequency(unsigned int old_index,
134 unsigned int new_index)
136 if (old_index > new_index) {
137 set_clkdiv(new_index);
139 } else if (old_index < new_index) {
141 set_clkdiv(new_index);
145 int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
147 struct device_node *np;
151 * HACK: This is a temporary workaround to get access to clock
152 * controller registers directly and remove static mappings and
153 * dependencies on platform headers. It is necessary to enable
154 * Exynos multi-platform support and will be removed together with
155 * this whole driver as soon as Exynos gets migrated to use
156 * cpufreq-cpu0 driver.
158 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5250-clock");
160 pr_err("%s: failed to find clock controller DT node\n",
165 info->cmu_regs = of_iomap(np, 0);
166 if (!info->cmu_regs) {
167 pr_err("%s: failed to map CMU registers\n", __func__);
171 cpu_clk = clk_get(NULL, "armclk");
173 return PTR_ERR(cpu_clk);
175 moutcore = clk_get(NULL, "mout_cpu");
176 if (IS_ERR(moutcore))
179 mout_mpll = clk_get(NULL, "mout_mpll");
180 if (IS_ERR(mout_mpll))
183 rate = clk_get_rate(mout_mpll) / 1000;
185 mout_apll = clk_get(NULL, "mout_apll");
186 if (IS_ERR(mout_apll))
189 info->mpll_freq_khz = rate;
191 info->pll_safe_idx = L9;
192 info->cpu_clk = cpu_clk;
193 info->volt_table = exynos5250_volt_table;
194 info->freq_table = exynos5250_freq_table;
195 info->set_freq = exynos5250_set_frequency;
208 pr_err("%s: failed initialization\n", __func__);