2 * Copyright (c) 2010-20122Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS5250 - CPU frequency scaling support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/err.h>
15 #include <linux/clk.h>
17 #include <linux/slab.h>
18 #include <linux/cpufreq.h>
21 #include <mach/regs-clock.h>
23 #include "exynos-cpufreq.h"
25 #define CPUFREQ_LEVEL_END (L15 + 1)
27 static int max_support_idx;
28 static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
29 static struct clk *cpu_clk;
30 static struct clk *moutcore;
31 static struct clk *mout_mpll;
32 static struct clk *mout_apll;
34 struct cpufreq_clkdiv {
40 static unsigned int exynos5250_volt_table[CPUFREQ_LEVEL_END];
42 static struct cpufreq_frequency_table exynos5250_freq_table[] = {
59 {0, CPUFREQ_TABLE_END},
62 static struct cpufreq_clkdiv exynos5250_clkdiv_table[CPUFREQ_LEVEL_END];
64 static unsigned int clkdiv_cpu0_5250[CPUFREQ_LEVEL_END][8] = {
66 * Clock divider value for following
67 * { ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2 }
69 { 0, 3, 7, 7, 7, 3, 5, 0 }, /* 1700 MHz */
70 { 0, 3, 7, 7, 7, 1, 4, 0 }, /* 1600 MHz */
71 { 0, 2, 7, 7, 7, 1, 4, 0 }, /* 1500 MHz */
72 { 0, 2, 7, 7, 6, 1, 4, 0 }, /* 1400 MHz */
73 { 0, 2, 7, 7, 6, 1, 3, 0 }, /* 1300 MHz */
74 { 0, 2, 7, 7, 5, 1, 3, 0 }, /* 1200 MHz */
75 { 0, 3, 7, 7, 5, 1, 3, 0 }, /* 1100 MHz */
76 { 0, 1, 7, 7, 4, 1, 2, 0 }, /* 1000 MHz */
77 { 0, 1, 7, 7, 4, 1, 2, 0 }, /* 900 MHz */
78 { 0, 1, 7, 7, 4, 1, 2, 0 }, /* 800 MHz */
79 { 0, 1, 7, 7, 3, 1, 1, 0 }, /* 700 MHz */
80 { 0, 1, 7, 7, 3, 1, 1, 0 }, /* 600 MHz */
81 { 0, 1, 7, 7, 2, 1, 1, 0 }, /* 500 MHz */
82 { 0, 1, 7, 7, 2, 1, 1, 0 }, /* 400 MHz */
83 { 0, 1, 7, 7, 1, 1, 1, 0 }, /* 300 MHz */
84 { 0, 1, 7, 7, 1, 1, 1, 0 }, /* 200 MHz */
87 static unsigned int clkdiv_cpu1_5250[CPUFREQ_LEVEL_END][2] = {
88 /* Clock divider value for following
91 { 0, 2 }, /* 1700 MHz */
92 { 0, 2 }, /* 1600 MHz */
93 { 0, 2 }, /* 1500 MHz */
94 { 0, 2 }, /* 1400 MHz */
95 { 0, 2 }, /* 1300 MHz */
96 { 0, 2 }, /* 1200 MHz */
97 { 0, 2 }, /* 1100 MHz */
98 { 0, 2 }, /* 1000 MHz */
99 { 0, 2 }, /* 900 MHz */
100 { 0, 2 }, /* 800 MHz */
101 { 0, 2 }, /* 700 MHz */
102 { 0, 2 }, /* 600 MHz */
103 { 0, 2 }, /* 500 MHz */
104 { 0, 2 }, /* 400 MHz */
105 { 0, 2 }, /* 300 MHz */
106 { 0, 2 }, /* 200 MHz */
109 static unsigned int exynos5_apll_pms_table[CPUFREQ_LEVEL_END] = {
110 ((425 << 16) | (6 << 8) | 0), /* 1700 MHz */
111 ((200 << 16) | (3 << 8) | 0), /* 1600 MHz */
112 ((250 << 16) | (4 << 8) | 0), /* 1500 MHz */
113 ((175 << 16) | (3 << 8) | 0), /* 1400 MHz */
114 ((325 << 16) | (6 << 8) | 0), /* 1300 MHz */
115 ((200 << 16) | (4 << 8) | 0), /* 1200 MHz */
116 ((275 << 16) | (6 << 8) | 0), /* 1100 MHz */
117 ((125 << 16) | (3 << 8) | 0), /* 1000 MHz */
118 ((150 << 16) | (4 << 8) | 0), /* 900 MHz */
119 ((100 << 16) | (3 << 8) | 0), /* 800 MHz */
120 ((175 << 16) | (3 << 8) | 1), /* 700 MHz */
121 ((200 << 16) | (4 << 8) | 1), /* 600 MHz */
122 ((125 << 16) | (3 << 8) | 1), /* 500 MHz */
123 ((100 << 16) | (3 << 8) | 1), /* 400 MHz */
124 ((200 << 16) | (4 << 8) | 2), /* 300 MHz */
125 ((100 << 16) | (3 << 8) | 2), /* 200 MHz */
128 /* ASV group voltage table */
129 static const unsigned int asv_voltage_5250[CPUFREQ_LEVEL_END] = {
130 1300000, 1250000, 1225000, 1200000, 1150000,
131 1125000, 1100000, 1075000, 1050000, 1025000,
132 1012500, 1000000, 975000, 950000, 937500,
136 static void set_clkdiv(unsigned int div_index)
140 /* Change Divider - CPU0 */
142 tmp = exynos5250_clkdiv_table[div_index].clkdiv;
144 __raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
146 while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
149 /* Change Divider - CPU1 */
150 tmp = exynos5250_clkdiv_table[div_index].clkdiv1;
152 __raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
154 while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
158 static void set_apll(unsigned int new_index,
159 unsigned int old_index)
161 unsigned int tmp, pdiv;
163 /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
164 clk_set_parent(moutcore, mout_mpll);
168 tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16);
170 } while (tmp != 0x2);
172 /* 2. Set APLL Lock time */
173 pdiv = ((exynos5_apll_pms_table[new_index] >> 8) & 0x3f);
175 __raw_writel((pdiv * 250), EXYNOS5_APLL_LOCK);
177 /* 3. Change PLL PMS values */
178 tmp = __raw_readl(EXYNOS5_APLL_CON0);
179 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
180 tmp |= exynos5_apll_pms_table[new_index];
181 __raw_writel(tmp, EXYNOS5_APLL_CON0);
183 /* 4. wait_lock_time */
186 tmp = __raw_readl(EXYNOS5_APLL_CON0);
187 } while (!(tmp & (0x1 << 29)));
189 /* 5. MUX_CORE_SEL = APLL */
190 clk_set_parent(moutcore, mout_apll);
194 tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
196 } while (tmp != (0x1 << 16));
200 bool exynos5250_pms_change(unsigned int old_index, unsigned int new_index)
202 unsigned int old_pm = (exynos5_apll_pms_table[old_index] >> 8);
203 unsigned int new_pm = (exynos5_apll_pms_table[new_index] >> 8);
205 return (old_pm == new_pm) ? 0 : 1;
208 static void exynos5250_set_frequency(unsigned int old_index,
209 unsigned int new_index)
213 if (old_index > new_index) {
214 if (!exynos5250_pms_change(old_index, new_index)) {
215 /* 1. Change the system clock divider values */
216 set_clkdiv(new_index);
217 /* 2. Change just s value in apll m,p,s value */
218 tmp = __raw_readl(EXYNOS5_APLL_CON0);
220 tmp |= (exynos5_apll_pms_table[new_index] & 0x7);
221 __raw_writel(tmp, EXYNOS5_APLL_CON0);
224 /* Clock Configuration Procedure */
225 /* 1. Change the system clock divider values */
226 set_clkdiv(new_index);
227 /* 2. Change the apll m,p,s value */
228 set_apll(new_index, old_index);
230 } else if (old_index < new_index) {
231 if (!exynos5250_pms_change(old_index, new_index)) {
232 /* 1. Change just s value in apll m,p,s value */
233 tmp = __raw_readl(EXYNOS5_APLL_CON0);
235 tmp |= (exynos5_apll_pms_table[new_index] & 0x7);
236 __raw_writel(tmp, EXYNOS5_APLL_CON0);
237 /* 2. Change the system clock divider values */
238 set_clkdiv(new_index);
240 /* Clock Configuration Procedure */
241 /* 1. Change the apll m,p,s value */
242 set_apll(new_index, old_index);
243 /* 2. Change the system clock divider values */
244 set_clkdiv(new_index);
249 static void __init set_volt_table(void)
253 max_support_idx = L0;
255 for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
256 exynos5250_volt_table[i] = asv_voltage_5250[i];
259 int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
267 cpu_clk = clk_get(NULL, "armclk");
269 return PTR_ERR(cpu_clk);
271 moutcore = clk_get(NULL, "mout_cpu");
272 if (IS_ERR(moutcore))
275 mout_mpll = clk_get(NULL, "mout_mpll");
276 if (IS_ERR(mout_mpll))
279 rate = clk_get_rate(mout_mpll) / 1000;
281 mout_apll = clk_get(NULL, "mout_apll");
282 if (IS_ERR(mout_apll))
285 for (i = L0; i < CPUFREQ_LEVEL_END; i++) {
287 exynos5250_clkdiv_table[i].index = i;
289 tmp = __raw_readl(EXYNOS5_CLKDIV_CPU0);
291 tmp &= ~((0x7 << 0) | (0x7 << 4) | (0x7 << 8) |
292 (0x7 << 12) | (0x7 << 16) | (0x7 << 20) |
293 (0x7 << 24) | (0x7 << 28));
295 tmp |= ((clkdiv_cpu0_5250[i][0] << 0) |
296 (clkdiv_cpu0_5250[i][1] << 4) |
297 (clkdiv_cpu0_5250[i][2] << 8) |
298 (clkdiv_cpu0_5250[i][3] << 12) |
299 (clkdiv_cpu0_5250[i][4] << 16) |
300 (clkdiv_cpu0_5250[i][5] << 20) |
301 (clkdiv_cpu0_5250[i][6] << 24) |
302 (clkdiv_cpu0_5250[i][7] << 28));
304 exynos5250_clkdiv_table[i].clkdiv = tmp;
306 tmp = __raw_readl(EXYNOS5_CLKDIV_CPU1);
308 tmp &= ~((0x7 << 0) | (0x7 << 4));
310 tmp |= ((clkdiv_cpu1_5250[i][0] << 0) |
311 (clkdiv_cpu1_5250[i][1] << 4));
313 exynos5250_clkdiv_table[i].clkdiv1 = tmp;
316 info->mpll_freq_khz = rate;
318 info->pm_lock_idx = L7;
320 info->pll_safe_idx = L9;
321 info->max_support_idx = max_support_idx;
322 info->min_support_idx = min_support_idx;
323 info->cpu_clk = cpu_clk;
324 info->volt_table = exynos5250_volt_table;
325 info->freq_table = exynos5250_freq_table;
326 info->set_freq = exynos5250_set_frequency;
327 info->need_apll_change = exynos5250_pms_change;
338 pr_err("%s: failed initialization\n", __func__);
341 EXPORT_SYMBOL(exynos5250_cpufreq_init);