drivers/cpufreq/imx6q-cpufreq.c

   1 /*
   2  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/cpu.h>
  11 #include <linux/cpufreq.h>
  12 #include <linux/delay.h>
  13 #include <linux/err.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/opp.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regulator/consumer.h>
  19
  20 #define PU_SOC_VOLTAGE_NORMAL   1250000
  21 #define PU_SOC_VOLTAGE_HIGH     1275000
  22 #define FREQ_1P2_GHZ            1200000000
  23
  24 static struct regulator *arm_reg;
  25 static struct regulator *pu_reg;
  26 static struct regulator *soc_reg;
  27
  28 static struct clk *arm_clk;
  29 static struct clk *pll1_sys_clk;
  30 static struct clk *pll1_sw_clk;
  31 static struct clk *step_clk;
  32 static struct clk *pll2_pfd2_396m_clk;
  33
  34 static struct device *cpu_dev;
  35 static struct cpufreq_frequency_table *freq_table;
  36 static unsigned int transition_latency;
  37
  38 static int imx6q_verify_speed(struct cpufreq_policy *policy)
  39 {
  40         return cpufreq_frequency_table_verify(policy, freq_table);
  41 }
  42
  43 static unsigned int imx6q_get_speed(unsigned int cpu)
  44 {
  45         return clk_get_rate(arm_clk) / 1000;
  46 }
  47
  48 static int imx6q_set_target(struct cpufreq_policy *policy,
  49                             unsigned int target_freq, unsigned int relation)
  50 {
  51         struct cpufreq_freqs freqs;
  52         struct opp *opp;
  53         unsigned long freq_hz, volt, volt_old;
  54         unsigned int index;
  55         int ret;
  56
  57         ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
  58                                              relation, &index);
  59         if (ret) {
  60                 dev_err(cpu_dev, "failed to match target frequency %d: %d\n",
  61                         target_freq, ret);
  62                 return ret;
  63         }
  64
  65         freqs.new = freq_table[index].frequency;
  66         freq_hz = freqs.new * 1000;
  67         freqs.old = clk_get_rate(arm_clk) / 1000;
  68
  69         if (freqs.old == freqs.new)
  70                 return 0;
  71
  72         rcu_read_lock();
  73         opp = opp_find_freq_ceil(cpu_dev, &freq_hz);
  74         if (IS_ERR(opp)) {
  75                 rcu_read_unlock();
  76                 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
  77                 return PTR_ERR(opp);
  78         }
  79
  80         volt = opp_get_voltage(opp);
  81         rcu_read_unlock();
  82         volt_old = regulator_get_voltage(arm_reg);
  83
  84         dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
  85                 freqs.old / 1000, volt_old / 1000,
  86                 freqs.new / 1000, volt / 1000);
  87
  88         cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
  89
  90         /* scaling up?  scale voltage before frequency */
  91         if (freqs.new > freqs.old) {
  92                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
  93                 if (ret) {
  94                         dev_err(cpu_dev,
  95                                 "failed to scale vddarm up: %d\n", ret);
  96                         freqs.new = freqs.old;
  97                         goto post_notify;
  98                 }
  99
 100                 /*
 101                  * Need to increase vddpu and vddsoc for safety
 102                  * if we are about to run at 1.2 GHz.
 103                  */
 104                 if (freqs.new == FREQ_1P2_GHZ / 1000) {
 105                         regulator_set_voltage_tol(pu_reg,
 106                                         PU_SOC_VOLTAGE_HIGH, 0);
 107                         regulator_set_voltage_tol(soc_reg,
 108                                         PU_SOC_VOLTAGE_HIGH, 0);
 109                 }
 110         }
 111
 112         /*
 113          * The setpoints are selected per PLL/PDF frequencies, so we need to
 114          * reprogram PLL for frequency scaling.  The procedure of reprogramming
 115          * PLL1 is as below.
 116          *
 117          *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
 118          *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
 119          *  - Disable pll2_pfd2_396m_clk
 120          */
 121         clk_set_parent(step_clk, pll2_pfd2_396m_clk);
 122         clk_set_parent(pll1_sw_clk, step_clk);
 123         if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
 124                 clk_set_rate(pll1_sys_clk, freqs.new * 1000);
 125                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
 126         }
 127
 128         /* Ensure the arm clock divider is what we expect */
 129         ret = clk_set_rate(arm_clk, freqs.new * 1000);
 130         if (ret) {
 131                 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
 132                 regulator_set_voltage_tol(arm_reg, volt_old, 0);
 133                 freqs.new = freqs.old;
 134                 goto post_notify;
 135         }
 136
 137         /* scaling down?  scale voltage after frequency */
 138         if (freqs.new < freqs.old) {
 139                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
 140                 if (ret) {
 141                         dev_warn(cpu_dev,
 142                                  "failed to scale vddarm down: %d\n", ret);
 143                         ret = 0;
 144                 }
 145
 146                 if (freqs.old == FREQ_1P2_GHZ / 1000) {
 147                         regulator_set_voltage_tol(pu_reg,
 148                                         PU_SOC_VOLTAGE_NORMAL, 0);
 149                         regulator_set_voltage_tol(soc_reg,
 150                                         PU_SOC_VOLTAGE_NORMAL, 0);
 151                 }
 152         }
 153
 154 post_notify:
 155         cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
 156
 157         return ret;
 158 }
 159
 160 static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
 161 {
 162         int ret;
 163
 164         ret = cpufreq_table_validate_and_show(policy, freq_table);
 165         if (ret) {
 166                 dev_err(cpu_dev, "invalid frequency table: %d\n", ret);
 167                 return ret;
 168         }
 169
 170         policy->cpuinfo.transition_latency = transition_latency;
 171         policy->cur = clk_get_rate(arm_clk) / 1000;
 172         cpumask_setall(policy->cpus);
 173
 174         return 0;
 175 }
 176
 177 static int imx6q_cpufreq_exit(struct cpufreq_policy *policy)
 178 {
 179         cpufreq_frequency_table_put_attr(policy->cpu);
 180         return 0;
 181 }
 182
 183 static struct freq_attr *imx6q_cpufreq_attr[] = {
 184         &cpufreq_freq_attr_scaling_available_freqs,
 185         NULL,
 186 };
 187
 188 static struct cpufreq_driver imx6q_cpufreq_driver = {
 189         .verify = imx6q_verify_speed,
 190         .target = imx6q_set_target,
 191         .get = imx6q_get_speed,
 192         .init = imx6q_cpufreq_init,
 193         .exit = imx6q_cpufreq_exit,
 194         .name = "imx6q-cpufreq",
 195         .attr = imx6q_cpufreq_attr,
 196 };
 197
 198 static int imx6q_cpufreq_probe(struct platform_device *pdev)
 199 {
 200         struct device_node *np;
 201         struct opp *opp;
 202         unsigned long min_volt, max_volt;
 203         int num, ret;
 204
 205         cpu_dev = get_cpu_device(0);
 206         if (!cpu_dev) {
 207                 pr_err("failed to get cpu0 device\n");
 208                 return -ENODEV;
 209         }
 210
 211         np = of_node_get(cpu_dev->of_node);
 212         if (!np) {
 213                 dev_err(cpu_dev, "failed to find cpu0 node\n");
 214                 return -ENOENT;
 215         }
 216
 217         arm_clk = devm_clk_get(cpu_dev, "arm");
 218         pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys");
 219         pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw");
 220         step_clk = devm_clk_get(cpu_dev, "step");
 221         pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m");
 222         if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
 223             IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
 224                 dev_err(cpu_dev, "failed to get clocks\n");
 225                 ret = -ENOENT;
 226                 goto put_node;
 227         }
 228
 229         arm_reg = devm_regulator_get(cpu_dev, "arm");
 230         pu_reg = devm_regulator_get(cpu_dev, "pu");
 231         soc_reg = devm_regulator_get(cpu_dev, "soc");
 232         if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) {
 233                 dev_err(cpu_dev, "failed to get regulators\n");
 234                 ret = -ENOENT;
 235                 goto put_node;
 236         }
 237
 238         /* We expect an OPP table supplied by platform */
 239         num = opp_get_opp_count(cpu_dev);
 240         if (num < 0) {
 241                 ret = num;
 242                 dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
 243                 goto put_node;
 244         }
 245
 246         ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
 247         if (ret) {
 248                 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
 249                 goto put_node;
 250         }
 251
 252         if (of_property_read_u32(np, "clock-latency", &transition_latency))
 253                 transition_latency = CPUFREQ_ETERNAL;
 254
 255         /*
 256          * OPP is maintained in order of increasing frequency, and
 257          * freq_table initialised from OPP is therefore sorted in the
 258          * same order.
 259          */
 260         rcu_read_lock();
 261         opp = opp_find_freq_exact(cpu_dev,
 262                                   freq_table[0].frequency * 1000, true);
 263         min_volt = opp_get_voltage(opp);
 264         opp = opp_find_freq_exact(cpu_dev,
 265                                   freq_table[--num].frequency * 1000, true);
 266         max_volt = opp_get_voltage(opp);
 267         rcu_read_unlock();
 268         ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
 269         if (ret > 0)
 270                 transition_latency += ret * 1000;
 271
 272         /* Count vddpu and vddsoc latency in for 1.2 GHz support */
 273         if (freq_table[num].frequency == FREQ_1P2_GHZ / 1000) {
 274                 ret = regulator_set_voltage_time(pu_reg, PU_SOC_VOLTAGE_NORMAL,
 275                                                  PU_SOC_VOLTAGE_HIGH);
 276                 if (ret > 0)
 277                         transition_latency += ret * 1000;
 278                 ret = regulator_set_voltage_time(soc_reg, PU_SOC_VOLTAGE_NORMAL,
 279                                                  PU_SOC_VOLTAGE_HIGH);
 280                 if (ret > 0)
 281                         transition_latency += ret * 1000;
 282         }
 283
 284         ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
 285         if (ret) {
 286                 dev_err(cpu_dev, "failed register driver: %d\n", ret);
 287                 goto free_freq_table;
 288         }
 289
 290         of_node_put(np);
 291         return 0;
 292
 293 free_freq_table:
 294         opp_free_cpufreq_table(cpu_dev, &freq_table);
 295 put_node:
 296         of_node_put(np);
 297         return ret;
 298 }
 299
 300 static int imx6q_cpufreq_remove(struct platform_device *pdev)
 301 {
 302         cpufreq_unregister_driver(&imx6q_cpufreq_driver);
 303         opp_free_cpufreq_table(cpu_dev, &freq_table);
 304
 305         return 0;
 306 }
 307
 308 static struct platform_driver imx6q_cpufreq_platdrv = {
 309         .driver = {
 310                 .name   = "imx6q-cpufreq",
 311                 .owner  = THIS_MODULE,
 312         },
 313         .probe          = imx6q_cpufreq_probe,
 314         .remove         = imx6q_cpufreq_remove,
 315 };
 316 module_platform_driver(imx6q_cpufreq_platdrv);
 317
 318 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
 319 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
 320 MODULE_LICENSE("GPL");