2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/cpu.h>
11 #include <linux/cpufreq.h>
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/module.h>
16 #include <linux/opp.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
20 #define PU_SOC_VOLTAGE_NORMAL 1250000
21 #define PU_SOC_VOLTAGE_HIGH 1275000
22 #define FREQ_1P2_GHZ 1200000000
24 static struct regulator *arm_reg;
25 static struct regulator *pu_reg;
26 static struct regulator *soc_reg;
28 static struct clk *arm_clk;
29 static struct clk *pll1_sys_clk;
30 static struct clk *pll1_sw_clk;
31 static struct clk *step_clk;
32 static struct clk *pll2_pfd2_396m_clk;
34 static struct device *cpu_dev;
35 static struct cpufreq_frequency_table *freq_table;
36 static unsigned int transition_latency;
38 static unsigned int imx6q_get_speed(unsigned int cpu)
40 return clk_get_rate(arm_clk) / 1000;
43 static int imx6q_set_target(struct cpufreq_policy *policy,
44 unsigned int target_freq, unsigned int relation)
46 struct cpufreq_freqs freqs;
48 unsigned long freq_hz, volt, volt_old;
52 ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
55 dev_err(cpu_dev, "failed to match target frequency %d: %d\n",
60 freqs.new = freq_table[index].frequency;
61 freq_hz = freqs.new * 1000;
62 freqs.old = clk_get_rate(arm_clk) / 1000;
64 if (freqs.old == freqs.new)
68 opp = opp_find_freq_ceil(cpu_dev, &freq_hz);
71 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
75 volt = opp_get_voltage(opp);
77 volt_old = regulator_get_voltage(arm_reg);
79 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
80 freqs.old / 1000, volt_old / 1000,
81 freqs.new / 1000, volt / 1000);
83 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
85 /* scaling up? scale voltage before frequency */
86 if (freqs.new > freqs.old) {
87 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
90 "failed to scale vddarm up: %d\n", ret);
91 freqs.new = freqs.old;
96 * Need to increase vddpu and vddsoc for safety
97 * if we are about to run at 1.2 GHz.
99 if (freqs.new == FREQ_1P2_GHZ / 1000) {
100 regulator_set_voltage_tol(pu_reg,
101 PU_SOC_VOLTAGE_HIGH, 0);
102 regulator_set_voltage_tol(soc_reg,
103 PU_SOC_VOLTAGE_HIGH, 0);
108 * The setpoints are selected per PLL/PDF frequencies, so we need to
109 * reprogram PLL for frequency scaling. The procedure of reprogramming
112 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
113 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
114 * - Disable pll2_pfd2_396m_clk
116 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
117 clk_set_parent(pll1_sw_clk, step_clk);
118 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
119 clk_set_rate(pll1_sys_clk, freqs.new * 1000);
120 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
123 /* Ensure the arm clock divider is what we expect */
124 ret = clk_set_rate(arm_clk, freqs.new * 1000);
126 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
127 regulator_set_voltage_tol(arm_reg, volt_old, 0);
128 freqs.new = freqs.old;
132 /* scaling down? scale voltage after frequency */
133 if (freqs.new < freqs.old) {
134 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
137 "failed to scale vddarm down: %d\n", ret);
141 if (freqs.old == FREQ_1P2_GHZ / 1000) {
142 regulator_set_voltage_tol(pu_reg,
143 PU_SOC_VOLTAGE_NORMAL, 0);
144 regulator_set_voltage_tol(soc_reg,
145 PU_SOC_VOLTAGE_NORMAL, 0);
150 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
155 static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
157 return cpufreq_generic_init(policy, freq_table, transition_latency);
160 static struct cpufreq_driver imx6q_cpufreq_driver = {
161 .verify = cpufreq_generic_frequency_table_verify,
162 .target = imx6q_set_target,
163 .get = imx6q_get_speed,
164 .init = imx6q_cpufreq_init,
165 .exit = cpufreq_generic_exit,
166 .name = "imx6q-cpufreq",
167 .attr = cpufreq_generic_attr,
170 static int imx6q_cpufreq_probe(struct platform_device *pdev)
172 struct device_node *np;
174 unsigned long min_volt, max_volt;
177 cpu_dev = get_cpu_device(0);
179 pr_err("failed to get cpu0 device\n");
183 np = of_node_get(cpu_dev->of_node);
185 dev_err(cpu_dev, "failed to find cpu0 node\n");
189 arm_clk = devm_clk_get(cpu_dev, "arm");
190 pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys");
191 pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw");
192 step_clk = devm_clk_get(cpu_dev, "step");
193 pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m");
194 if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
195 IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
196 dev_err(cpu_dev, "failed to get clocks\n");
201 arm_reg = devm_regulator_get(cpu_dev, "arm");
202 pu_reg = devm_regulator_get(cpu_dev, "pu");
203 soc_reg = devm_regulator_get(cpu_dev, "soc");
204 if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) {
205 dev_err(cpu_dev, "failed to get regulators\n");
210 /* We expect an OPP table supplied by platform */
211 num = opp_get_opp_count(cpu_dev);
214 dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
218 ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
220 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
224 if (of_property_read_u32(np, "clock-latency", &transition_latency))
225 transition_latency = CPUFREQ_ETERNAL;
228 * OPP is maintained in order of increasing frequency, and
229 * freq_table initialised from OPP is therefore sorted in the
233 opp = opp_find_freq_exact(cpu_dev,
234 freq_table[0].frequency * 1000, true);
235 min_volt = opp_get_voltage(opp);
236 opp = opp_find_freq_exact(cpu_dev,
237 freq_table[--num].frequency * 1000, true);
238 max_volt = opp_get_voltage(opp);
240 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
242 transition_latency += ret * 1000;
244 /* Count vddpu and vddsoc latency in for 1.2 GHz support */
245 if (freq_table[num].frequency == FREQ_1P2_GHZ / 1000) {
246 ret = regulator_set_voltage_time(pu_reg, PU_SOC_VOLTAGE_NORMAL,
247 PU_SOC_VOLTAGE_HIGH);
249 transition_latency += ret * 1000;
250 ret = regulator_set_voltage_time(soc_reg, PU_SOC_VOLTAGE_NORMAL,
251 PU_SOC_VOLTAGE_HIGH);
253 transition_latency += ret * 1000;
256 ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
258 dev_err(cpu_dev, "failed register driver: %d\n", ret);
259 goto free_freq_table;
266 opp_free_cpufreq_table(cpu_dev, &freq_table);
272 static int imx6q_cpufreq_remove(struct platform_device *pdev)
274 cpufreq_unregister_driver(&imx6q_cpufreq_driver);
275 opp_free_cpufreq_table(cpu_dev, &freq_table);
280 static struct platform_driver imx6q_cpufreq_platdrv = {
282 .name = "imx6q-cpufreq",
283 .owner = THIS_MODULE,
285 .probe = imx6q_cpufreq_probe,
286 .remove = imx6q_cpufreq_remove,
288 module_platform_driver(imx6q_cpufreq_platdrv);
290 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
291 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
292 MODULE_LICENSE("GPL");