drivers/cpufreq/intel_pstate.c

   1 /*
   2  * intel_pstate.c: Native P state management for Intel processors
   3  *
   4  * (C) Copyright 2012 Intel Corporation
   5  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; version 2
  10  * of the License.
  11  */
  12
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/kernel_stat.h>
  17 #include <linux/module.h>
  18 #include <linux/ktime.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/tick.h>
  21 #include <linux/slab.h>
  22 #include <linux/sched/cpufreq.h>
  23 #include <linux/list.h>
  24 #include <linux/cpu.h>
  25 #include <linux/cpufreq.h>
  26 #include <linux/sysfs.h>
  27 #include <linux/types.h>
  28 #include <linux/fs.h>
  29 #include <linux/debugfs.h>
  30 #include <linux/acpi.h>
  31 #include <linux/vmalloc.h>
  32 #include <trace/events/power.h>
  33
  34 #include <asm/div64.h>
  35 #include <asm/msr.h>
  36 #include <asm/cpu_device_id.h>
  37 #include <asm/cpufeature.h>
  38 #include <asm/intel-family.h>
  39
  40 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
  41
  42 #ifdef CONFIG_ACPI
  43 #include <acpi/processor.h>
  44 #include <acpi/cppc_acpi.h>
  45 #endif
  46
  47 #define FRAC_BITS 8
  48 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  49 #define fp_toint(X) ((X) >> FRAC_BITS)
  50
  51 #define EXT_BITS 6
  52 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
  53 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
  54 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
  55
  56 static inline int32_t mul_fp(int32_t x, int32_t y)
  57 {
  58         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  59 }
  60
  61 static inline int32_t div_fp(s64 x, s64 y)
  62 {
  63         return div64_s64((int64_t)x << FRAC_BITS, y);
  64 }
  65
  66 static inline int ceiling_fp(int32_t x)
  67 {
  68         int mask, ret;
  69
  70         ret = fp_toint(x);
  71         mask = (1 << FRAC_BITS) - 1;
  72         if (x & mask)
  73                 ret += 1;
  74         return ret;
  75 }
  76
  77 static inline u64 mul_ext_fp(u64 x, u64 y)
  78 {
  79         return (x * y) >> EXT_FRAC_BITS;
  80 }
  81
  82 static inline u64 div_ext_fp(u64 x, u64 y)
  83 {
  84         return div64_u64(x << EXT_FRAC_BITS, y);
  85 }
  86
  87 /**
  88  * struct sample -      Store performance sample
  89  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
  90  *                      performance during last sample period
  91  * @busy_scaled:        Scaled busy value which is used to calculate next
  92  *                      P state. This can be different than core_avg_perf
  93  *                      to account for cpu idle period
  94  * @aperf:              Difference of actual performance frequency clock count
  95  *                      read from APERF MSR between last and current sample
  96  * @mperf:              Difference of maximum performance frequency clock count
  97  *                      read from MPERF MSR between last and current sample
  98  * @tsc:                Difference of time stamp counter between last and
  99  *                      current sample
 100  * @time:               Current time from scheduler
 101  *
 102  * This structure is used in the cpudata structure to store performance sample
 103  * data for choosing next P State.
 104  */
 105 struct sample {
 106         int32_t core_avg_perf;
 107         int32_t busy_scaled;
 108         u64 aperf;
 109         u64 mperf;
 110         u64 tsc;
 111         u64 time;
 112 };
 113
 114 /**
 115  * struct pstate_data - Store P state data
 116  * @current_pstate:     Current requested P state
 117  * @min_pstate:         Min P state possible for this platform
 118  * @max_pstate:         Max P state possible for this platform
 119  * @max_pstate_physical:This is physical Max P state for a processor
 120  *                      This can be higher than the max_pstate which can
 121  *                      be limited by platform thermal design power limits
 122  * @scaling:            Scaling factor to  convert frequency to cpufreq
 123  *                      frequency units
 124  * @turbo_pstate:       Max Turbo P state possible for this platform
 125  * @max_freq:           @max_pstate frequency in cpufreq units
 126  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
 127  *
 128  * Stores the per cpu model P state limits and current P state.
 129  */
 130 struct pstate_data {
 131         int     current_pstate;
 132         int     min_pstate;
 133         int     max_pstate;
 134         int     max_pstate_physical;
 135         int     scaling;
 136         int     turbo_pstate;
 137         unsigned int max_freq;
 138         unsigned int turbo_freq;
 139 };
 140
 141 /**
 142  * struct vid_data -    Stores voltage information data
 143  * @min:                VID data for this platform corresponding to
 144  *                      the lowest P state
 145  * @max:                VID data corresponding to the highest P State.
 146  * @turbo:              VID data for turbo P state
 147  * @ratio:              Ratio of (vid max - vid min) /
 148  *                      (max P state - Min P State)
 149  *
 150  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
 151  * This data is used in Atom platforms, where in addition to target P state,
 152  * the voltage data needs to be specified to select next P State.
 153  */
 154 struct vid_data {
 155         int min;
 156         int max;
 157         int turbo;
 158         int32_t ratio;
 159 };
 160
 161 /**
 162  * struct _pid -        Stores PID data
 163  * @setpoint:           Target set point for busyness or performance
 164  * @integral:           Storage for accumulated error values
 165  * @p_gain:             PID proportional gain
 166  * @i_gain:             PID integral gain
 167  * @d_gain:             PID derivative gain
 168  * @deadband:           PID deadband
 169  * @last_err:           Last error storage for integral part of PID calculation
 170  *
 171  * Stores PID coefficients and last error for PID controller.
 172  */
 173 struct _pid {
 174         int setpoint;
 175         int32_t integral;
 176         int32_t p_gain;
 177         int32_t i_gain;
 178         int32_t d_gain;
 179         int deadband;
 180         int32_t last_err;
 181 };
 182
 183 /**
 184  * struct perf_limits - Store user and policy limits
 185  * @no_turbo:           User requested turbo state from intel_pstate sysfs
 186  * @turbo_disabled:     Platform turbo status either from msr
 187  *                      MSR_IA32_MISC_ENABLE or when maximum available pstate
 188  *                      matches the maximum turbo pstate
 189  * @max_perf_pct:       Effective maximum performance limit in percentage, this
 190  *                      is minimum of either limits enforced by cpufreq policy
 191  *                      or limits from user set limits via intel_pstate sysfs
 192  * @min_perf_pct:       Effective minimum performance limit in percentage, this
 193  *                      is maximum of either limits enforced by cpufreq policy
 194  *                      or limits from user set limits via intel_pstate sysfs
 195  * @max_perf:           This is a scaled value between 0 to 255 for max_perf_pct
 196  *                      This value is used to limit max pstate
 197  * @min_perf:           This is a scaled value between 0 to 255 for min_perf_pct
 198  *                      This value is used to limit min pstate
 199  * @max_policy_pct:     The maximum performance in percentage enforced by
 200  *                      cpufreq setpolicy interface
 201  * @max_sysfs_pct:      The maximum performance in percentage enforced by
 202  *                      intel pstate sysfs interface, unused when per cpu
 203  *                      controls are enforced
 204  * @min_policy_pct:     The minimum performance in percentage enforced by
 205  *                      cpufreq setpolicy interface
 206  * @min_sysfs_pct:      The minimum performance in percentage enforced by
 207  *                      intel pstate sysfs interface, unused when per cpu
 208  *                      controls are enforced
 209  *
 210  * Storage for user and policy defined limits.
 211  */
 212 struct perf_limits {
 213         int no_turbo;
 214         int turbo_disabled;
 215         int max_perf_pct;
 216         int min_perf_pct;
 217         int32_t max_perf;
 218         int32_t min_perf;
 219         int max_policy_pct;
 220         int max_sysfs_pct;
 221         int min_policy_pct;
 222         int min_sysfs_pct;
 223 };
 224
 225 /**
 226  * struct cpudata -     Per CPU instance data storage
 227  * @cpu:                CPU number for this instance data
 228  * @policy:             CPUFreq policy value
 229  * @update_util:        CPUFreq utility callback information
 230  * @update_util_set:    CPUFreq utility callback is set
 231  * @iowait_boost:       iowait-related boost fraction
 232  * @last_update:        Time of the last update.
 233  * @pstate:             Stores P state limits for this CPU
 234  * @vid:                Stores VID limits for this CPU
 235  * @pid:                Stores PID parameters for this CPU
 236  * @last_sample_time:   Last Sample time
 237  * @prev_aperf:         Last APERF value read from APERF MSR
 238  * @prev_mperf:         Last MPERF value read from MPERF MSR
 239  * @prev_tsc:           Last timestamp counter (TSC) value
 240  * @prev_cummulative_iowait: IO Wait time difference from last and
 241  *                      current sample
 242  * @sample:             Storage for storing last Sample data
 243  * @perf_limits:        Pointer to perf_limit unique to this CPU
 244  *                      Not all field in the structure are applicable
 245  *                      when per cpu controls are enforced
 246  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
 247  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
 248  * @epp_powersave:      Last saved HWP energy performance preference
 249  *                      (EPP) or energy performance bias (EPB),
 250  *                      when policy switched to performance
 251  * @epp_policy:         Last saved policy used to set EPP/EPB
 252  * @epp_default:        Power on default HWP energy performance
 253  *                      preference/bias
 254  * @epp_saved:          Saved EPP/EPB during system suspend or CPU offline
 255  *                      operation
 256  *
 257  * This structure stores per CPU instance data for all CPUs.
 258  */
 259 struct cpudata {
 260         int cpu;
 261
 262         unsigned int policy;
 263         struct update_util_data update_util;
 264         bool   update_util_set;
 265
 266         struct pstate_data pstate;
 267         struct vid_data vid;
 268         struct _pid pid;
 269
 270         u64     last_update;
 271         u64     last_sample_time;
 272         u64     prev_aperf;
 273         u64     prev_mperf;
 274         u64     prev_tsc;
 275         u64     prev_cummulative_iowait;
 276         struct sample sample;
 277         struct perf_limits *perf_limits;
 278 #ifdef CONFIG_ACPI
 279         struct acpi_processor_performance acpi_perf_data;
 280         bool valid_pss_table;
 281 #endif
 282         unsigned int iowait_boost;
 283         s16 epp_powersave;
 284         s16 epp_policy;
 285         s16 epp_default;
 286         s16 epp_saved;
 287 };
 288
 289 static struct cpudata **all_cpu_data;
 290
 291 /**
 292  * struct pstate_adjust_policy - Stores static PID configuration data
 293  * @sample_rate_ms:     PID calculation sample rate in ms
 294  * @sample_rate_ns:     Sample rate calculation in ns
 295  * @deadband:           PID deadband
 296  * @setpoint:           PID Setpoint
 297  * @p_gain_pct:         PID proportional gain
 298  * @i_gain_pct:         PID integral gain
 299  * @d_gain_pct:         PID derivative gain
 300  *
 301  * Stores per CPU model static PID configuration data.
 302  */
 303 struct pstate_adjust_policy {
 304         int sample_rate_ms;
 305         s64 sample_rate_ns;
 306         int deadband;
 307         int setpoint;
 308         int p_gain_pct;
 309         int d_gain_pct;
 310         int i_gain_pct;
 311 };
 312
 313 /**
 314  * struct pstate_funcs - Per CPU model specific callbacks
 315  * @get_max:            Callback to get maximum non turbo effective P state
 316  * @get_max_physical:   Callback to get maximum non turbo physical P state
 317  * @get_min:            Callback to get minimum P state
 318  * @get_turbo:          Callback to get turbo P state
 319  * @get_scaling:        Callback to get frequency scaling factor
 320  * @get_val:            Callback to convert P state to actual MSR write value
 321  * @get_vid:            Callback to get VID data for Atom platforms
 322  * @get_target_pstate:  Callback to a function to calculate next P state to use
 323  *
 324  * Core and Atom CPU models have different way to get P State limits. This
 325  * structure is used to store those callbacks.
 326  */
 327 struct pstate_funcs {
 328         int (*get_max)(void);
 329         int (*get_max_physical)(void);
 330         int (*get_min)(void);
 331         int (*get_turbo)(void);
 332         int (*get_scaling)(void);
 333         u64 (*get_val)(struct cpudata*, int pstate);
 334         void (*get_vid)(struct cpudata *);
 335         int32_t (*get_target_pstate)(struct cpudata *);
 336 };
 337
 338 /**
 339  * struct cpu_defaults- Per CPU model default config data
 340  * @pid_policy: PID config data
 341  * @funcs:              Callback function data
 342  */
 343 struct cpu_defaults {
 344         struct pstate_adjust_policy pid_policy;
 345         struct pstate_funcs funcs;
 346 };
 347
 348 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
 349 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
 350
 351 static struct pstate_adjust_policy pid_params __read_mostly;
 352 static struct pstate_funcs pstate_funcs __read_mostly;
 353 static int hwp_active __read_mostly;
 354 static bool per_cpu_limits __read_mostly;
 355
 356 static bool driver_registered __read_mostly;
 357
 358 #ifdef CONFIG_ACPI
 359 static bool acpi_ppc;
 360 #endif
 361
 362 static struct perf_limits performance_limits;
 363 static struct perf_limits powersave_limits;
 364 static struct perf_limits *limits;
 365
 366 static void intel_pstate_init_limits(struct perf_limits *limits)
 367 {
 368         memset(limits, 0, sizeof(*limits));
 369         limits->max_perf_pct = 100;
 370         limits->max_perf = int_ext_tofp(1);
 371         limits->max_policy_pct = 100;
 372         limits->max_sysfs_pct = 100;
 373 }
 374
 375 static void intel_pstate_set_performance_limits(struct perf_limits *limits)
 376 {
 377         intel_pstate_init_limits(limits);
 378         limits->min_perf_pct = 100;
 379         limits->min_perf = int_ext_tofp(1);
 380         limits->min_sysfs_pct = 100;
 381 }
 382
 383 static DEFINE_MUTEX(intel_pstate_driver_lock);
 384 static DEFINE_MUTEX(intel_pstate_limits_lock);
 385
 386 #ifdef CONFIG_ACPI
 387
 388 static bool intel_pstate_get_ppc_enable_status(void)
 389 {
 390         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
 391             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
 392                 return true;
 393
 394         return acpi_ppc;
 395 }
 396
 397 #ifdef CONFIG_ACPI_CPPC_LIB
 398
 399 /* The work item is needed to avoid CPU hotplug locking issues */
 400 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
 401 {
 402         sched_set_itmt_support();
 403 }
 404
 405 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
 406
 407 static void intel_pstate_set_itmt_prio(int cpu)
 408 {
 409         struct cppc_perf_caps cppc_perf;
 410         static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
 411         int ret;
 412
 413         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 414         if (ret)
 415                 return;
 416
 417         /*
 418          * The priorities can be set regardless of whether or not
 419          * sched_set_itmt_support(true) has been called and it is valid to
 420          * update them at any time after it has been called.
 421          */
 422         sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
 423
 424         if (max_highest_perf <= min_highest_perf) {
 425                 if (cppc_perf.highest_perf > max_highest_perf)
 426                         max_highest_perf = cppc_perf.highest_perf;
 427
 428                 if (cppc_perf.highest_perf < min_highest_perf)
 429                         min_highest_perf = cppc_perf.highest_perf;
 430
 431                 if (max_highest_perf > min_highest_perf) {
 432                         /*
 433                          * This code can be run during CPU online under the
 434                          * CPU hotplug locks, so sched_set_itmt_support()
 435                          * cannot be called from here.  Queue up a work item
 436                          * to invoke it.
 437                          */
 438                         schedule_work(&sched_itmt_work);
 439                 }
 440         }
 441 }
 442 #else
 443 static void intel_pstate_set_itmt_prio(int cpu)
 444 {
 445 }
 446 #endif
 447
 448 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 449 {
 450         struct cpudata *cpu;
 451         int ret;
 452         int i;
 453
 454         if (hwp_active) {
 455                 intel_pstate_set_itmt_prio(policy->cpu);
 456                 return;
 457         }
 458
 459         if (!intel_pstate_get_ppc_enable_status())
 460                 return;
 461
 462         cpu = all_cpu_data[policy->cpu];
 463
 464         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
 465                                                   policy->cpu);
 466         if (ret)
 467                 return;
 468
 469         /*
 470          * Check if the control value in _PSS is for PERF_CTL MSR, which should
 471          * guarantee that the states returned by it map to the states in our
 472          * list directly.
 473          */
 474         if (cpu->acpi_perf_data.control_register.space_id !=
 475                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
 476                 goto err;
 477
 478         /*
 479          * If there is only one entry _PSS, simply ignore _PSS and continue as
 480          * usual without taking _PSS into account
 481          */
 482         if (cpu->acpi_perf_data.state_count < 2)
 483                 goto err;
 484
 485         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
 486         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
 487                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
 488                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
 489                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
 490                          (u32) cpu->acpi_perf_data.states[i].power,
 491                          (u32) cpu->acpi_perf_data.states[i].control);
 492         }
 493
 494         /*
 495          * The _PSS table doesn't contain whole turbo frequency range.
 496          * This just contains +1 MHZ above the max non turbo frequency,
 497          * with control value corresponding to max turbo ratio. But
 498          * when cpufreq set policy is called, it will call with this
 499          * max frequency, which will cause a reduced performance as
 500          * this driver uses real max turbo frequency as the max
 501          * frequency. So correct this frequency in _PSS table to
 502          * correct max turbo frequency based on the turbo state.
 503          * Also need to convert to MHz as _PSS freq is in MHz.
 504          */
 505         if (!limits->turbo_disabled)
 506                 cpu->acpi_perf_data.states[0].core_frequency =
 507                                         policy->cpuinfo.max_freq / 1000;
 508         cpu->valid_pss_table = true;
 509         pr_debug("_PPC limits will be enforced\n");
 510
 511         return;
 512
 513  err:
 514         cpu->valid_pss_table = false;
 515         acpi_processor_unregister_performance(policy->cpu);
 516 }
 517
 518 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 519 {
 520         struct cpudata *cpu;
 521
 522         cpu = all_cpu_data[policy->cpu];
 523         if (!cpu->valid_pss_table)
 524                 return;
 525
 526         acpi_processor_unregister_performance(policy->cpu);
 527 }
 528 #else
 529 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 530 {
 531 }
 532
 533 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 534 {
 535 }
 536 #endif
 537
 538 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
 539                              int deadband, int integral) {
 540         pid->setpoint = int_tofp(setpoint);
 541         pid->deadband  = int_tofp(deadband);
 542         pid->integral  = int_tofp(integral);
 543         pid->last_err  = int_tofp(setpoint) - int_tofp(busy);
 544 }
 545
 546 static inline void pid_p_gain_set(struct _pid *pid, int percent)
 547 {
 548         pid->p_gain = div_fp(percent, 100);
 549 }
 550
 551 static inline void pid_i_gain_set(struct _pid *pid, int percent)
 552 {
 553         pid->i_gain = div_fp(percent, 100);
 554 }
 555
 556 static inline void pid_d_gain_set(struct _pid *pid, int percent)
 557 {
 558         pid->d_gain = div_fp(percent, 100);
 559 }
 560
 561 static signed int pid_calc(struct _pid *pid, int32_t busy)
 562 {
 563         signed int result;
 564         int32_t pterm, dterm, fp_error;
 565         int32_t integral_limit;
 566
 567         fp_error = pid->setpoint - busy;
 568
 569         if (abs(fp_error) <= pid->deadband)
 570                 return 0;
 571
 572         pterm = mul_fp(pid->p_gain, fp_error);
 573
 574         pid->integral += fp_error;
 575
 576         /*
 577          * We limit the integral here so that it will never
 578          * get higher than 30.  This prevents it from becoming
 579          * too large an input over long periods of time and allows
 580          * it to get factored out sooner.
 581          *
 582          * The value of 30 was chosen through experimentation.
 583          */
 584         integral_limit = int_tofp(30);
 585         if (pid->integral > integral_limit)
 586                 pid->integral = integral_limit;
 587         if (pid->integral < -integral_limit)
 588                 pid->integral = -integral_limit;
 589
 590         dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
 591         pid->last_err = fp_error;
 592
 593         result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
 594         result = result + (1 << (FRAC_BITS-1));
 595         return (signed int)fp_toint(result);
 596 }
 597
 598 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
 599 {
 600         pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
 601         pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
 602         pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
 603
 604         pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
 605 }
 606
 607 static inline void intel_pstate_reset_all_pid(void)
 608 {
 609         unsigned int cpu;
 610
 611         for_each_online_cpu(cpu) {
 612                 if (all_cpu_data[cpu])
 613                         intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
 614         }
 615 }
 616
 617 static inline void update_turbo_state(void)
 618 {
 619         u64 misc_en;
 620         struct cpudata *cpu;
 621
 622         cpu = all_cpu_data[0];
 623         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 624         limits->turbo_disabled =
 625                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
 626                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
 627 }
 628
 629 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
 630 {
 631         u64 epb;
 632         int ret;
 633
 634         if (!static_cpu_has(X86_FEATURE_EPB))
 635                 return -ENXIO;
 636
 637         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 638         if (ret)
 639                 return (s16)ret;
 640
 641         return (s16)(epb & 0x0f);
 642 }
 643
 644 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
 645 {
 646         s16 epp;
 647
 648         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 649                 /*
 650                  * When hwp_req_data is 0, means that caller didn't read
 651                  * MSR_HWP_REQUEST, so need to read and get EPP.
 652                  */
 653                 if (!hwp_req_data) {
 654                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
 655                                             &hwp_req_data);
 656                         if (epp)
 657                                 return epp;
 658                 }
 659                 epp = (hwp_req_data >> 24) & 0xff;
 660         } else {
 661                 /* When there is no EPP present, HWP uses EPB settings */
 662                 epp = intel_pstate_get_epb(cpu_data);
 663         }
 664
 665         return epp;
 666 }
 667
 668 static int intel_pstate_set_epb(int cpu, s16 pref)
 669 {
 670         u64 epb;
 671         int ret;
 672
 673         if (!static_cpu_has(X86_FEATURE_EPB))
 674                 return -ENXIO;
 675
 676         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 677         if (ret)
 678                 return ret;
 679
 680         epb = (epb & ~0x0f) | pref;
 681         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
 682
 683         return 0;
 684 }
 685
 686 /*
 687  * EPP/EPB display strings corresponding to EPP index in the
 688  * energy_perf_strings[]
 689  *      index           String
 690  *-------------------------------------
 691  *      0               default
 692  *      1               performance
 693  *      2               balance_performance
 694  *      3               balance_power
 695  *      4               power
 696  */
 697 static const char * const energy_perf_strings[] = {
 698         "default",
 699         "performance",
 700         "balance_performance",
 701         "balance_power",
 702         "power",
 703         NULL
 704 };
 705
 706 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
 707 {
 708         s16 epp;
 709         int index = -EINVAL;
 710
 711         epp = intel_pstate_get_epp(cpu_data, 0);
 712         if (epp < 0)
 713                 return epp;
 714
 715         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 716                 /*
 717                  * Range:
 718                  *      0x00-0x3F       :       Performance
 719                  *      0x40-0x7F       :       Balance performance
 720                  *      0x80-0xBF       :       Balance power
 721                  *      0xC0-0xFF       :       Power
 722                  * The EPP is a 8 bit value, but our ranges restrict the
 723                  * value which can be set. Here only using top two bits
 724                  * effectively.
 725                  */
 726                 index = (epp >> 6) + 1;
 727         } else if (static_cpu_has(X86_FEATURE_EPB)) {
 728                 /*
 729                  * Range:
 730                  *      0x00-0x03       :       Performance
 731                  *      0x04-0x07       :       Balance performance
 732                  *      0x08-0x0B       :       Balance power
 733                  *      0x0C-0x0F       :       Power
 734                  * The EPB is a 4 bit value, but our ranges restrict the
 735                  * value which can be set. Here only using top two bits
 736                  * effectively.
 737                  */
 738                 index = (epp >> 2) + 1;
 739         }
 740
 741         return index;
 742 }
 743
 744 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
 745                                               int pref_index)
 746 {
 747         int epp = -EINVAL;
 748         int ret;
 749
 750         if (!pref_index)
 751                 epp = cpu_data->epp_default;
 752
 753         mutex_lock(&intel_pstate_limits_lock);
 754
 755         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 756                 u64 value;
 757
 758                 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
 759                 if (ret)
 760                         goto return_pref;
 761
 762                 value &= ~GENMASK_ULL(31, 24);
 763
 764                 /*
 765                  * If epp is not default, convert from index into
 766                  * energy_perf_strings to epp value, by shifting 6
 767                  * bits left to use only top two bits in epp.
 768                  * The resultant epp need to shifted by 24 bits to
 769                  * epp position in MSR_HWP_REQUEST.
 770                  */
 771                 if (epp == -EINVAL)
 772                         epp = (pref_index - 1) << 6;
 773
 774                 value |= (u64)epp << 24;
 775                 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
 776         } else {
 777                 if (epp == -EINVAL)
 778                         epp = (pref_index - 1) << 2;
 779                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
 780         }
 781 return_pref:
 782         mutex_unlock(&intel_pstate_limits_lock);
 783
 784         return ret;
 785 }
 786
 787 static ssize_t show_energy_performance_available_preferences(
 788                                 struct cpufreq_policy *policy, char *buf)
 789 {
 790         int i = 0;
 791         int ret = 0;
 792
 793         while (energy_perf_strings[i] != NULL)
 794                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
 795
 796         ret += sprintf(&buf[ret], "\n");
 797
 798         return ret;
 799 }
 800
 801 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 802
 803 static ssize_t store_energy_performance_preference(
 804                 struct cpufreq_policy *policy, const char *buf, size_t count)
 805 {
 806         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 807         char str_preference[21];
 808         int ret, i = 0;
 809
 810         ret = sscanf(buf, "%20s", str_preference);
 811         if (ret != 1)
 812                 return -EINVAL;
 813
 814         while (energy_perf_strings[i] != NULL) {
 815                 if (!strcmp(str_preference, energy_perf_strings[i])) {
 816                         intel_pstate_set_energy_pref_index(cpu_data, i);
 817                         return count;
 818                 }
 819                 ++i;
 820         }
 821
 822         return -EINVAL;
 823 }
 824
 825 static ssize_t show_energy_performance_preference(
 826                                 struct cpufreq_policy *policy, char *buf)
 827 {
 828         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 829         int preference;
 830
 831         preference = intel_pstate_get_energy_pref_index(cpu_data);
 832         if (preference < 0)
 833                 return preference;
 834
 835         return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
 836 }
 837
 838 cpufreq_freq_attr_rw(energy_performance_preference);
 839
 840 static struct freq_attr *hwp_cpufreq_attrs[] = {
 841         &energy_performance_preference,
 842         &energy_performance_available_preferences,
 843         NULL,
 844 };
 845
 846 static void intel_pstate_hwp_set(struct cpufreq_policy *policy)
 847 {
 848         int min, hw_min, max, hw_max, cpu;
 849         struct perf_limits *perf_limits = limits;
 850         u64 value, cap;
 851
 852         for_each_cpu(cpu, policy->cpus) {
 853                 int max_perf_pct, min_perf_pct;
 854                 struct cpudata *cpu_data = all_cpu_data[cpu];
 855                 s16 epp;
 856
 857                 if (per_cpu_limits)
 858                         perf_limits = all_cpu_data[cpu]->perf_limits;
 859
 860                 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
 861                 hw_min = HWP_LOWEST_PERF(cap);
 862                 if (limits->no_turbo)
 863                         hw_max = HWP_GUARANTEED_PERF(cap);
 864                 else
 865                         hw_max = HWP_HIGHEST_PERF(cap);
 866
 867                 max_perf_pct = perf_limits->max_perf_pct;
 868                 min_perf_pct = perf_limits->min_perf_pct;
 869                 min = hw_max * min_perf_pct / 100;
 870
 871                 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 872
 873                 value &= ~HWP_MIN_PERF(~0L);
 874                 value |= HWP_MIN_PERF(min);
 875
 876                 max = hw_max * max_perf_pct / 100;
 877                 value &= ~HWP_MAX_PERF(~0L);
 878                 value |= HWP_MAX_PERF(max);
 879
 880                 if (cpu_data->epp_policy == cpu_data->policy)
 881                         goto skip_epp;
 882
 883                 cpu_data->epp_policy = cpu_data->policy;
 884
 885                 if (cpu_data->epp_saved >= 0) {
 886                         epp = cpu_data->epp_saved;
 887                         cpu_data->epp_saved = -EINVAL;
 888                         goto update_epp;
 889                 }
 890
 891                 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
 892                         epp = intel_pstate_get_epp(cpu_data, value);
 893                         cpu_data->epp_powersave = epp;
 894                         /* If EPP read was failed, then don't try to write */
 895                         if (epp < 0)
 896                                 goto skip_epp;
 897
 898
 899                         epp = 0;
 900                 } else {
 901                         /* skip setting EPP, when saved value is invalid */
 902                         if (cpu_data->epp_powersave < 0)
 903                                 goto skip_epp;
 904
 905                         /*
 906                          * No need to restore EPP when it is not zero. This
 907                          * means:
 908                          *  - Policy is not changed
 909                          *  - user has manually changed
 910                          *  - Error reading EPB
 911                          */
 912                         epp = intel_pstate_get_epp(cpu_data, value);
 913                         if (epp)
 914                                 goto skip_epp;
 915
 916                         epp = cpu_data->epp_powersave;
 917                 }
 918 update_epp:
 919                 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 920                         value &= ~GENMASK_ULL(31, 24);
 921                         value |= (u64)epp << 24;
 922                 } else {
 923                         intel_pstate_set_epb(cpu, epp);
 924                 }
 925 skip_epp:
 926                 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 927         }
 928 }
 929
 930 static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy)
 931 {
 932         if (hwp_active)
 933                 intel_pstate_hwp_set(policy);
 934
 935         return 0;
 936 }
 937
 938 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
 939 {
 940         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 941
 942         if (!hwp_active)
 943                 return 0;
 944
 945         cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
 946
 947         return 0;
 948 }
 949
 950 static int intel_pstate_resume(struct cpufreq_policy *policy)
 951 {
 952         int ret;
 953
 954         if (!hwp_active)
 955                 return 0;
 956
 957         mutex_lock(&intel_pstate_limits_lock);
 958
 959         all_cpu_data[policy->cpu]->epp_policy = 0;
 960
 961         ret = intel_pstate_hwp_set_policy(policy);
 962
 963         mutex_unlock(&intel_pstate_limits_lock);
 964
 965         return ret;
 966 }
 967
 968 static void intel_pstate_update_policies(void)
 969         __releases(&intel_pstate_limits_lock)
 970         __acquires(&intel_pstate_limits_lock)
 971 {
 972         struct perf_limits *saved_limits = limits;
 973         int cpu;
 974
 975         mutex_unlock(&intel_pstate_limits_lock);
 976
 977         for_each_possible_cpu(cpu)
 978                 cpufreq_update_policy(cpu);
 979
 980         mutex_lock(&intel_pstate_limits_lock);
 981
 982         limits = saved_limits;
 983 }
 984
 985 /************************** debugfs begin ************************/
 986 static int pid_param_set(void *data, u64 val)
 987 {
 988         *(u32 *)data = val;
 989         pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
 990         intel_pstate_reset_all_pid();
 991         return 0;
 992 }
 993
 994 static int pid_param_get(void *data, u64 *val)
 995 {
 996         *val = *(u32 *)data;
 997         return 0;
 998 }
 999 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
1000
1001 static struct dentry *debugfs_parent;
1002
1003 struct pid_param {
1004         char *name;
1005         void *value;
1006         struct dentry *dentry;
1007 };
1008
1009 static struct pid_param pid_files[] = {
1010         {"sample_rate_ms", &pid_params.sample_rate_ms, },
1011         {"d_gain_pct", &pid_params.d_gain_pct, },
1012         {"i_gain_pct", &pid_params.i_gain_pct, },
1013         {"deadband", &pid_params.deadband, },
1014         {"setpoint", &pid_params.setpoint, },
1015         {"p_gain_pct", &pid_params.p_gain_pct, },
1016         {NULL, NULL, }
1017 };
1018
1019 static void intel_pstate_debug_expose_params(void)
1020 {
1021         int i;
1022
1023         debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
1024         if (IS_ERR_OR_NULL(debugfs_parent))
1025                 return;
1026
1027         for (i = 0; pid_files[i].name; i++) {
1028                 struct dentry *dentry;
1029
1030                 dentry = debugfs_create_file(pid_files[i].name, 0660,
1031                                              debugfs_parent, pid_files[i].value,
1032                                              &fops_pid_param);
1033                 if (!IS_ERR(dentry))
1034                         pid_files[i].dentry = dentry;
1035         }
1036 }
1037
1038 static void intel_pstate_debug_hide_params(void)
1039 {
1040         int i;
1041
1042         if (IS_ERR_OR_NULL(debugfs_parent))
1043                 return;
1044
1045         for (i = 0; pid_files[i].name; i++) {
1046                 debugfs_remove(pid_files[i].dentry);
1047                 pid_files[i].dentry = NULL;
1048         }
1049
1050         debugfs_remove(debugfs_parent);
1051         debugfs_parent = NULL;
1052 }
1053
1054 /************************** debugfs end ************************/
1055
1056 /************************** sysfs begin ************************/
1057 #define show_one(file_name, object)                                     \
1058         static ssize_t show_##file_name                                 \
1059         (struct kobject *kobj, struct attribute *attr, char *buf)       \
1060         {                                                               \
1061                 return sprintf(buf, "%u\n", limits->object);            \
1062         }
1063
1064 static ssize_t intel_pstate_show_status(char *buf);
1065 static int intel_pstate_update_status(const char *buf, size_t size);
1066
1067 static ssize_t show_status(struct kobject *kobj,
1068                            struct attribute *attr, char *buf)
1069 {
1070         ssize_t ret;
1071
1072         mutex_lock(&intel_pstate_driver_lock);
1073         ret = intel_pstate_show_status(buf);
1074         mutex_unlock(&intel_pstate_driver_lock);
1075
1076         return ret;
1077 }
1078
1079 static ssize_t store_status(struct kobject *a, struct attribute *b,
1080                             const char *buf, size_t count)
1081 {
1082         char *p = memchr(buf, '\n', count);
1083         int ret;
1084
1085         mutex_lock(&intel_pstate_driver_lock);
1086         ret = intel_pstate_update_status(buf, p ? p - buf : count);
1087         mutex_unlock(&intel_pstate_driver_lock);
1088
1089         return ret < 0 ? ret : count;
1090 }
1091
1092 static ssize_t show_turbo_pct(struct kobject *kobj,
1093                                 struct attribute *attr, char *buf)
1094 {
1095         struct cpudata *cpu;
1096         int total, no_turbo, turbo_pct;
1097         uint32_t turbo_fp;
1098
1099         mutex_lock(&intel_pstate_driver_lock);
1100
1101         if (!driver_registered) {
1102                 mutex_unlock(&intel_pstate_driver_lock);
1103                 return -EAGAIN;
1104         }
1105
1106         cpu = all_cpu_data[0];
1107
1108         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1109         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1110         turbo_fp = div_fp(no_turbo, total);
1111         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1112
1113         mutex_unlock(&intel_pstate_driver_lock);
1114
1115         return sprintf(buf, "%u\n", turbo_pct);
1116 }
1117
1118 static ssize_t show_num_pstates(struct kobject *kobj,
1119                                 struct attribute *attr, char *buf)
1120 {
1121         struct cpudata *cpu;
1122         int total;
1123
1124         mutex_lock(&intel_pstate_driver_lock);
1125
1126         if (!driver_registered) {
1127                 mutex_unlock(&intel_pstate_driver_lock);
1128                 return -EAGAIN;
1129         }
1130
1131         cpu = all_cpu_data[0];
1132         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1133
1134         mutex_unlock(&intel_pstate_driver_lock);
1135
1136         return sprintf(buf, "%u\n", total);
1137 }
1138
1139 static ssize_t show_no_turbo(struct kobject *kobj,
1140                              struct attribute *attr, char *buf)
1141 {
1142         ssize_t ret;
1143
1144         mutex_lock(&intel_pstate_driver_lock);
1145
1146         if (!driver_registered) {
1147                 mutex_unlock(&intel_pstate_driver_lock);
1148                 return -EAGAIN;
1149         }
1150
1151         update_turbo_state();
1152         if (limits->turbo_disabled)
1153                 ret = sprintf(buf, "%u\n", limits->turbo_disabled);
1154         else
1155                 ret = sprintf(buf, "%u\n", limits->no_turbo);
1156
1157         mutex_unlock(&intel_pstate_driver_lock);
1158
1159         return ret;
1160 }
1161
1162 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
1163                               const char *buf, size_t count)
1164 {
1165         unsigned int input;
1166         int ret;
1167
1168         ret = sscanf(buf, "%u", &input);
1169         if (ret != 1)
1170                 return -EINVAL;
1171
1172         mutex_lock(&intel_pstate_driver_lock);
1173
1174         if (!driver_registered) {
1175                 mutex_unlock(&intel_pstate_driver_lock);
1176                 return -EAGAIN;
1177         }
1178
1179         mutex_lock(&intel_pstate_limits_lock);
1180
1181         update_turbo_state();
1182         if (limits->turbo_disabled) {
1183                 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1184                 mutex_unlock(&intel_pstate_limits_lock);
1185                 mutex_unlock(&intel_pstate_driver_lock);
1186                 return -EPERM;
1187         }
1188
1189         limits->no_turbo = clamp_t(int, input, 0, 1);
1190
1191         intel_pstate_update_policies();
1192
1193         mutex_unlock(&intel_pstate_limits_lock);
1194
1195         mutex_unlock(&intel_pstate_driver_lock);
1196
1197         return count;
1198 }
1199
1200 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
1201                                   const char *buf, size_t count)
1202 {
1203         unsigned int input;
1204         int ret;
1205
1206         ret = sscanf(buf, "%u", &input);
1207         if (ret != 1)
1208                 return -EINVAL;
1209
1210         mutex_lock(&intel_pstate_driver_lock);
1211
1212         if (!driver_registered) {
1213                 mutex_unlock(&intel_pstate_driver_lock);
1214                 return -EAGAIN;
1215         }
1216
1217         mutex_lock(&intel_pstate_limits_lock);
1218
1219         limits->max_sysfs_pct = clamp_t(int, input, 0 , 100);
1220         limits->max_perf_pct = min(limits->max_policy_pct,
1221                                    limits->max_sysfs_pct);
1222         limits->max_perf_pct = max(limits->min_policy_pct,
1223                                    limits->max_perf_pct);
1224         limits->max_perf_pct = max(limits->min_perf_pct,
1225                                    limits->max_perf_pct);
1226         limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
1227
1228         intel_pstate_update_policies();
1229
1230         mutex_unlock(&intel_pstate_limits_lock);
1231
1232         mutex_unlock(&intel_pstate_driver_lock);
1233
1234         return count;
1235 }
1236
1237 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1238                                   const char *buf, size_t count)
1239 {
1240         unsigned int input;
1241         int ret;
1242
1243         ret = sscanf(buf, "%u", &input);
1244         if (ret != 1)
1245                 return -EINVAL;
1246
1247         mutex_lock(&intel_pstate_driver_lock);
1248
1249         if (!driver_registered) {
1250                 mutex_unlock(&intel_pstate_driver_lock);
1251                 return -EAGAIN;
1252         }
1253
1254         mutex_lock(&intel_pstate_limits_lock);
1255
1256         limits->min_sysfs_pct = clamp_t(int, input, 0 , 100);
1257         limits->min_perf_pct = max(limits->min_policy_pct,
1258                                    limits->min_sysfs_pct);
1259         limits->min_perf_pct = min(limits->max_policy_pct,
1260                                    limits->min_perf_pct);
1261         limits->min_perf_pct = min(limits->max_perf_pct,
1262                                    limits->min_perf_pct);
1263         limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
1264
1265         intel_pstate_update_policies();
1266
1267         mutex_unlock(&intel_pstate_limits_lock);
1268
1269         mutex_unlock(&intel_pstate_driver_lock);
1270
1271         return count;
1272 }
1273
1274 show_one(max_perf_pct, max_perf_pct);
1275 show_one(min_perf_pct, min_perf_pct);
1276
1277 define_one_global_rw(status);
1278 define_one_global_rw(no_turbo);
1279 define_one_global_rw(max_perf_pct);
1280 define_one_global_rw(min_perf_pct);
1281 define_one_global_ro(turbo_pct);
1282 define_one_global_ro(num_pstates);
1283
1284 static struct attribute *intel_pstate_attributes[] = {
1285         &status.attr,
1286         &no_turbo.attr,
1287         &turbo_pct.attr,
1288         &num_pstates.attr,
1289         NULL
1290 };
1291
1292 static struct attribute_group intel_pstate_attr_group = {
1293         .attrs = intel_pstate_attributes,
1294 };
1295
1296 static void __init intel_pstate_sysfs_expose_params(void)
1297 {
1298         struct kobject *intel_pstate_kobject;
1299         int rc;
1300
1301         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1302                                                 &cpu_subsys.dev_root->kobj);
1303         if (WARN_ON(!intel_pstate_kobject))
1304                 return;
1305
1306         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1307         if (WARN_ON(rc))
1308                 return;
1309
1310         /*
1311          * If per cpu limits are enforced there are no global limits, so
1312          * return without creating max/min_perf_pct attributes
1313          */
1314         if (per_cpu_limits)
1315                 return;
1316
1317         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1318         WARN_ON(rc);
1319
1320         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1321         WARN_ON(rc);
1322
1323 }
1324 /************************** sysfs end ************************/
1325
1326 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1327 {
1328         /* First disable HWP notification interrupt as we don't process them */
1329         if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1330                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1331
1332         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1333         cpudata->epp_policy = 0;
1334         if (cpudata->epp_default == -EINVAL)
1335                 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1336 }
1337
1338 #define MSR_IA32_POWER_CTL_BIT_EE       19
1339
1340 /* Disable energy efficiency optimization */
1341 static void intel_pstate_disable_ee(int cpu)
1342 {
1343         u64 power_ctl;
1344         int ret;
1345
1346         ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1347         if (ret)
1348                 return;
1349
1350         if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1351                 pr_info("Disabling energy efficiency optimization\n");
1352                 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1353                 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1354         }
1355 }
1356
1357 static int atom_get_min_pstate(void)
1358 {
1359         u64 value;
1360
1361         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1362         return (value >> 8) & 0x7F;
1363 }
1364
1365 static int atom_get_max_pstate(void)
1366 {
1367         u64 value;
1368
1369         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1370         return (value >> 16) & 0x7F;
1371 }
1372
1373 static int atom_get_turbo_pstate(void)
1374 {
1375         u64 value;
1376
1377         rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1378         return value & 0x7F;
1379 }
1380
1381 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1382 {
1383         u64 val;
1384         int32_t vid_fp;
1385         u32 vid;
1386
1387         val = (u64)pstate << 8;
1388         if (limits->no_turbo && !limits->turbo_disabled)
1389                 val |= (u64)1 << 32;
1390
1391         vid_fp = cpudata->vid.min + mul_fp(
1392                 int_tofp(pstate - cpudata->pstate.min_pstate),
1393                 cpudata->vid.ratio);
1394
1395         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1396         vid = ceiling_fp(vid_fp);
1397
1398         if (pstate > cpudata->pstate.max_pstate)
1399                 vid = cpudata->vid.turbo;
1400
1401         return val | vid;
1402 }
1403
1404 static int silvermont_get_scaling(void)
1405 {
1406         u64 value;
1407         int i;
1408         /* Defined in Table 35-6 from SDM (Sept 2015) */
1409         static int silvermont_freq_table[] = {
1410                 83300, 100000, 133300, 116700, 80000};
1411
1412         rdmsrl(MSR_FSB_FREQ, value);
1413         i = value & 0x7;
1414         WARN_ON(i > 4);
1415
1416         return silvermont_freq_table[i];
1417 }
1418
1419 static int airmont_get_scaling(void)
1420 {
1421         u64 value;
1422         int i;
1423         /* Defined in Table 35-10 from SDM (Sept 2015) */
1424         static int airmont_freq_table[] = {
1425                 83300, 100000, 133300, 116700, 80000,
1426                 93300, 90000, 88900, 87500};
1427
1428         rdmsrl(MSR_FSB_FREQ, value);
1429         i = value & 0xF;
1430         WARN_ON(i > 8);
1431
1432         return airmont_freq_table[i];
1433 }
1434
1435 static void atom_get_vid(struct cpudata *cpudata)
1436 {
1437         u64 value;
1438
1439         rdmsrl(MSR_ATOM_CORE_VIDS, value);
1440         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1441         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1442         cpudata->vid.ratio = div_fp(
1443                 cpudata->vid.max - cpudata->vid.min,
1444                 int_tofp(cpudata->pstate.max_pstate -
1445                         cpudata->pstate.min_pstate));
1446
1447         rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1448         cpudata->vid.turbo = value & 0x7f;
1449 }
1450
1451 static int core_get_min_pstate(void)
1452 {
1453         u64 value;
1454
1455         rdmsrl(MSR_PLATFORM_INFO, value);
1456         return (value >> 40) & 0xFF;
1457 }
1458
1459 static int core_get_max_pstate_physical(void)
1460 {
1461         u64 value;
1462
1463         rdmsrl(MSR_PLATFORM_INFO, value);
1464         return (value >> 8) & 0xFF;
1465 }
1466
1467 static int core_get_tdp_ratio(u64 plat_info)
1468 {
1469         /* Check how many TDP levels present */
1470         if (plat_info & 0x600000000) {
1471                 u64 tdp_ctrl;
1472                 u64 tdp_ratio;
1473                 int tdp_msr;
1474                 int err;
1475
1476                 /* Get the TDP level (0, 1, 2) to get ratios */
1477                 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1478                 if (err)
1479                         return err;
1480
1481                 /* TDP MSR are continuous starting at 0x648 */
1482                 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1483                 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1484                 if (err)
1485                         return err;
1486
1487                 /* For level 1 and 2, bits[23:16] contain the ratio */
1488                 if (tdp_ctrl & 0x03)
1489                         tdp_ratio >>= 16;
1490
1491                 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1492                 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1493
1494                 return (int)tdp_ratio;
1495         }
1496
1497         return -ENXIO;
1498 }
1499
1500 static int core_get_max_pstate(void)
1501 {
1502         u64 tar;
1503         u64 plat_info;
1504         int max_pstate;
1505         int tdp_ratio;
1506         int err;
1507
1508         rdmsrl(MSR_PLATFORM_INFO, plat_info);
1509         max_pstate = (plat_info >> 8) & 0xFF;
1510
1511         tdp_ratio = core_get_tdp_ratio(plat_info);
1512         if (tdp_ratio <= 0)
1513                 return max_pstate;
1514
1515         if (hwp_active) {
1516                 /* Turbo activation ratio is not used on HWP platforms */
1517                 return tdp_ratio;
1518         }
1519
1520         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1521         if (!err) {
1522                 int tar_levels;
1523
1524                 /* Do some sanity checking for safety */
1525                 tar_levels = tar & 0xff;
1526                 if (tdp_ratio - 1 == tar_levels) {
1527                         max_pstate = tar_levels;
1528                         pr_debug("max_pstate=TAC %x\n", max_pstate);
1529                 }
1530         }
1531
1532         return max_pstate;
1533 }
1534
1535 static int core_get_turbo_pstate(void)
1536 {
1537         u64 value;
1538         int nont, ret;
1539
1540         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1541         nont = core_get_max_pstate();
1542         ret = (value) & 255;
1543         if (ret <= nont)
1544                 ret = nont;
1545         return ret;
1546 }
1547
1548 static inline int core_get_scaling(void)
1549 {
1550         return 100000;
1551 }
1552
1553 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1554 {
1555         u64 val;
1556
1557         val = (u64)pstate << 8;
1558         if (limits->no_turbo && !limits->turbo_disabled)
1559                 val |= (u64)1 << 32;
1560
1561         return val;
1562 }
1563
1564 static int knl_get_turbo_pstate(void)
1565 {
1566         u64 value;
1567         int nont, ret;
1568
1569         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1570         nont = core_get_max_pstate();
1571         ret = (((value) >> 8) & 0xFF);
1572         if (ret <= nont)
1573                 ret = nont;
1574         return ret;
1575 }
1576
1577 static struct cpu_defaults core_params = {
1578         .pid_policy = {
1579                 .sample_rate_ms = 10,
1580                 .deadband = 0,
1581                 .setpoint = 97,
1582                 .p_gain_pct = 20,
1583                 .d_gain_pct = 0,
1584                 .i_gain_pct = 0,
1585         },
1586         .funcs = {
1587                 .get_max = core_get_max_pstate,
1588                 .get_max_physical = core_get_max_pstate_physical,
1589                 .get_min = core_get_min_pstate,
1590                 .get_turbo = core_get_turbo_pstate,
1591                 .get_scaling = core_get_scaling,
1592                 .get_val = core_get_val,
1593                 .get_target_pstate = get_target_pstate_use_performance,
1594         },
1595 };
1596
1597 static const struct cpu_defaults silvermont_params = {
1598         .pid_policy = {
1599                 .sample_rate_ms = 10,
1600                 .deadband = 0,
1601                 .setpoint = 60,
1602                 .p_gain_pct = 14,
1603                 .d_gain_pct = 0,
1604                 .i_gain_pct = 4,
1605         },
1606         .funcs = {
1607                 .get_max = atom_get_max_pstate,
1608                 .get_max_physical = atom_get_max_pstate,
1609                 .get_min = atom_get_min_pstate,
1610                 .get_turbo = atom_get_turbo_pstate,
1611                 .get_val = atom_get_val,
1612                 .get_scaling = silvermont_get_scaling,
1613                 .get_vid = atom_get_vid,
1614                 .get_target_pstate = get_target_pstate_use_cpu_load,
1615         },
1616 };
1617
1618 static const struct cpu_defaults airmont_params = {
1619         .pid_policy = {
1620                 .sample_rate_ms = 10,
1621                 .deadband = 0,
1622                 .setpoint = 60,
1623                 .p_gain_pct = 14,
1624                 .d_gain_pct = 0,
1625                 .i_gain_pct = 4,
1626         },
1627         .funcs = {
1628                 .get_max = atom_get_max_pstate,
1629                 .get_max_physical = atom_get_max_pstate,
1630                 .get_min = atom_get_min_pstate,
1631                 .get_turbo = atom_get_turbo_pstate,
1632                 .get_val = atom_get_val,
1633                 .get_scaling = airmont_get_scaling,
1634                 .get_vid = atom_get_vid,
1635                 .get_target_pstate = get_target_pstate_use_cpu_load,
1636         },
1637 };
1638
1639 static const struct cpu_defaults knl_params = {
1640         .pid_policy = {
1641                 .sample_rate_ms = 10,
1642                 .deadband = 0,
1643                 .setpoint = 97,
1644                 .p_gain_pct = 20,
1645                 .d_gain_pct = 0,
1646                 .i_gain_pct = 0,
1647         },
1648         .funcs = {
1649                 .get_max = core_get_max_pstate,
1650                 .get_max_physical = core_get_max_pstate_physical,
1651                 .get_min = core_get_min_pstate,
1652                 .get_turbo = knl_get_turbo_pstate,
1653                 .get_scaling = core_get_scaling,
1654                 .get_val = core_get_val,
1655                 .get_target_pstate = get_target_pstate_use_performance,
1656         },
1657 };
1658
1659 static const struct cpu_defaults bxt_params = {
1660         .pid_policy = {
1661                 .sample_rate_ms = 10,
1662                 .deadband = 0,
1663                 .setpoint = 60,
1664                 .p_gain_pct = 14,
1665                 .d_gain_pct = 0,
1666                 .i_gain_pct = 4,
1667         },
1668         .funcs = {
1669                 .get_max = core_get_max_pstate,
1670                 .get_max_physical = core_get_max_pstate_physical,
1671                 .get_min = core_get_min_pstate,
1672                 .get_turbo = core_get_turbo_pstate,
1673                 .get_scaling = core_get_scaling,
1674                 .get_val = core_get_val,
1675                 .get_target_pstate = get_target_pstate_use_cpu_load,
1676         },
1677 };
1678
1679 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
1680 {
1681         int max_perf = cpu->pstate.turbo_pstate;
1682         int max_perf_adj;
1683         int min_perf;
1684         struct perf_limits *perf_limits = limits;
1685
1686         if (limits->no_turbo || limits->turbo_disabled)
1687                 max_perf = cpu->pstate.max_pstate;
1688
1689         if (per_cpu_limits)
1690                 perf_limits = cpu->perf_limits;
1691
1692         /*
1693          * performance can be limited by user through sysfs, by cpufreq
1694          * policy, or by cpu specific default values determined through
1695          * experimentation.
1696          */
1697         max_perf_adj = fp_ext_toint(max_perf * perf_limits->max_perf);
1698         *max = clamp_t(int, max_perf_adj,
1699                         cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
1700
1701         min_perf = fp_ext_toint(max_perf * perf_limits->min_perf);
1702         *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
1703 }
1704
1705 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1706 {
1707         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1708         cpu->pstate.current_pstate = pstate;
1709         /*
1710          * Generally, there is no guarantee that this code will always run on
1711          * the CPU being updated, so force the register update to run on the
1712          * right CPU.
1713          */
1714         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1715                       pstate_funcs.get_val(cpu, pstate));
1716 }
1717
1718 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1719 {
1720         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1721 }
1722
1723 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1724 {
1725         int min_pstate, max_pstate;
1726
1727         update_turbo_state();
1728         intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate);
1729         intel_pstate_set_pstate(cpu, max_pstate);
1730 }
1731
1732 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1733 {
1734         cpu->pstate.min_pstate = pstate_funcs.get_min();
1735         cpu->pstate.max_pstate = pstate_funcs.get_max();
1736         cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1737         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1738         cpu->pstate.scaling = pstate_funcs.get_scaling();
1739         cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1740         cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1741
1742         if (pstate_funcs.get_vid)
1743                 pstate_funcs.get_vid(cpu);
1744
1745         intel_pstate_set_min_pstate(cpu);
1746 }
1747
1748 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1749 {
1750         struct sample *sample = &cpu->sample;
1751
1752         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1753 }
1754
1755 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1756 {
1757         u64 aperf, mperf;
1758         unsigned long flags;
1759         u64 tsc;
1760
1761         local_irq_save(flags);
1762         rdmsrl(MSR_IA32_APERF, aperf);
1763         rdmsrl(MSR_IA32_MPERF, mperf);
1764         tsc = rdtsc();
1765         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1766                 local_irq_restore(flags);
1767                 return false;
1768         }
1769         local_irq_restore(flags);
1770
1771         cpu->last_sample_time = cpu->sample.time;
1772         cpu->sample.time = time;
1773         cpu->sample.aperf = aperf;
1774         cpu->sample.mperf = mperf;
1775         cpu->sample.tsc =  tsc;
1776         cpu->sample.aperf -= cpu->prev_aperf;
1777         cpu->sample.mperf -= cpu->prev_mperf;
1778         cpu->sample.tsc -= cpu->prev_tsc;
1779
1780         cpu->prev_aperf = aperf;
1781         cpu->prev_mperf = mperf;
1782         cpu->prev_tsc = tsc;
1783         /*
1784          * First time this function is invoked in a given cycle, all of the
1785          * previous sample data fields are equal to zero or stale and they must
1786          * be populated with meaningful numbers for things to work, so assume
1787          * that sample.time will always be reset before setting the utilization
1788          * update hook and make the caller skip the sample then.
1789          */
1790         return !!cpu->last_sample_time;
1791 }
1792
1793 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1794 {
1795         return mul_ext_fp(cpu->sample.core_avg_perf,
1796                           cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1797 }
1798
1799 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1800 {
1801         return mul_ext_fp(cpu->pstate.max_pstate_physical,
1802                           cpu->sample.core_avg_perf);
1803 }
1804
1805 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1806 {
1807         struct sample *sample = &cpu->sample;
1808         int32_t busy_frac, boost;
1809         int target, avg_pstate;
1810
1811         busy_frac = div_fp(sample->mperf, sample->tsc);
1812
1813         boost = cpu->iowait_boost;
1814         cpu->iowait_boost >>= 1;
1815
1816         if (busy_frac < boost)
1817                 busy_frac = boost;
1818
1819         sample->busy_scaled = busy_frac * 100;
1820
1821         target = limits->no_turbo || limits->turbo_disabled ?
1822                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1823         target += target >> 2;
1824         target = mul_fp(target, busy_frac);
1825         if (target < cpu->pstate.min_pstate)
1826                 target = cpu->pstate.min_pstate;
1827
1828         /*
1829          * If the average P-state during the previous cycle was higher than the
1830          * current target, add 50% of the difference to the target to reduce
1831          * possible performance oscillations and offset possible performance
1832          * loss related to moving the workload from one CPU to another within
1833          * a package/module.
1834          */
1835         avg_pstate = get_avg_pstate(cpu);
1836         if (avg_pstate > target)
1837                 target += (avg_pstate - target) >> 1;
1838
1839         return target;
1840 }
1841
1842 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1843 {
1844         int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1845         u64 duration_ns;
1846
1847         /*
1848          * perf_scaled is the ratio of the average P-state during the last
1849          * sampling period to the P-state requested last time (in percent).
1850          *
1851          * That measures the system's response to the previous P-state
1852          * selection.
1853          */
1854         max_pstate = cpu->pstate.max_pstate_physical;
1855         current_pstate = cpu->pstate.current_pstate;
1856         perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1857                                div_fp(100 * max_pstate, current_pstate));
1858
1859         /*
1860          * Since our utilization update callback will not run unless we are
1861          * in C0, check if the actual elapsed time is significantly greater (3x)
1862          * than our sample interval.  If it is, then we were idle for a long
1863          * enough period of time to adjust our performance metric.
1864          */
1865         duration_ns = cpu->sample.time - cpu->last_sample_time;
1866         if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1867                 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1868                 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1869         } else {
1870                 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1871                 if (sample_ratio < int_tofp(1))
1872                         perf_scaled = 0;
1873         }
1874
1875         cpu->sample.busy_scaled = perf_scaled;
1876         return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1877 }
1878
1879 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1880 {
1881         int max_perf, min_perf;
1882
1883         intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1884         pstate = clamp_t(int, pstate, min_perf, max_perf);
1885         return pstate;
1886 }
1887
1888 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1889 {
1890         if (pstate == cpu->pstate.current_pstate)
1891                 return;
1892
1893         cpu->pstate.current_pstate = pstate;
1894         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1895 }
1896
1897 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1898 {
1899         int from, target_pstate;
1900         struct sample *sample;
1901
1902         from = cpu->pstate.current_pstate;
1903
1904         target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ?
1905                 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu);
1906
1907         update_turbo_state();
1908
1909         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1910         trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1911         intel_pstate_update_pstate(cpu, target_pstate);
1912
1913         sample = &cpu->sample;
1914         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1915                 fp_toint(sample->busy_scaled),
1916                 from,
1917                 cpu->pstate.current_pstate,
1918                 sample->mperf,
1919                 sample->aperf,
1920                 sample->tsc,
1921                 get_avg_frequency(cpu),
1922                 fp_toint(cpu->iowait_boost * 100));
1923 }
1924
1925 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1926                                      unsigned int flags)
1927 {
1928         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1929         u64 delta_ns;
1930
1931         if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) {
1932                 if (flags & SCHED_CPUFREQ_IOWAIT) {
1933                         cpu->iowait_boost = int_tofp(1);
1934                 } else if (cpu->iowait_boost) {
1935                         /* Clear iowait_boost if the CPU may have been idle. */
1936                         delta_ns = time - cpu->last_update;
1937                         if (delta_ns > TICK_NSEC)
1938                                 cpu->iowait_boost = 0;
1939                 }
1940                 cpu->last_update = time;
1941         }
1942
1943         delta_ns = time - cpu->sample.time;
1944         if ((s64)delta_ns >= pid_params.sample_rate_ns) {
1945                 bool sample_taken = intel_pstate_sample(cpu, time);
1946
1947                 if (sample_taken) {
1948                         intel_pstate_calc_avg_perf(cpu);
1949                         if (!hwp_active)
1950                                 intel_pstate_adjust_busy_pstate(cpu);
1951                 }
1952         }
1953 }
1954
1955 #define ICPU(model, policy) \
1956         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1957                         (unsigned long)&policy }
1958
1959 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1960         ICPU(INTEL_FAM6_SANDYBRIDGE,            core_params),
1961         ICPU(INTEL_FAM6_SANDYBRIDGE_X,          core_params),
1962         ICPU(INTEL_FAM6_ATOM_SILVERMONT1,       silvermont_params),
1963         ICPU(INTEL_FAM6_IVYBRIDGE,              core_params),
1964         ICPU(INTEL_FAM6_HASWELL_CORE,           core_params),
1965         ICPU(INTEL_FAM6_BROADWELL_CORE,         core_params),
1966         ICPU(INTEL_FAM6_IVYBRIDGE_X,            core_params),
1967         ICPU(INTEL_FAM6_HASWELL_X,              core_params),
1968         ICPU(INTEL_FAM6_HASWELL_ULT,            core_params),
1969         ICPU(INTEL_FAM6_HASWELL_GT3E,           core_params),
1970         ICPU(INTEL_FAM6_BROADWELL_GT3E,         core_params),
1971         ICPU(INTEL_FAM6_ATOM_AIRMONT,           airmont_params),
1972         ICPU(INTEL_FAM6_SKYLAKE_MOBILE,         core_params),
1973         ICPU(INTEL_FAM6_BROADWELL_X,            core_params),
1974         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP,        core_params),
1975         ICPU(INTEL_FAM6_BROADWELL_XEON_D,       core_params),
1976         ICPU(INTEL_FAM6_XEON_PHI_KNL,           knl_params),
1977         ICPU(INTEL_FAM6_XEON_PHI_KNM,           knl_params),
1978         ICPU(INTEL_FAM6_ATOM_GOLDMONT,          bxt_params),
1979         {}
1980 };
1981 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1982
1983 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1984         ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1985         ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1986         ICPU(INTEL_FAM6_SKYLAKE_X, core_params),
1987         {}
1988 };
1989
1990 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1991         ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_params),
1992         {}
1993 };
1994
1995 static int intel_pstate_init_cpu(unsigned int cpunum)
1996 {
1997         struct cpudata *cpu;
1998
1999         cpu = all_cpu_data[cpunum];
2000
2001         if (!cpu) {
2002                 unsigned int size = sizeof(struct cpudata);
2003
2004                 if (per_cpu_limits)
2005                         size += sizeof(struct perf_limits);
2006
2007                 cpu = kzalloc(size, GFP_KERNEL);
2008                 if (!cpu)
2009                         return -ENOMEM;
2010
2011                 all_cpu_data[cpunum] = cpu;
2012                 if (per_cpu_limits)
2013                         cpu->perf_limits = (struct perf_limits *)(cpu + 1);
2014
2015                 cpu->epp_default = -EINVAL;
2016                 cpu->epp_powersave = -EINVAL;
2017                 cpu->epp_saved = -EINVAL;
2018         }
2019
2020         cpu = all_cpu_data[cpunum];
2021
2022         cpu->cpu = cpunum;
2023
2024         if (hwp_active) {
2025                 const struct x86_cpu_id *id;
2026
2027                 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
2028                 if (id)
2029                         intel_pstate_disable_ee(cpunum);
2030
2031                 intel_pstate_hwp_enable(cpu);
2032                 pid_params.sample_rate_ms = 50;
2033                 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
2034         }
2035
2036         intel_pstate_get_cpu_pstates(cpu);
2037
2038         intel_pstate_busy_pid_reset(cpu);
2039
2040         pr_debug("controlling: cpu %d\n", cpunum);
2041
2042         return 0;
2043 }
2044
2045 static unsigned int intel_pstate_get(unsigned int cpu_num)
2046 {
2047         struct cpudata *cpu = all_cpu_data[cpu_num];
2048
2049         return cpu ? get_avg_frequency(cpu) : 0;
2050 }
2051
2052 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2053 {
2054         struct cpudata *cpu = all_cpu_data[cpu_num];
2055
2056         if (cpu->update_util_set)
2057                 return;
2058
2059         /* Prevent intel_pstate_update_util() from using stale data. */
2060         cpu->sample.time = 0;
2061         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2062                                      intel_pstate_update_util);
2063         cpu->update_util_set = true;
2064 }
2065
2066 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2067 {
2068         struct cpudata *cpu_data = all_cpu_data[cpu];
2069
2070         if (!cpu_data->update_util_set)
2071                 return;
2072
2073         cpufreq_remove_update_util_hook(cpu);
2074         cpu_data->update_util_set = false;
2075         synchronize_sched();
2076 }
2077
2078 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
2079                                             struct perf_limits *limits)
2080 {
2081
2082         limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,
2083                                               policy->cpuinfo.max_freq);
2084         limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0, 100);
2085         if (policy->max == policy->min) {
2086                 limits->min_policy_pct = limits->max_policy_pct;
2087         } else {
2088                 limits->min_policy_pct = DIV_ROUND_UP(policy->min * 100,
2089                                                       policy->cpuinfo.max_freq);
2090                 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct,
2091                                                  0, 100);
2092         }
2093
2094         /* Normalize user input to [min_policy_pct, max_policy_pct] */
2095         limits->min_perf_pct = max(limits->min_policy_pct,
2096                                    limits->min_sysfs_pct);
2097         limits->min_perf_pct = min(limits->max_policy_pct,
2098                                    limits->min_perf_pct);
2099         limits->max_perf_pct = min(limits->max_policy_pct,
2100                                    limits->max_sysfs_pct);
2101         limits->max_perf_pct = max(limits->min_policy_pct,
2102                                    limits->max_perf_pct);
2103
2104         /* Make sure min_perf_pct <= max_perf_pct */
2105         limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct);
2106
2107         limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
2108         limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
2109         limits->max_perf = round_up(limits->max_perf, EXT_FRAC_BITS);
2110         limits->min_perf = round_up(limits->min_perf, EXT_FRAC_BITS);
2111
2112         pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
2113                  limits->max_perf_pct, limits->min_perf_pct);
2114 }
2115
2116 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2117 {
2118         struct cpudata *cpu;
2119         struct perf_limits *perf_limits = NULL;
2120
2121         if (!policy->cpuinfo.max_freq)
2122                 return -ENODEV;
2123
2124         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2125                  policy->cpuinfo.max_freq, policy->max);
2126
2127         cpu = all_cpu_data[policy->cpu];
2128         cpu->policy = policy->policy;
2129
2130         if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2131             policy->max < policy->cpuinfo.max_freq &&
2132             policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) {
2133                 pr_debug("policy->max > max non turbo frequency\n");
2134                 policy->max = policy->cpuinfo.max_freq;
2135         }
2136
2137         if (per_cpu_limits)
2138                 perf_limits = cpu->perf_limits;
2139
2140         mutex_lock(&intel_pstate_limits_lock);
2141
2142         if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
2143                 pr_debug("set performance\n");
2144                 if (!perf_limits) {
2145                         limits = &performance_limits;
2146                         perf_limits = limits;
2147                 }
2148         } else {
2149                 pr_debug("set powersave\n");
2150                 if (!perf_limits) {
2151                         limits = &powersave_limits;
2152                         perf_limits = limits;
2153                 }
2154
2155         }
2156
2157         intel_pstate_update_perf_limits(policy, perf_limits);
2158
2159         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2160                 /*
2161                  * NOHZ_FULL CPUs need this as the governor callback may not
2162                  * be invoked on them.
2163                  */
2164                 intel_pstate_clear_update_util_hook(policy->cpu);
2165                 intel_pstate_max_within_limits(cpu);
2166         }
2167
2168         intel_pstate_set_update_util_hook(policy->cpu);
2169
2170         intel_pstate_hwp_set_policy(policy);
2171
2172         mutex_unlock(&intel_pstate_limits_lock);
2173
2174         return 0;
2175 }
2176
2177 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2178 {
2179         struct cpudata *cpu = all_cpu_data[policy->cpu];
2180         struct perf_limits *perf_limits;
2181
2182         if (policy->policy == CPUFREQ_POLICY_PERFORMANCE)
2183                 perf_limits = &performance_limits;
2184         else
2185                 perf_limits = &powersave_limits;
2186
2187         update_turbo_state();
2188         policy->cpuinfo.max_freq = perf_limits->turbo_disabled ||
2189                                         perf_limits->no_turbo ?
2190                                         cpu->pstate.max_freq :
2191                                         cpu->pstate.turbo_freq;
2192
2193         cpufreq_verify_within_cpu_limits(policy);
2194
2195         if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2196             policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2197                 return -EINVAL;
2198
2199         /* When per-CPU limits are used, sysfs limits are not used */
2200         if (!per_cpu_limits) {
2201                 unsigned int max_freq, min_freq;
2202
2203                 max_freq = policy->cpuinfo.max_freq *
2204                                         perf_limits->max_sysfs_pct / 100;
2205                 min_freq = policy->cpuinfo.max_freq *
2206                                         perf_limits->min_sysfs_pct / 100;
2207                 cpufreq_verify_within_limits(policy, min_freq, max_freq);
2208         }
2209
2210         return 0;
2211 }
2212
2213 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2214 {
2215         intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2216 }
2217
2218 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2219 {
2220         pr_debug("CPU %d exiting\n", policy->cpu);
2221
2222         intel_pstate_clear_update_util_hook(policy->cpu);
2223         if (hwp_active)
2224                 intel_pstate_hwp_save_state(policy);
2225         else
2226                 intel_cpufreq_stop_cpu(policy);
2227 }
2228
2229 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2230 {
2231         intel_pstate_exit_perf_limits(policy);
2232
2233         policy->fast_switch_possible = false;
2234
2235         return 0;
2236 }
2237
2238 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2239 {
2240         struct cpudata *cpu;
2241         int rc;
2242
2243         rc = intel_pstate_init_cpu(policy->cpu);
2244         if (rc)
2245                 return rc;
2246
2247         cpu = all_cpu_data[policy->cpu];
2248
2249         if (per_cpu_limits)
2250                 intel_pstate_init_limits(cpu->perf_limits);
2251
2252         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2253         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2254
2255         /* cpuinfo and default policy values */
2256         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2257         update_turbo_state();
2258         policy->cpuinfo.max_freq = limits->turbo_disabled ?
2259                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2260         policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2261
2262         intel_pstate_init_acpi_perf_limits(policy);
2263         cpumask_set_cpu(policy->cpu, policy->cpus);
2264
2265         policy->fast_switch_possible = true;
2266
2267         return 0;
2268 }
2269
2270 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2271 {
2272         int ret = __intel_pstate_cpu_init(policy);
2273
2274         if (ret)
2275                 return ret;
2276
2277         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2278         if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100)
2279                 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2280         else
2281                 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2282
2283         return 0;
2284 }
2285
2286 static struct cpufreq_driver intel_pstate = {
2287         .flags          = CPUFREQ_CONST_LOOPS,
2288         .verify         = intel_pstate_verify_policy,
2289         .setpolicy      = intel_pstate_set_policy,
2290         .suspend        = intel_pstate_hwp_save_state,
2291         .resume         = intel_pstate_resume,
2292         .get            = intel_pstate_get,
2293         .init           = intel_pstate_cpu_init,
2294         .exit           = intel_pstate_cpu_exit,
2295         .stop_cpu       = intel_pstate_stop_cpu,
2296         .name           = "intel_pstate",
2297 };
2298
2299 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2300 {
2301         struct cpudata *cpu = all_cpu_data[policy->cpu];
2302
2303         update_turbo_state();
2304         policy->cpuinfo.max_freq = limits->turbo_disabled ?
2305                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2306
2307         cpufreq_verify_within_cpu_limits(policy);
2308
2309         return 0;
2310 }
2311
2312 static unsigned int intel_cpufreq_turbo_update(struct cpudata *cpu,
2313                                                struct cpufreq_policy *policy,
2314                                                unsigned int target_freq)
2315 {
2316         unsigned int max_freq;
2317
2318         update_turbo_state();
2319
2320         max_freq = limits->no_turbo || limits->turbo_disabled ?
2321                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2322         policy->cpuinfo.max_freq = max_freq;
2323         if (policy->max > max_freq)
2324                 policy->max = max_freq;
2325
2326         if (target_freq > max_freq)
2327                 target_freq = max_freq;
2328
2329         return target_freq;
2330 }
2331
2332 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2333                                 unsigned int target_freq,
2334                                 unsigned int relation)
2335 {
2336         struct cpudata *cpu = all_cpu_data[policy->cpu];
2337         struct cpufreq_freqs freqs;
2338         int target_pstate;
2339
2340         freqs.old = policy->cur;
2341         freqs.new = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2342
2343         cpufreq_freq_transition_begin(policy, &freqs);
2344         switch (relation) {
2345         case CPUFREQ_RELATION_L:
2346                 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2347                 break;
2348         case CPUFREQ_RELATION_H:
2349                 target_pstate = freqs.new / cpu->pstate.scaling;
2350                 break;
2351         default:
2352                 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2353                 break;
2354         }
2355         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2356         if (target_pstate != cpu->pstate.current_pstate) {
2357                 cpu->pstate.current_pstate = target_pstate;
2358                 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2359                               pstate_funcs.get_val(cpu, target_pstate));
2360         }
2361         freqs.new = target_pstate * cpu->pstate.scaling;
2362         cpufreq_freq_transition_end(policy, &freqs, false);
2363
2364         return 0;
2365 }
2366
2367 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2368                                               unsigned int target_freq)
2369 {
2370         struct cpudata *cpu = all_cpu_data[policy->cpu];
2371         int target_pstate;
2372
2373         target_freq = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2374         target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2375         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2376         intel_pstate_update_pstate(cpu, target_pstate);
2377         return target_pstate * cpu->pstate.scaling;
2378 }
2379
2380 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2381 {
2382         int ret = __intel_pstate_cpu_init(policy);
2383
2384         if (ret)
2385                 return ret;
2386
2387         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2388         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2389         policy->cur = policy->cpuinfo.min_freq;
2390
2391         return 0;
2392 }
2393
2394 static struct cpufreq_driver intel_cpufreq = {
2395         .flags          = CPUFREQ_CONST_LOOPS,
2396         .verify         = intel_cpufreq_verify_policy,
2397         .target         = intel_cpufreq_target,
2398         .fast_switch    = intel_cpufreq_fast_switch,
2399         .init           = intel_cpufreq_cpu_init,
2400         .exit           = intel_pstate_cpu_exit,
2401         .stop_cpu       = intel_cpufreq_stop_cpu,
2402         .name           = "intel_cpufreq",
2403 };
2404
2405 static struct cpufreq_driver *intel_pstate_driver = &intel_pstate;
2406
2407 static void intel_pstate_driver_cleanup(void)
2408 {
2409         unsigned int cpu;
2410
2411         get_online_cpus();
2412         for_each_online_cpu(cpu) {
2413                 if (all_cpu_data[cpu]) {
2414                         if (intel_pstate_driver == &intel_pstate)
2415                                 intel_pstate_clear_update_util_hook(cpu);
2416
2417                         kfree(all_cpu_data[cpu]);
2418                         all_cpu_data[cpu] = NULL;
2419                 }
2420         }
2421         put_online_cpus();
2422 }
2423
2424 static int intel_pstate_register_driver(void)
2425 {
2426         int ret;
2427
2428         intel_pstate_init_limits(&powersave_limits);
2429         intel_pstate_set_performance_limits(&performance_limits);
2430         if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE) &&
2431             intel_pstate_driver == &intel_pstate)
2432                 limits = &performance_limits;
2433         else
2434                 limits = &powersave_limits;
2435
2436         ret = cpufreq_register_driver(intel_pstate_driver);
2437         if (ret) {
2438                 intel_pstate_driver_cleanup();
2439                 return ret;
2440         }
2441
2442         mutex_lock(&intel_pstate_limits_lock);
2443         driver_registered = true;
2444         mutex_unlock(&intel_pstate_limits_lock);
2445
2446         if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2447             pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2448                 intel_pstate_debug_expose_params();
2449
2450         return 0;
2451 }
2452
2453 static int intel_pstate_unregister_driver(void)
2454 {
2455         if (hwp_active)
2456                 return -EBUSY;
2457
2458         if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2459             pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2460                 intel_pstate_debug_hide_params();
2461
2462         mutex_lock(&intel_pstate_limits_lock);
2463         driver_registered = false;
2464         mutex_unlock(&intel_pstate_limits_lock);
2465
2466         cpufreq_unregister_driver(intel_pstate_driver);
2467         intel_pstate_driver_cleanup();
2468
2469         return 0;
2470 }
2471
2472 static ssize_t intel_pstate_show_status(char *buf)
2473 {
2474         if (!driver_registered)
2475                 return sprintf(buf, "off\n");
2476
2477         return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2478                                         "active" : "passive");
2479 }
2480
2481 static int intel_pstate_update_status(const char *buf, size_t size)
2482 {
2483         int ret;
2484
2485         if (size == 3 && !strncmp(buf, "off", size))
2486                 return driver_registered ?
2487                         intel_pstate_unregister_driver() : -EINVAL;
2488
2489         if (size == 6 && !strncmp(buf, "active", size)) {
2490                 if (driver_registered) {
2491                         if (intel_pstate_driver == &intel_pstate)
2492                                 return 0;
2493
2494                         ret = intel_pstate_unregister_driver();
2495                         if (ret)
2496                                 return ret;
2497                 }
2498
2499                 intel_pstate_driver = &intel_pstate;
2500                 return intel_pstate_register_driver();
2501         }
2502
2503         if (size == 7 && !strncmp(buf, "passive", size)) {
2504                 if (driver_registered) {
2505                         if (intel_pstate_driver != &intel_pstate)
2506                                 return 0;
2507
2508                         ret = intel_pstate_unregister_driver();
2509                         if (ret)
2510                                 return ret;
2511                 }
2512
2513                 intel_pstate_driver = &intel_cpufreq;
2514                 return intel_pstate_register_driver();
2515         }
2516
2517         return -EINVAL;
2518 }
2519
2520 static int no_load __initdata;
2521 static int no_hwp __initdata;
2522 static int hwp_only __initdata;
2523 static unsigned int force_load __initdata;
2524
2525 static int __init intel_pstate_msrs_not_valid(void)
2526 {
2527         if (!pstate_funcs.get_max() ||
2528             !pstate_funcs.get_min() ||
2529             !pstate_funcs.get_turbo())
2530                 return -ENODEV;
2531
2532         return 0;
2533 }
2534
2535 static void __init copy_pid_params(struct pstate_adjust_policy *policy)
2536 {
2537         pid_params.sample_rate_ms = policy->sample_rate_ms;
2538         pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
2539         pid_params.p_gain_pct = policy->p_gain_pct;
2540         pid_params.i_gain_pct = policy->i_gain_pct;
2541         pid_params.d_gain_pct = policy->d_gain_pct;
2542         pid_params.deadband = policy->deadband;
2543         pid_params.setpoint = policy->setpoint;
2544 }
2545
2546 #ifdef CONFIG_ACPI
2547 static void intel_pstate_use_acpi_profile(void)
2548 {
2549         if (acpi_gbl_FADT.preferred_profile == PM_MOBILE)
2550                 pstate_funcs.get_target_pstate =
2551                                 get_target_pstate_use_cpu_load;
2552 }
2553 #else
2554 static void intel_pstate_use_acpi_profile(void)
2555 {
2556 }
2557 #endif
2558
2559 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2560 {
2561         pstate_funcs.get_max   = funcs->get_max;
2562         pstate_funcs.get_max_physical = funcs->get_max_physical;
2563         pstate_funcs.get_min   = funcs->get_min;
2564         pstate_funcs.get_turbo = funcs->get_turbo;
2565         pstate_funcs.get_scaling = funcs->get_scaling;
2566         pstate_funcs.get_val   = funcs->get_val;
2567         pstate_funcs.get_vid   = funcs->get_vid;
2568         pstate_funcs.get_target_pstate = funcs->get_target_pstate;
2569
2570         intel_pstate_use_acpi_profile();
2571 }
2572
2573 #ifdef CONFIG_ACPI
2574
2575 static bool __init intel_pstate_no_acpi_pss(void)
2576 {
2577         int i;
2578
2579         for_each_possible_cpu(i) {
2580                 acpi_status status;
2581                 union acpi_object *pss;
2582                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2583                 struct acpi_processor *pr = per_cpu(processors, i);
2584
2585                 if (!pr)
2586                         continue;
2587
2588                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2589                 if (ACPI_FAILURE(status))
2590                         continue;
2591
2592                 pss = buffer.pointer;
2593                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2594                         kfree(pss);
2595                         return false;
2596                 }
2597
2598                 kfree(pss);
2599         }
2600
2601         return true;
2602 }
2603
2604 static bool __init intel_pstate_has_acpi_ppc(void)
2605 {
2606         int i;
2607
2608         for_each_possible_cpu(i) {
2609                 struct acpi_processor *pr = per_cpu(processors, i);
2610
2611                 if (!pr)
2612                         continue;
2613                 if (acpi_has_method(pr->handle, "_PPC"))
2614                         return true;
2615         }
2616         return false;
2617 }
2618
2619 enum {
2620         PSS,
2621         PPC,
2622 };
2623
2624 struct hw_vendor_info {
2625         u16  valid;
2626         char oem_id[ACPI_OEM_ID_SIZE];
2627         char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
2628         int  oem_pwr_table;
2629 };
2630
2631 /* Hardware vendor-specific info that has its own power management modes */
2632 static struct hw_vendor_info vendor_info[] __initdata = {
2633         {1, "HP    ", "ProLiant", PSS},
2634         {1, "ORACLE", "X4-2    ", PPC},
2635         {1, "ORACLE", "X4-2L   ", PPC},
2636         {1, "ORACLE", "X4-2B   ", PPC},
2637         {1, "ORACLE", "X3-2    ", PPC},
2638         {1, "ORACLE", "X3-2L   ", PPC},
2639         {1, "ORACLE", "X3-2B   ", PPC},
2640         {1, "ORACLE", "X4470M2 ", PPC},
2641         {1, "ORACLE", "X4270M3 ", PPC},
2642         {1, "ORACLE", "X4270M2 ", PPC},
2643         {1, "ORACLE", "X4170M2 ", PPC},
2644         {1, "ORACLE", "X4170 M3", PPC},
2645         {1, "ORACLE", "X4275 M3", PPC},
2646         {1, "ORACLE", "X6-2    ", PPC},
2647         {1, "ORACLE", "Sudbury ", PPC},
2648         {0, "", ""},
2649 };
2650
2651 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2652 {
2653         struct acpi_table_header hdr;
2654         struct hw_vendor_info *v_info;
2655         const struct x86_cpu_id *id;
2656         u64 misc_pwr;
2657
2658         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2659         if (id) {
2660                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2661                 if ( misc_pwr & (1 << 8))
2662                         return true;
2663         }
2664
2665         if (acpi_disabled ||
2666             ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
2667                 return false;
2668
2669         for (v_info = vendor_info; v_info->valid; v_info++) {
2670                 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
2671                         !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2672                                                 ACPI_OEM_TABLE_ID_SIZE))
2673                         switch (v_info->oem_pwr_table) {
2674                         case PSS:
2675                                 return intel_pstate_no_acpi_pss();
2676                         case PPC:
2677                                 return intel_pstate_has_acpi_ppc() &&
2678                                         (!force_load);
2679                         }
2680         }
2681
2682         return false;
2683 }
2684
2685 static void intel_pstate_request_control_from_smm(void)
2686 {
2687         /*
2688          * It may be unsafe to request P-states control from SMM if _PPC support
2689          * has not been enabled.
2690          */
2691         if (acpi_ppc)
2692                 acpi_processor_pstate_control();
2693 }
2694 #else /* CONFIG_ACPI not enabled */
2695 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2696 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2697 static inline void intel_pstate_request_control_from_smm(void) {}
2698 #endif /* CONFIG_ACPI */
2699
2700 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2701         { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2702         {}
2703 };
2704
2705 static int __init intel_pstate_init(void)
2706 {
2707         const struct x86_cpu_id *id;
2708         struct cpu_defaults *cpu_def;
2709         int rc = 0;
2710
2711         if (no_load)
2712                 return -ENODEV;
2713
2714         if (x86_match_cpu(hwp_support_ids) && !no_hwp) {
2715                 copy_cpu_funcs(&core_params.funcs);
2716                 hwp_active++;
2717                 intel_pstate.attr = hwp_cpufreq_attrs;
2718                 goto hwp_cpu_matched;
2719         }
2720
2721         id = x86_match_cpu(intel_pstate_cpu_ids);
2722         if (!id)
2723                 return -ENODEV;
2724
2725         cpu_def = (struct cpu_defaults *)id->driver_data;
2726
2727         copy_pid_params(&cpu_def->pid_policy);
2728         copy_cpu_funcs(&cpu_def->funcs);
2729
2730         if (intel_pstate_msrs_not_valid())
2731                 return -ENODEV;
2732
2733 hwp_cpu_matched:
2734         /*
2735          * The Intel pstate driver will be ignored if the platform
2736          * firmware has its own power management modes.
2737          */
2738         if (intel_pstate_platform_pwr_mgmt_exists())
2739                 return -ENODEV;
2740
2741         if (!hwp_active && hwp_only)
2742                 return -ENOTSUPP;
2743
2744         pr_info("Intel P-state driver initializing\n");
2745
2746         all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2747         if (!all_cpu_data)
2748                 return -ENOMEM;
2749
2750         intel_pstate_request_control_from_smm();
2751
2752         intel_pstate_sysfs_expose_params();
2753
2754         mutex_lock(&intel_pstate_driver_lock);
2755         rc = intel_pstate_register_driver();
2756         mutex_unlock(&intel_pstate_driver_lock);
2757         if (rc)
2758                 return rc;
2759
2760         if (hwp_active)
2761                 pr_info("HWP enabled\n");
2762
2763         return 0;
2764 }
2765 device_initcall(intel_pstate_init);
2766
2767 static int __init intel_pstate_setup(char *str)
2768 {
2769         if (!str)
2770                 return -EINVAL;
2771
2772         if (!strcmp(str, "disable")) {
2773                 no_load = 1;
2774         } else if (!strcmp(str, "passive")) {
2775                 pr_info("Passive mode enabled\n");
2776                 intel_pstate_driver = &intel_cpufreq;
2777                 no_hwp = 1;
2778         }
2779         if (!strcmp(str, "no_hwp")) {
2780                 pr_info("HWP disabled\n");
2781                 no_hwp = 1;
2782         }
2783         if (!strcmp(str, "force"))
2784                 force_load = 1;
2785         if (!strcmp(str, "hwp_only"))
2786                 hwp_only = 1;
2787         if (!strcmp(str, "per_cpu_perf_limits"))
2788                 per_cpu_limits = true;
2789
2790 #ifdef CONFIG_ACPI
2791         if (!strcmp(str, "support_acpi_ppc"))
2792                 acpi_ppc = true;
2793 #endif
2794
2795         return 0;
2796 }
2797 early_param("intel_pstate", intel_pstate_setup);
2798
2799 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2800 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2801 MODULE_LICENSE("GPL");