drivers/cpufreq/intel_pstate.c

   1 /*
   2  * intel_pstate.c: Native P state management for Intel processors
   3  *
   4  * (C) Copyright 2012 Intel Corporation
   5  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; version 2
  10  * of the License.
  11  */
  12
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/kernel_stat.h>
  17 #include <linux/module.h>
  18 #include <linux/ktime.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/tick.h>
  21 #include <linux/slab.h>
  22 #include <linux/sched/cpufreq.h>
  23 #include <linux/list.h>
  24 #include <linux/cpu.h>
  25 #include <linux/cpufreq.h>
  26 #include <linux/sysfs.h>
  27 #include <linux/types.h>
  28 #include <linux/fs.h>
  29 #include <linux/debugfs.h>
  30 #include <linux/acpi.h>
  31 #include <linux/vmalloc.h>
  32 #include <trace/events/power.h>
  33
  34 #include <asm/div64.h>
  35 #include <asm/msr.h>
  36 #include <asm/cpu_device_id.h>
  37 #include <asm/cpufeature.h>
  38 #include <asm/intel-family.h>
  39
  40 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
  41
  42 #ifdef CONFIG_ACPI
  43 #include <acpi/processor.h>
  44 #include <acpi/cppc_acpi.h>
  45 #endif
  46
  47 #define FRAC_BITS 8
  48 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  49 #define fp_toint(X) ((X) >> FRAC_BITS)
  50
  51 #define EXT_BITS 6
  52 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
  53 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
  54 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
  55
  56 static inline int32_t mul_fp(int32_t x, int32_t y)
  57 {
  58         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  59 }
  60
  61 static inline int32_t div_fp(s64 x, s64 y)
  62 {
  63         return div64_s64((int64_t)x << FRAC_BITS, y);
  64 }
  65
  66 static inline int ceiling_fp(int32_t x)
  67 {
  68         int mask, ret;
  69
  70         ret = fp_toint(x);
  71         mask = (1 << FRAC_BITS) - 1;
  72         if (x & mask)
  73                 ret += 1;
  74         return ret;
  75 }
  76
  77 static inline u64 mul_ext_fp(u64 x, u64 y)
  78 {
  79         return (x * y) >> EXT_FRAC_BITS;
  80 }
  81
  82 static inline u64 div_ext_fp(u64 x, u64 y)
  83 {
  84         return div64_u64(x << EXT_FRAC_BITS, y);
  85 }
  86
  87 static inline int32_t percent_ext_fp(int percent)
  88 {
  89         return div_ext_fp(percent, 100);
  90 }
  91
  92 /**
  93  * struct sample -      Store performance sample
  94  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
  95  *                      performance during last sample period
  96  * @busy_scaled:        Scaled busy value which is used to calculate next
  97  *                      P state. This can be different than core_avg_perf
  98  *                      to account for cpu idle period
  99  * @aperf:              Difference of actual performance frequency clock count
 100  *                      read from APERF MSR between last and current sample
 101  * @mperf:              Difference of maximum performance frequency clock count
 102  *                      read from MPERF MSR between last and current sample
 103  * @tsc:                Difference of time stamp counter between last and
 104  *                      current sample
 105  * @time:               Current time from scheduler
 106  *
 107  * This structure is used in the cpudata structure to store performance sample
 108  * data for choosing next P State.
 109  */
 110 struct sample {
 111         int32_t core_avg_perf;
 112         int32_t busy_scaled;
 113         u64 aperf;
 114         u64 mperf;
 115         u64 tsc;
 116         u64 time;
 117 };
 118
 119 /**
 120  * struct pstate_data - Store P state data
 121  * @current_pstate:     Current requested P state
 122  * @min_pstate:         Min P state possible for this platform
 123  * @max_pstate:         Max P state possible for this platform
 124  * @max_pstate_physical:This is physical Max P state for a processor
 125  *                      This can be higher than the max_pstate which can
 126  *                      be limited by platform thermal design power limits
 127  * @scaling:            Scaling factor to  convert frequency to cpufreq
 128  *                      frequency units
 129  * @turbo_pstate:       Max Turbo P state possible for this platform
 130  * @max_freq:           @max_pstate frequency in cpufreq units
 131  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
 132  *
 133  * Stores the per cpu model P state limits and current P state.
 134  */
 135 struct pstate_data {
 136         int     current_pstate;
 137         int     min_pstate;
 138         int     max_pstate;
 139         int     max_pstate_physical;
 140         int     scaling;
 141         int     turbo_pstate;
 142         unsigned int max_freq;
 143         unsigned int turbo_freq;
 144 };
 145
 146 /**
 147  * struct vid_data -    Stores voltage information data
 148  * @min:                VID data for this platform corresponding to
 149  *                      the lowest P state
 150  * @max:                VID data corresponding to the highest P State.
 151  * @turbo:              VID data for turbo P state
 152  * @ratio:              Ratio of (vid max - vid min) /
 153  *                      (max P state - Min P State)
 154  *
 155  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
 156  * This data is used in Atom platforms, where in addition to target P state,
 157  * the voltage data needs to be specified to select next P State.
 158  */
 159 struct vid_data {
 160         int min;
 161         int max;
 162         int turbo;
 163         int32_t ratio;
 164 };
 165
 166 /**
 167  * struct _pid -        Stores PID data
 168  * @setpoint:           Target set point for busyness or performance
 169  * @integral:           Storage for accumulated error values
 170  * @p_gain:             PID proportional gain
 171  * @i_gain:             PID integral gain
 172  * @d_gain:             PID derivative gain
 173  * @deadband:           PID deadband
 174  * @last_err:           Last error storage for integral part of PID calculation
 175  *
 176  * Stores PID coefficients and last error for PID controller.
 177  */
 178 struct _pid {
 179         int setpoint;
 180         int32_t integral;
 181         int32_t p_gain;
 182         int32_t i_gain;
 183         int32_t d_gain;
 184         int deadband;
 185         int32_t last_err;
 186 };
 187
 188 /**
 189  * struct global_params - Global parameters, mostly tunable via sysfs.
 190  * @no_turbo:           Whether or not to use turbo P-states.
 191  * @turbo_disabled:     Whethet or not turbo P-states are available at all,
 192  *                      based on the MSR_IA32_MISC_ENABLE value and whether or
 193  *                      not the maximum reported turbo P-state is different from
 194  *                      the maximum reported non-turbo one.
 195  * @min_perf_pct:       Minimum capacity limit in percent of the maximum turbo
 196  *                      P-state capacity.
 197  * @max_perf_pct:       Maximum capacity limit in percent of the maximum turbo
 198  *                      P-state capacity.
 199  */
 200 struct global_params {
 201         bool no_turbo;
 202         bool turbo_disabled;
 203         int max_perf_pct;
 204         int min_perf_pct;
 205 };
 206
 207 /**
 208  * struct cpudata -     Per CPU instance data storage
 209  * @cpu:                CPU number for this instance data
 210  * @policy:             CPUFreq policy value
 211  * @update_util:        CPUFreq utility callback information
 212  * @update_util_set:    CPUFreq utility callback is set
 213  * @iowait_boost:       iowait-related boost fraction
 214  * @last_update:        Time of the last update.
 215  * @pstate:             Stores P state limits for this CPU
 216  * @vid:                Stores VID limits for this CPU
 217  * @pid:                Stores PID parameters for this CPU
 218  * @last_sample_time:   Last Sample time
 219  * @prev_aperf:         Last APERF value read from APERF MSR
 220  * @prev_mperf:         Last MPERF value read from MPERF MSR
 221  * @prev_tsc:           Last timestamp counter (TSC) value
 222  * @prev_cummulative_iowait: IO Wait time difference from last and
 223  *                      current sample
 224  * @sample:             Storage for storing last Sample data
 225  * @min_perf:           Minimum capacity limit as a fraction of the maximum
 226  *                      turbo P-state capacity.
 227  * @max_perf:           Maximum capacity limit as a fraction of the maximum
 228  *                      turbo P-state capacity.
 229  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
 230  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
 231  * @epp_powersave:      Last saved HWP energy performance preference
 232  *                      (EPP) or energy performance bias (EPB),
 233  *                      when policy switched to performance
 234  * @epp_policy:         Last saved policy used to set EPP/EPB
 235  * @epp_default:        Power on default HWP energy performance
 236  *                      preference/bias
 237  * @epp_saved:          Saved EPP/EPB during system suspend or CPU offline
 238  *                      operation
 239  *
 240  * This structure stores per CPU instance data for all CPUs.
 241  */
 242 struct cpudata {
 243         int cpu;
 244
 245         unsigned int policy;
 246         struct update_util_data update_util;
 247         bool   update_util_set;
 248
 249         struct pstate_data pstate;
 250         struct vid_data vid;
 251         struct _pid pid;
 252
 253         u64     last_update;
 254         u64     last_sample_time;
 255         u64     prev_aperf;
 256         u64     prev_mperf;
 257         u64     prev_tsc;
 258         u64     prev_cummulative_iowait;
 259         struct sample sample;
 260         int32_t min_perf;
 261         int32_t max_perf;
 262 #ifdef CONFIG_ACPI
 263         struct acpi_processor_performance acpi_perf_data;
 264         bool valid_pss_table;
 265 #endif
 266         unsigned int iowait_boost;
 267         s16 epp_powersave;
 268         s16 epp_policy;
 269         s16 epp_default;
 270         s16 epp_saved;
 271 };
 272
 273 static struct cpudata **all_cpu_data;
 274
 275 /**
 276  * struct pstate_adjust_policy - Stores static PID configuration data
 277  * @sample_rate_ms:     PID calculation sample rate in ms
 278  * @sample_rate_ns:     Sample rate calculation in ns
 279  * @deadband:           PID deadband
 280  * @setpoint:           PID Setpoint
 281  * @p_gain_pct:         PID proportional gain
 282  * @i_gain_pct:         PID integral gain
 283  * @d_gain_pct:         PID derivative gain
 284  *
 285  * Stores per CPU model static PID configuration data.
 286  */
 287 struct pstate_adjust_policy {
 288         int sample_rate_ms;
 289         s64 sample_rate_ns;
 290         int deadband;
 291         int setpoint;
 292         int p_gain_pct;
 293         int d_gain_pct;
 294         int i_gain_pct;
 295 };
 296
 297 /**
 298  * struct pstate_funcs - Per CPU model specific callbacks
 299  * @get_max:            Callback to get maximum non turbo effective P state
 300  * @get_max_physical:   Callback to get maximum non turbo physical P state
 301  * @get_min:            Callback to get minimum P state
 302  * @get_turbo:          Callback to get turbo P state
 303  * @get_scaling:        Callback to get frequency scaling factor
 304  * @get_val:            Callback to convert P state to actual MSR write value
 305  * @get_vid:            Callback to get VID data for Atom platforms
 306  * @get_target_pstate:  Callback to a function to calculate next P state to use
 307  *
 308  * Core and Atom CPU models have different way to get P State limits. This
 309  * structure is used to store those callbacks.
 310  */
 311 struct pstate_funcs {
 312         int (*get_max)(void);
 313         int (*get_max_physical)(void);
 314         int (*get_min)(void);
 315         int (*get_turbo)(void);
 316         int (*get_scaling)(void);
 317         u64 (*get_val)(struct cpudata*, int pstate);
 318         void (*get_vid)(struct cpudata *);
 319         int32_t (*get_target_pstate)(struct cpudata *);
 320 };
 321
 322 /**
 323  * struct cpu_defaults- Per CPU model default config data
 324  * @funcs:              Callback function data
 325  */
 326 struct cpu_defaults {
 327         struct pstate_funcs funcs;
 328 };
 329
 330 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
 331 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
 332
 333 static struct pstate_funcs pstate_funcs __read_mostly;
 334 static struct pstate_adjust_policy pid_params __read_mostly = {
 335         .sample_rate_ms = 10,
 336         .sample_rate_ns = 10 * NSEC_PER_MSEC,
 337         .deadband = 0,
 338         .setpoint = 97,
 339         .p_gain_pct = 20,
 340         .d_gain_pct = 0,
 341         .i_gain_pct = 0,
 342 };
 343
 344 static int hwp_active __read_mostly;
 345 static bool per_cpu_limits __read_mostly;
 346
 347 static bool driver_registered __read_mostly;
 348
 349 #ifdef CONFIG_ACPI
 350 static bool acpi_ppc;
 351 #endif
 352
 353 static struct global_params global;
 354
 355 static DEFINE_MUTEX(intel_pstate_driver_lock);
 356 static DEFINE_MUTEX(intel_pstate_limits_lock);
 357
 358 #ifdef CONFIG_ACPI
 359
 360 static bool intel_pstate_get_ppc_enable_status(void)
 361 {
 362         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
 363             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
 364                 return true;
 365
 366         return acpi_ppc;
 367 }
 368
 369 #ifdef CONFIG_ACPI_CPPC_LIB
 370
 371 /* The work item is needed to avoid CPU hotplug locking issues */
 372 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
 373 {
 374         sched_set_itmt_support();
 375 }
 376
 377 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
 378
 379 static void intel_pstate_set_itmt_prio(int cpu)
 380 {
 381         struct cppc_perf_caps cppc_perf;
 382         static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
 383         int ret;
 384
 385         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 386         if (ret)
 387                 return;
 388
 389         /*
 390          * The priorities can be set regardless of whether or not
 391          * sched_set_itmt_support(true) has been called and it is valid to
 392          * update them at any time after it has been called.
 393          */
 394         sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
 395
 396         if (max_highest_perf <= min_highest_perf) {
 397                 if (cppc_perf.highest_perf > max_highest_perf)
 398                         max_highest_perf = cppc_perf.highest_perf;
 399
 400                 if (cppc_perf.highest_perf < min_highest_perf)
 401                         min_highest_perf = cppc_perf.highest_perf;
 402
 403                 if (max_highest_perf > min_highest_perf) {
 404                         /*
 405                          * This code can be run during CPU online under the
 406                          * CPU hotplug locks, so sched_set_itmt_support()
 407                          * cannot be called from here.  Queue up a work item
 408                          * to invoke it.
 409                          */
 410                         schedule_work(&sched_itmt_work);
 411                 }
 412         }
 413 }
 414 #else
 415 static void intel_pstate_set_itmt_prio(int cpu)
 416 {
 417 }
 418 #endif
 419
 420 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 421 {
 422         struct cpudata *cpu;
 423         int ret;
 424         int i;
 425
 426         if (hwp_active) {
 427                 intel_pstate_set_itmt_prio(policy->cpu);
 428                 return;
 429         }
 430
 431         if (!intel_pstate_get_ppc_enable_status())
 432                 return;
 433
 434         cpu = all_cpu_data[policy->cpu];
 435
 436         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
 437                                                   policy->cpu);
 438         if (ret)
 439                 return;
 440
 441         /*
 442          * Check if the control value in _PSS is for PERF_CTL MSR, which should
 443          * guarantee that the states returned by it map to the states in our
 444          * list directly.
 445          */
 446         if (cpu->acpi_perf_data.control_register.space_id !=
 447                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
 448                 goto err;
 449
 450         /*
 451          * If there is only one entry _PSS, simply ignore _PSS and continue as
 452          * usual without taking _PSS into account
 453          */
 454         if (cpu->acpi_perf_data.state_count < 2)
 455                 goto err;
 456
 457         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
 458         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
 459                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
 460                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
 461                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
 462                          (u32) cpu->acpi_perf_data.states[i].power,
 463                          (u32) cpu->acpi_perf_data.states[i].control);
 464         }
 465
 466         /*
 467          * The _PSS table doesn't contain whole turbo frequency range.
 468          * This just contains +1 MHZ above the max non turbo frequency,
 469          * with control value corresponding to max turbo ratio. But
 470          * when cpufreq set policy is called, it will call with this
 471          * max frequency, which will cause a reduced performance as
 472          * this driver uses real max turbo frequency as the max
 473          * frequency. So correct this frequency in _PSS table to
 474          * correct max turbo frequency based on the turbo state.
 475          * Also need to convert to MHz as _PSS freq is in MHz.
 476          */
 477         if (!global.turbo_disabled)
 478                 cpu->acpi_perf_data.states[0].core_frequency =
 479                                         policy->cpuinfo.max_freq / 1000;
 480         cpu->valid_pss_table = true;
 481         pr_debug("_PPC limits will be enforced\n");
 482
 483         return;
 484
 485  err:
 486         cpu->valid_pss_table = false;
 487         acpi_processor_unregister_performance(policy->cpu);
 488 }
 489
 490 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 491 {
 492         struct cpudata *cpu;
 493
 494         cpu = all_cpu_data[policy->cpu];
 495         if (!cpu->valid_pss_table)
 496                 return;
 497
 498         acpi_processor_unregister_performance(policy->cpu);
 499 }
 500 #else
 501 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 502 {
 503 }
 504
 505 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 506 {
 507 }
 508 #endif
 509
 510 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
 511                              int deadband, int integral) {
 512         pid->setpoint = int_tofp(setpoint);
 513         pid->deadband  = int_tofp(deadband);
 514         pid->integral  = int_tofp(integral);
 515         pid->last_err  = int_tofp(setpoint) - int_tofp(busy);
 516 }
 517
 518 static inline void pid_p_gain_set(struct _pid *pid, int percent)
 519 {
 520         pid->p_gain = div_fp(percent, 100);
 521 }
 522
 523 static inline void pid_i_gain_set(struct _pid *pid, int percent)
 524 {
 525         pid->i_gain = div_fp(percent, 100);
 526 }
 527
 528 static inline void pid_d_gain_set(struct _pid *pid, int percent)
 529 {
 530         pid->d_gain = div_fp(percent, 100);
 531 }
 532
 533 static signed int pid_calc(struct _pid *pid, int32_t busy)
 534 {
 535         signed int result;
 536         int32_t pterm, dterm, fp_error;
 537         int32_t integral_limit;
 538
 539         fp_error = pid->setpoint - busy;
 540
 541         if (abs(fp_error) <= pid->deadband)
 542                 return 0;
 543
 544         pterm = mul_fp(pid->p_gain, fp_error);
 545
 546         pid->integral += fp_error;
 547
 548         /*
 549          * We limit the integral here so that it will never
 550          * get higher than 30.  This prevents it from becoming
 551          * too large an input over long periods of time and allows
 552          * it to get factored out sooner.
 553          *
 554          * The value of 30 was chosen through experimentation.
 555          */
 556         integral_limit = int_tofp(30);
 557         if (pid->integral > integral_limit)
 558                 pid->integral = integral_limit;
 559         if (pid->integral < -integral_limit)
 560                 pid->integral = -integral_limit;
 561
 562         dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
 563         pid->last_err = fp_error;
 564
 565         result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
 566         result = result + (1 << (FRAC_BITS-1));
 567         return (signed int)fp_toint(result);
 568 }
 569
 570 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
 571 {
 572         pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
 573         pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
 574         pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
 575
 576         pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
 577 }
 578
 579 static inline void intel_pstate_reset_all_pid(void)
 580 {
 581         unsigned int cpu;
 582
 583         for_each_online_cpu(cpu) {
 584                 if (all_cpu_data[cpu])
 585                         intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
 586         }
 587 }
 588
 589 static inline void update_turbo_state(void)
 590 {
 591         u64 misc_en;
 592         struct cpudata *cpu;
 593
 594         cpu = all_cpu_data[0];
 595         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 596         global.turbo_disabled =
 597                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
 598                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
 599 }
 600
 601 static int min_perf_pct_min(void)
 602 {
 603         struct cpudata *cpu = all_cpu_data[0];
 604
 605         return DIV_ROUND_UP(cpu->pstate.min_pstate * 100,
 606                             cpu->pstate.turbo_pstate);
 607 }
 608
 609 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
 610 {
 611         u64 epb;
 612         int ret;
 613
 614         if (!static_cpu_has(X86_FEATURE_EPB))
 615                 return -ENXIO;
 616
 617         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 618         if (ret)
 619                 return (s16)ret;
 620
 621         return (s16)(epb & 0x0f);
 622 }
 623
 624 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
 625 {
 626         s16 epp;
 627
 628         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 629                 /*
 630                  * When hwp_req_data is 0, means that caller didn't read
 631                  * MSR_HWP_REQUEST, so need to read and get EPP.
 632                  */
 633                 if (!hwp_req_data) {
 634                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
 635                                             &hwp_req_data);
 636                         if (epp)
 637                                 return epp;
 638                 }
 639                 epp = (hwp_req_data >> 24) & 0xff;
 640         } else {
 641                 /* When there is no EPP present, HWP uses EPB settings */
 642                 epp = intel_pstate_get_epb(cpu_data);
 643         }
 644
 645         return epp;
 646 }
 647
 648 static int intel_pstate_set_epb(int cpu, s16 pref)
 649 {
 650         u64 epb;
 651         int ret;
 652
 653         if (!static_cpu_has(X86_FEATURE_EPB))
 654                 return -ENXIO;
 655
 656         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 657         if (ret)
 658                 return ret;
 659
 660         epb = (epb & ~0x0f) | pref;
 661         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
 662
 663         return 0;
 664 }
 665
 666 /*
 667  * EPP/EPB display strings corresponding to EPP index in the
 668  * energy_perf_strings[]
 669  *      index           String
 670  *-------------------------------------
 671  *      0               default
 672  *      1               performance
 673  *      2               balance_performance
 674  *      3               balance_power
 675  *      4               power
 676  */
 677 static const char * const energy_perf_strings[] = {
 678         "default",
 679         "performance",
 680         "balance_performance",
 681         "balance_power",
 682         "power",
 683         NULL
 684 };
 685
 686 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
 687 {
 688         s16 epp;
 689         int index = -EINVAL;
 690
 691         epp = intel_pstate_get_epp(cpu_data, 0);
 692         if (epp < 0)
 693                 return epp;
 694
 695         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 696                 /*
 697                  * Range:
 698                  *      0x00-0x3F       :       Performance
 699                  *      0x40-0x7F       :       Balance performance
 700                  *      0x80-0xBF       :       Balance power
 701                  *      0xC0-0xFF       :       Power
 702                  * The EPP is a 8 bit value, but our ranges restrict the
 703                  * value which can be set. Here only using top two bits
 704                  * effectively.
 705                  */
 706                 index = (epp >> 6) + 1;
 707         } else if (static_cpu_has(X86_FEATURE_EPB)) {
 708                 /*
 709                  * Range:
 710                  *      0x00-0x03       :       Performance
 711                  *      0x04-0x07       :       Balance performance
 712                  *      0x08-0x0B       :       Balance power
 713                  *      0x0C-0x0F       :       Power
 714                  * The EPB is a 4 bit value, but our ranges restrict the
 715                  * value which can be set. Here only using top two bits
 716                  * effectively.
 717                  */
 718                 index = (epp >> 2) + 1;
 719         }
 720
 721         return index;
 722 }
 723
 724 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
 725                                               int pref_index)
 726 {
 727         int epp = -EINVAL;
 728         int ret;
 729
 730         if (!pref_index)
 731                 epp = cpu_data->epp_default;
 732
 733         mutex_lock(&intel_pstate_limits_lock);
 734
 735         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 736                 u64 value;
 737
 738                 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
 739                 if (ret)
 740                         goto return_pref;
 741
 742                 value &= ~GENMASK_ULL(31, 24);
 743
 744                 /*
 745                  * If epp is not default, convert from index into
 746                  * energy_perf_strings to epp value, by shifting 6
 747                  * bits left to use only top two bits in epp.
 748                  * The resultant epp need to shifted by 24 bits to
 749                  * epp position in MSR_HWP_REQUEST.
 750                  */
 751                 if (epp == -EINVAL)
 752                         epp = (pref_index - 1) << 6;
 753
 754                 value |= (u64)epp << 24;
 755                 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
 756         } else {
 757                 if (epp == -EINVAL)
 758                         epp = (pref_index - 1) << 2;
 759                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
 760         }
 761 return_pref:
 762         mutex_unlock(&intel_pstate_limits_lock);
 763
 764         return ret;
 765 }
 766
 767 static ssize_t show_energy_performance_available_preferences(
 768                                 struct cpufreq_policy *policy, char *buf)
 769 {
 770         int i = 0;
 771         int ret = 0;
 772
 773         while (energy_perf_strings[i] != NULL)
 774                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
 775
 776         ret += sprintf(&buf[ret], "\n");
 777
 778         return ret;
 779 }
 780
 781 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 782
 783 static ssize_t store_energy_performance_preference(
 784                 struct cpufreq_policy *policy, const char *buf, size_t count)
 785 {
 786         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 787         char str_preference[21];
 788         int ret, i = 0;
 789
 790         ret = sscanf(buf, "%20s", str_preference);
 791         if (ret != 1)
 792                 return -EINVAL;
 793
 794         while (energy_perf_strings[i] != NULL) {
 795                 if (!strcmp(str_preference, energy_perf_strings[i])) {
 796                         intel_pstate_set_energy_pref_index(cpu_data, i);
 797                         return count;
 798                 }
 799                 ++i;
 800         }
 801
 802         return -EINVAL;
 803 }
 804
 805 static ssize_t show_energy_performance_preference(
 806                                 struct cpufreq_policy *policy, char *buf)
 807 {
 808         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 809         int preference;
 810
 811         preference = intel_pstate_get_energy_pref_index(cpu_data);
 812         if (preference < 0)
 813                 return preference;
 814
 815         return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
 816 }
 817
 818 cpufreq_freq_attr_rw(energy_performance_preference);
 819
 820 static struct freq_attr *hwp_cpufreq_attrs[] = {
 821         &energy_performance_preference,
 822         &energy_performance_available_preferences,
 823         NULL,
 824 };
 825
 826 static void intel_pstate_hwp_set(struct cpufreq_policy *policy)
 827 {
 828         int min, hw_min, max, hw_max, cpu;
 829         u64 value, cap;
 830
 831         for_each_cpu(cpu, policy->cpus) {
 832                 struct cpudata *cpu_data = all_cpu_data[cpu];
 833                 s16 epp;
 834
 835                 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
 836                 hw_min = HWP_LOWEST_PERF(cap);
 837                 if (global.no_turbo)
 838                         hw_max = HWP_GUARANTEED_PERF(cap);
 839                 else
 840                         hw_max = HWP_HIGHEST_PERF(cap);
 841
 842                 max = fp_ext_toint(hw_max * cpu_data->max_perf);
 843                 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
 844                         min = max;
 845                 else
 846                         min = fp_ext_toint(hw_max * cpu_data->min_perf);
 847
 848                 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 849
 850                 value &= ~HWP_MIN_PERF(~0L);
 851                 value |= HWP_MIN_PERF(min);
 852
 853                 value &= ~HWP_MAX_PERF(~0L);
 854                 value |= HWP_MAX_PERF(max);
 855
 856                 if (cpu_data->epp_policy == cpu_data->policy)
 857                         goto skip_epp;
 858
 859                 cpu_data->epp_policy = cpu_data->policy;
 860
 861                 if (cpu_data->epp_saved >= 0) {
 862                         epp = cpu_data->epp_saved;
 863                         cpu_data->epp_saved = -EINVAL;
 864                         goto update_epp;
 865                 }
 866
 867                 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
 868                         epp = intel_pstate_get_epp(cpu_data, value);
 869                         cpu_data->epp_powersave = epp;
 870                         /* If EPP read was failed, then don't try to write */
 871                         if (epp < 0)
 872                                 goto skip_epp;
 873
 874
 875                         epp = 0;
 876                 } else {
 877                         /* skip setting EPP, when saved value is invalid */
 878                         if (cpu_data->epp_powersave < 0)
 879                                 goto skip_epp;
 880
 881                         /*
 882                          * No need to restore EPP when it is not zero. This
 883                          * means:
 884                          *  - Policy is not changed
 885                          *  - user has manually changed
 886                          *  - Error reading EPB
 887                          */
 888                         epp = intel_pstate_get_epp(cpu_data, value);
 889                         if (epp)
 890                                 goto skip_epp;
 891
 892                         epp = cpu_data->epp_powersave;
 893                 }
 894 update_epp:
 895                 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 896                         value &= ~GENMASK_ULL(31, 24);
 897                         value |= (u64)epp << 24;
 898                 } else {
 899                         intel_pstate_set_epb(cpu, epp);
 900                 }
 901 skip_epp:
 902                 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 903         }
 904 }
 905
 906 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
 907 {
 908         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 909
 910         if (!hwp_active)
 911                 return 0;
 912
 913         cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
 914
 915         return 0;
 916 }
 917
 918 static int intel_pstate_resume(struct cpufreq_policy *policy)
 919 {
 920         if (!hwp_active)
 921                 return 0;
 922
 923         mutex_lock(&intel_pstate_limits_lock);
 924
 925         all_cpu_data[policy->cpu]->epp_policy = 0;
 926         intel_pstate_hwp_set(policy);
 927
 928         mutex_unlock(&intel_pstate_limits_lock);
 929
 930         return 0;
 931 }
 932
 933 static void intel_pstate_update_policies(void)
 934 {
 935         int cpu;
 936
 937         for_each_possible_cpu(cpu)
 938                 cpufreq_update_policy(cpu);
 939 }
 940
 941 /************************** debugfs begin ************************/
 942 static int pid_param_set(void *data, u64 val)
 943 {
 944         *(u32 *)data = val;
 945         pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
 946         intel_pstate_reset_all_pid();
 947         return 0;
 948 }
 949
 950 static int pid_param_get(void *data, u64 *val)
 951 {
 952         *val = *(u32 *)data;
 953         return 0;
 954 }
 955 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
 956
 957 static struct dentry *debugfs_parent;
 958
 959 struct pid_param {
 960         char *name;
 961         void *value;
 962         struct dentry *dentry;
 963 };
 964
 965 static struct pid_param pid_files[] = {
 966         {"sample_rate_ms", &pid_params.sample_rate_ms, },
 967         {"d_gain_pct", &pid_params.d_gain_pct, },
 968         {"i_gain_pct", &pid_params.i_gain_pct, },
 969         {"deadband", &pid_params.deadband, },
 970         {"setpoint", &pid_params.setpoint, },
 971         {"p_gain_pct", &pid_params.p_gain_pct, },
 972         {NULL, NULL, }
 973 };
 974
 975 static void intel_pstate_debug_expose_params(void)
 976 {
 977         int i;
 978
 979         debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
 980         if (IS_ERR_OR_NULL(debugfs_parent))
 981                 return;
 982
 983         for (i = 0; pid_files[i].name; i++) {
 984                 struct dentry *dentry;
 985
 986                 dentry = debugfs_create_file(pid_files[i].name, 0660,
 987                                              debugfs_parent, pid_files[i].value,
 988                                              &fops_pid_param);
 989                 if (!IS_ERR(dentry))
 990                         pid_files[i].dentry = dentry;
 991         }
 992 }
 993
 994 static void intel_pstate_debug_hide_params(void)
 995 {
 996         int i;
 997
 998         if (IS_ERR_OR_NULL(debugfs_parent))
 999                 return;
1000
1001         for (i = 0; pid_files[i].name; i++) {
1002                 debugfs_remove(pid_files[i].dentry);
1003                 pid_files[i].dentry = NULL;
1004         }
1005
1006         debugfs_remove(debugfs_parent);
1007         debugfs_parent = NULL;
1008 }
1009
1010 /************************** debugfs end ************************/
1011
1012 /************************** sysfs begin ************************/
1013 #define show_one(file_name, object)                                     \
1014         static ssize_t show_##file_name                                 \
1015         (struct kobject *kobj, struct attribute *attr, char *buf)       \
1016         {                                                               \
1017                 return sprintf(buf, "%u\n", global.object);             \
1018         }
1019
1020 static ssize_t intel_pstate_show_status(char *buf);
1021 static int intel_pstate_update_status(const char *buf, size_t size);
1022
1023 static ssize_t show_status(struct kobject *kobj,
1024                            struct attribute *attr, char *buf)
1025 {
1026         ssize_t ret;
1027
1028         mutex_lock(&intel_pstate_driver_lock);
1029         ret = intel_pstate_show_status(buf);
1030         mutex_unlock(&intel_pstate_driver_lock);
1031
1032         return ret;
1033 }
1034
1035 static ssize_t store_status(struct kobject *a, struct attribute *b,
1036                             const char *buf, size_t count)
1037 {
1038         char *p = memchr(buf, '\n', count);
1039         int ret;
1040
1041         mutex_lock(&intel_pstate_driver_lock);
1042         ret = intel_pstate_update_status(buf, p ? p - buf : count);
1043         mutex_unlock(&intel_pstate_driver_lock);
1044
1045         return ret < 0 ? ret : count;
1046 }
1047
1048 static ssize_t show_turbo_pct(struct kobject *kobj,
1049                                 struct attribute *attr, char *buf)
1050 {
1051         struct cpudata *cpu;
1052         int total, no_turbo, turbo_pct;
1053         uint32_t turbo_fp;
1054
1055         mutex_lock(&intel_pstate_driver_lock);
1056
1057         if (!driver_registered) {
1058                 mutex_unlock(&intel_pstate_driver_lock);
1059                 return -EAGAIN;
1060         }
1061
1062         cpu = all_cpu_data[0];
1063
1064         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1065         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1066         turbo_fp = div_fp(no_turbo, total);
1067         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1068
1069         mutex_unlock(&intel_pstate_driver_lock);
1070
1071         return sprintf(buf, "%u\n", turbo_pct);
1072 }
1073
1074 static ssize_t show_num_pstates(struct kobject *kobj,
1075                                 struct attribute *attr, char *buf)
1076 {
1077         struct cpudata *cpu;
1078         int total;
1079
1080         mutex_lock(&intel_pstate_driver_lock);
1081
1082         if (!driver_registered) {
1083                 mutex_unlock(&intel_pstate_driver_lock);
1084                 return -EAGAIN;
1085         }
1086
1087         cpu = all_cpu_data[0];
1088         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1089
1090         mutex_unlock(&intel_pstate_driver_lock);
1091
1092         return sprintf(buf, "%u\n", total);
1093 }
1094
1095 static ssize_t show_no_turbo(struct kobject *kobj,
1096                              struct attribute *attr, char *buf)
1097 {
1098         ssize_t ret;
1099
1100         mutex_lock(&intel_pstate_driver_lock);
1101
1102         if (!driver_registered) {
1103                 mutex_unlock(&intel_pstate_driver_lock);
1104                 return -EAGAIN;
1105         }
1106
1107         update_turbo_state();
1108         if (global.turbo_disabled)
1109                 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1110         else
1111                 ret = sprintf(buf, "%u\n", global.no_turbo);
1112
1113         mutex_unlock(&intel_pstate_driver_lock);
1114
1115         return ret;
1116 }
1117
1118 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
1119                               const char *buf, size_t count)
1120 {
1121         unsigned int input;
1122         int ret;
1123
1124         ret = sscanf(buf, "%u", &input);
1125         if (ret != 1)
1126                 return -EINVAL;
1127
1128         mutex_lock(&intel_pstate_driver_lock);
1129
1130         if (!driver_registered) {
1131                 mutex_unlock(&intel_pstate_driver_lock);
1132                 return -EAGAIN;
1133         }
1134
1135         mutex_lock(&intel_pstate_limits_lock);
1136
1137         update_turbo_state();
1138         if (global.turbo_disabled) {
1139                 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1140                 mutex_unlock(&intel_pstate_limits_lock);
1141                 mutex_unlock(&intel_pstate_driver_lock);
1142                 return -EPERM;
1143         }
1144
1145         global.no_turbo = clamp_t(int, input, 0, 1);
1146
1147         if (global.no_turbo) {
1148                 struct cpudata *cpu = all_cpu_data[0];
1149                 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1150
1151                 /* Squash the global minimum into the permitted range. */
1152                 if (global.min_perf_pct > pct)
1153                         global.min_perf_pct = pct;
1154         }
1155
1156         mutex_unlock(&intel_pstate_limits_lock);
1157
1158         intel_pstate_update_policies();
1159
1160         mutex_unlock(&intel_pstate_driver_lock);
1161
1162         return count;
1163 }
1164
1165 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
1166                                   const char *buf, size_t count)
1167 {
1168         unsigned int input;
1169         int ret;
1170
1171         ret = sscanf(buf, "%u", &input);
1172         if (ret != 1)
1173                 return -EINVAL;
1174
1175         mutex_lock(&intel_pstate_driver_lock);
1176
1177         if (!driver_registered) {
1178                 mutex_unlock(&intel_pstate_driver_lock);
1179                 return -EAGAIN;
1180         }
1181
1182         mutex_lock(&intel_pstate_limits_lock);
1183
1184         global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1185
1186         mutex_unlock(&intel_pstate_limits_lock);
1187
1188         intel_pstate_update_policies();
1189
1190         mutex_unlock(&intel_pstate_driver_lock);
1191
1192         return count;
1193 }
1194
1195 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1196                                   const char *buf, size_t count)
1197 {
1198         unsigned int input;
1199         int ret;
1200
1201         ret = sscanf(buf, "%u", &input);
1202         if (ret != 1)
1203                 return -EINVAL;
1204
1205         mutex_lock(&intel_pstate_driver_lock);
1206
1207         if (!driver_registered) {
1208                 mutex_unlock(&intel_pstate_driver_lock);
1209                 return -EAGAIN;
1210         }
1211
1212         mutex_lock(&intel_pstate_limits_lock);
1213
1214         global.min_perf_pct = clamp_t(int, input,
1215                                       min_perf_pct_min(), global.max_perf_pct);
1216
1217         mutex_unlock(&intel_pstate_limits_lock);
1218
1219         intel_pstate_update_policies();
1220
1221         mutex_unlock(&intel_pstate_driver_lock);
1222
1223         return count;
1224 }
1225
1226 show_one(max_perf_pct, max_perf_pct);
1227 show_one(min_perf_pct, min_perf_pct);
1228
1229 define_one_global_rw(status);
1230 define_one_global_rw(no_turbo);
1231 define_one_global_rw(max_perf_pct);
1232 define_one_global_rw(min_perf_pct);
1233 define_one_global_ro(turbo_pct);
1234 define_one_global_ro(num_pstates);
1235
1236 static struct attribute *intel_pstate_attributes[] = {
1237         &status.attr,
1238         &no_turbo.attr,
1239         &turbo_pct.attr,
1240         &num_pstates.attr,
1241         NULL
1242 };
1243
1244 static struct attribute_group intel_pstate_attr_group = {
1245         .attrs = intel_pstate_attributes,
1246 };
1247
1248 static void __init intel_pstate_sysfs_expose_params(void)
1249 {
1250         struct kobject *intel_pstate_kobject;
1251         int rc;
1252
1253         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1254                                                 &cpu_subsys.dev_root->kobj);
1255         if (WARN_ON(!intel_pstate_kobject))
1256                 return;
1257
1258         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1259         if (WARN_ON(rc))
1260                 return;
1261
1262         /*
1263          * If per cpu limits are enforced there are no global limits, so
1264          * return without creating max/min_perf_pct attributes
1265          */
1266         if (per_cpu_limits)
1267                 return;
1268
1269         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1270         WARN_ON(rc);
1271
1272         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1273         WARN_ON(rc);
1274
1275 }
1276 /************************** sysfs end ************************/
1277
1278 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1279 {
1280         /* First disable HWP notification interrupt as we don't process them */
1281         if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1282                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1283
1284         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1285         cpudata->epp_policy = 0;
1286         if (cpudata->epp_default == -EINVAL)
1287                 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1288 }
1289
1290 #define MSR_IA32_POWER_CTL_BIT_EE       19
1291
1292 /* Disable energy efficiency optimization */
1293 static void intel_pstate_disable_ee(int cpu)
1294 {
1295         u64 power_ctl;
1296         int ret;
1297
1298         ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1299         if (ret)
1300                 return;
1301
1302         if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1303                 pr_info("Disabling energy efficiency optimization\n");
1304                 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1305                 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1306         }
1307 }
1308
1309 static int atom_get_min_pstate(void)
1310 {
1311         u64 value;
1312
1313         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1314         return (value >> 8) & 0x7F;
1315 }
1316
1317 static int atom_get_max_pstate(void)
1318 {
1319         u64 value;
1320
1321         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1322         return (value >> 16) & 0x7F;
1323 }
1324
1325 static int atom_get_turbo_pstate(void)
1326 {
1327         u64 value;
1328
1329         rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1330         return value & 0x7F;
1331 }
1332
1333 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1334 {
1335         u64 val;
1336         int32_t vid_fp;
1337         u32 vid;
1338
1339         val = (u64)pstate << 8;
1340         if (global.no_turbo && !global.turbo_disabled)
1341                 val |= (u64)1 << 32;
1342
1343         vid_fp = cpudata->vid.min + mul_fp(
1344                 int_tofp(pstate - cpudata->pstate.min_pstate),
1345                 cpudata->vid.ratio);
1346
1347         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1348         vid = ceiling_fp(vid_fp);
1349
1350         if (pstate > cpudata->pstate.max_pstate)
1351                 vid = cpudata->vid.turbo;
1352
1353         return val | vid;
1354 }
1355
1356 static int silvermont_get_scaling(void)
1357 {
1358         u64 value;
1359         int i;
1360         /* Defined in Table 35-6 from SDM (Sept 2015) */
1361         static int silvermont_freq_table[] = {
1362                 83300, 100000, 133300, 116700, 80000};
1363
1364         rdmsrl(MSR_FSB_FREQ, value);
1365         i = value & 0x7;
1366         WARN_ON(i > 4);
1367
1368         return silvermont_freq_table[i];
1369 }
1370
1371 static int airmont_get_scaling(void)
1372 {
1373         u64 value;
1374         int i;
1375         /* Defined in Table 35-10 from SDM (Sept 2015) */
1376         static int airmont_freq_table[] = {
1377                 83300, 100000, 133300, 116700, 80000,
1378                 93300, 90000, 88900, 87500};
1379
1380         rdmsrl(MSR_FSB_FREQ, value);
1381         i = value & 0xF;
1382         WARN_ON(i > 8);
1383
1384         return airmont_freq_table[i];
1385 }
1386
1387 static void atom_get_vid(struct cpudata *cpudata)
1388 {
1389         u64 value;
1390
1391         rdmsrl(MSR_ATOM_CORE_VIDS, value);
1392         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1393         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1394         cpudata->vid.ratio = div_fp(
1395                 cpudata->vid.max - cpudata->vid.min,
1396                 int_tofp(cpudata->pstate.max_pstate -
1397                         cpudata->pstate.min_pstate));
1398
1399         rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1400         cpudata->vid.turbo = value & 0x7f;
1401 }
1402
1403 static int core_get_min_pstate(void)
1404 {
1405         u64 value;
1406
1407         rdmsrl(MSR_PLATFORM_INFO, value);
1408         return (value >> 40) & 0xFF;
1409 }
1410
1411 static int core_get_max_pstate_physical(void)
1412 {
1413         u64 value;
1414
1415         rdmsrl(MSR_PLATFORM_INFO, value);
1416         return (value >> 8) & 0xFF;
1417 }
1418
1419 static int core_get_tdp_ratio(u64 plat_info)
1420 {
1421         /* Check how many TDP levels present */
1422         if (plat_info & 0x600000000) {
1423                 u64 tdp_ctrl;
1424                 u64 tdp_ratio;
1425                 int tdp_msr;
1426                 int err;
1427
1428                 /* Get the TDP level (0, 1, 2) to get ratios */
1429                 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1430                 if (err)
1431                         return err;
1432
1433                 /* TDP MSR are continuous starting at 0x648 */
1434                 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1435                 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1436                 if (err)
1437                         return err;
1438
1439                 /* For level 1 and 2, bits[23:16] contain the ratio */
1440                 if (tdp_ctrl & 0x03)
1441                         tdp_ratio >>= 16;
1442
1443                 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1444                 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1445
1446                 return (int)tdp_ratio;
1447         }
1448
1449         return -ENXIO;
1450 }
1451
1452 static int core_get_max_pstate(void)
1453 {
1454         u64 tar;
1455         u64 plat_info;
1456         int max_pstate;
1457         int tdp_ratio;
1458         int err;
1459
1460         rdmsrl(MSR_PLATFORM_INFO, plat_info);
1461         max_pstate = (plat_info >> 8) & 0xFF;
1462
1463         tdp_ratio = core_get_tdp_ratio(plat_info);
1464         if (tdp_ratio <= 0)
1465                 return max_pstate;
1466
1467         if (hwp_active) {
1468                 /* Turbo activation ratio is not used on HWP platforms */
1469                 return tdp_ratio;
1470         }
1471
1472         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1473         if (!err) {
1474                 int tar_levels;
1475
1476                 /* Do some sanity checking for safety */
1477                 tar_levels = tar & 0xff;
1478                 if (tdp_ratio - 1 == tar_levels) {
1479                         max_pstate = tar_levels;
1480                         pr_debug("max_pstate=TAC %x\n", max_pstate);
1481                 }
1482         }
1483
1484         return max_pstate;
1485 }
1486
1487 static int core_get_turbo_pstate(void)
1488 {
1489         u64 value;
1490         int nont, ret;
1491
1492         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1493         nont = core_get_max_pstate();
1494         ret = (value) & 255;
1495         if (ret <= nont)
1496                 ret = nont;
1497         return ret;
1498 }
1499
1500 static inline int core_get_scaling(void)
1501 {
1502         return 100000;
1503 }
1504
1505 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1506 {
1507         u64 val;
1508
1509         val = (u64)pstate << 8;
1510         if (global.no_turbo && !global.turbo_disabled)
1511                 val |= (u64)1 << 32;
1512
1513         return val;
1514 }
1515
1516 static int knl_get_turbo_pstate(void)
1517 {
1518         u64 value;
1519         int nont, ret;
1520
1521         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1522         nont = core_get_max_pstate();
1523         ret = (((value) >> 8) & 0xFF);
1524         if (ret <= nont)
1525                 ret = nont;
1526         return ret;
1527 }
1528
1529 static struct cpu_defaults core_params = {
1530         .funcs = {
1531                 .get_max = core_get_max_pstate,
1532                 .get_max_physical = core_get_max_pstate_physical,
1533                 .get_min = core_get_min_pstate,
1534                 .get_turbo = core_get_turbo_pstate,
1535                 .get_scaling = core_get_scaling,
1536                 .get_val = core_get_val,
1537                 .get_target_pstate = get_target_pstate_use_performance,
1538         },
1539 };
1540
1541 static const struct cpu_defaults silvermont_params = {
1542         .funcs = {
1543                 .get_max = atom_get_max_pstate,
1544                 .get_max_physical = atom_get_max_pstate,
1545                 .get_min = atom_get_min_pstate,
1546                 .get_turbo = atom_get_turbo_pstate,
1547                 .get_val = atom_get_val,
1548                 .get_scaling = silvermont_get_scaling,
1549                 .get_vid = atom_get_vid,
1550                 .get_target_pstate = get_target_pstate_use_cpu_load,
1551         },
1552 };
1553
1554 static const struct cpu_defaults airmont_params = {
1555         .funcs = {
1556                 .get_max = atom_get_max_pstate,
1557                 .get_max_physical = atom_get_max_pstate,
1558                 .get_min = atom_get_min_pstate,
1559                 .get_turbo = atom_get_turbo_pstate,
1560                 .get_val = atom_get_val,
1561                 .get_scaling = airmont_get_scaling,
1562                 .get_vid = atom_get_vid,
1563                 .get_target_pstate = get_target_pstate_use_cpu_load,
1564         },
1565 };
1566
1567 static const struct cpu_defaults knl_params = {
1568         .funcs = {
1569                 .get_max = core_get_max_pstate,
1570                 .get_max_physical = core_get_max_pstate_physical,
1571                 .get_min = core_get_min_pstate,
1572                 .get_turbo = knl_get_turbo_pstate,
1573                 .get_scaling = core_get_scaling,
1574                 .get_val = core_get_val,
1575                 .get_target_pstate = get_target_pstate_use_performance,
1576         },
1577 };
1578
1579 static const struct cpu_defaults bxt_params = {
1580         .funcs = {
1581                 .get_max = core_get_max_pstate,
1582                 .get_max_physical = core_get_max_pstate_physical,
1583                 .get_min = core_get_min_pstate,
1584                 .get_turbo = core_get_turbo_pstate,
1585                 .get_scaling = core_get_scaling,
1586                 .get_val = core_get_val,
1587                 .get_target_pstate = get_target_pstate_use_cpu_load,
1588         },
1589 };
1590
1591 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
1592 {
1593         int max_perf = cpu->pstate.turbo_pstate;
1594         int max_perf_adj;
1595         int min_perf;
1596
1597         if (global.no_turbo || global.turbo_disabled)
1598                 max_perf = cpu->pstate.max_pstate;
1599
1600         /*
1601          * performance can be limited by user through sysfs, by cpufreq
1602          * policy, or by cpu specific default values determined through
1603          * experimentation.
1604          */
1605         max_perf_adj = fp_ext_toint(max_perf * cpu->max_perf);
1606         *max = clamp_t(int, max_perf_adj,
1607                         cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
1608
1609         min_perf = fp_ext_toint(max_perf * cpu->min_perf);
1610         *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
1611 }
1612
1613 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1614 {
1615         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1616         cpu->pstate.current_pstate = pstate;
1617         /*
1618          * Generally, there is no guarantee that this code will always run on
1619          * the CPU being updated, so force the register update to run on the
1620          * right CPU.
1621          */
1622         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1623                       pstate_funcs.get_val(cpu, pstate));
1624 }
1625
1626 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1627 {
1628         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1629 }
1630
1631 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1632 {
1633         int min_pstate, max_pstate;
1634
1635         update_turbo_state();
1636         intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate);
1637         intel_pstate_set_pstate(cpu, max_pstate);
1638 }
1639
1640 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1641 {
1642         cpu->pstate.min_pstate = pstate_funcs.get_min();
1643         cpu->pstate.max_pstate = pstate_funcs.get_max();
1644         cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1645         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1646         cpu->pstate.scaling = pstate_funcs.get_scaling();
1647         cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1648         cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1649
1650         if (pstate_funcs.get_vid)
1651                 pstate_funcs.get_vid(cpu);
1652
1653         intel_pstate_set_min_pstate(cpu);
1654 }
1655
1656 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1657 {
1658         struct sample *sample = &cpu->sample;
1659
1660         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1661 }
1662
1663 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1664 {
1665         u64 aperf, mperf;
1666         unsigned long flags;
1667         u64 tsc;
1668
1669         local_irq_save(flags);
1670         rdmsrl(MSR_IA32_APERF, aperf);
1671         rdmsrl(MSR_IA32_MPERF, mperf);
1672         tsc = rdtsc();
1673         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1674                 local_irq_restore(flags);
1675                 return false;
1676         }
1677         local_irq_restore(flags);
1678
1679         cpu->last_sample_time = cpu->sample.time;
1680         cpu->sample.time = time;
1681         cpu->sample.aperf = aperf;
1682         cpu->sample.mperf = mperf;
1683         cpu->sample.tsc =  tsc;
1684         cpu->sample.aperf -= cpu->prev_aperf;
1685         cpu->sample.mperf -= cpu->prev_mperf;
1686         cpu->sample.tsc -= cpu->prev_tsc;
1687
1688         cpu->prev_aperf = aperf;
1689         cpu->prev_mperf = mperf;
1690         cpu->prev_tsc = tsc;
1691         /*
1692          * First time this function is invoked in a given cycle, all of the
1693          * previous sample data fields are equal to zero or stale and they must
1694          * be populated with meaningful numbers for things to work, so assume
1695          * that sample.time will always be reset before setting the utilization
1696          * update hook and make the caller skip the sample then.
1697          */
1698         return !!cpu->last_sample_time;
1699 }
1700
1701 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1702 {
1703         return mul_ext_fp(cpu->sample.core_avg_perf,
1704                           cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1705 }
1706
1707 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1708 {
1709         return mul_ext_fp(cpu->pstate.max_pstate_physical,
1710                           cpu->sample.core_avg_perf);
1711 }
1712
1713 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1714 {
1715         struct sample *sample = &cpu->sample;
1716         int32_t busy_frac, boost;
1717         int target, avg_pstate;
1718
1719         busy_frac = div_fp(sample->mperf, sample->tsc);
1720
1721         boost = cpu->iowait_boost;
1722         cpu->iowait_boost >>= 1;
1723
1724         if (busy_frac < boost)
1725                 busy_frac = boost;
1726
1727         sample->busy_scaled = busy_frac * 100;
1728
1729         target = global.no_turbo || global.turbo_disabled ?
1730                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1731         target += target >> 2;
1732         target = mul_fp(target, busy_frac);
1733         if (target < cpu->pstate.min_pstate)
1734                 target = cpu->pstate.min_pstate;
1735
1736         /*
1737          * If the average P-state during the previous cycle was higher than the
1738          * current target, add 50% of the difference to the target to reduce
1739          * possible performance oscillations and offset possible performance
1740          * loss related to moving the workload from one CPU to another within
1741          * a package/module.
1742          */
1743         avg_pstate = get_avg_pstate(cpu);
1744         if (avg_pstate > target)
1745                 target += (avg_pstate - target) >> 1;
1746
1747         return target;
1748 }
1749
1750 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1751 {
1752         int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1753         u64 duration_ns;
1754
1755         /*
1756          * perf_scaled is the ratio of the average P-state during the last
1757          * sampling period to the P-state requested last time (in percent).
1758          *
1759          * That measures the system's response to the previous P-state
1760          * selection.
1761          */
1762         max_pstate = cpu->pstate.max_pstate_physical;
1763         current_pstate = cpu->pstate.current_pstate;
1764         perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1765                                div_fp(100 * max_pstate, current_pstate));
1766
1767         /*
1768          * Since our utilization update callback will not run unless we are
1769          * in C0, check if the actual elapsed time is significantly greater (3x)
1770          * than our sample interval.  If it is, then we were idle for a long
1771          * enough period of time to adjust our performance metric.
1772          */
1773         duration_ns = cpu->sample.time - cpu->last_sample_time;
1774         if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1775                 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1776                 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1777         } else {
1778                 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1779                 if (sample_ratio < int_tofp(1))
1780                         perf_scaled = 0;
1781         }
1782
1783         cpu->sample.busy_scaled = perf_scaled;
1784         return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1785 }
1786
1787 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1788 {
1789         int max_perf, min_perf;
1790
1791         intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1792         pstate = clamp_t(int, pstate, min_perf, max_perf);
1793         return pstate;
1794 }
1795
1796 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1797 {
1798         if (pstate == cpu->pstate.current_pstate)
1799                 return;
1800
1801         cpu->pstate.current_pstate = pstate;
1802         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1803 }
1804
1805 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1806 {
1807         int from, target_pstate;
1808         struct sample *sample;
1809
1810         from = cpu->pstate.current_pstate;
1811
1812         target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ?
1813                 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu);
1814
1815         update_turbo_state();
1816
1817         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1818         trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1819         intel_pstate_update_pstate(cpu, target_pstate);
1820
1821         sample = &cpu->sample;
1822         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1823                 fp_toint(sample->busy_scaled),
1824                 from,
1825                 cpu->pstate.current_pstate,
1826                 sample->mperf,
1827                 sample->aperf,
1828                 sample->tsc,
1829                 get_avg_frequency(cpu),
1830                 fp_toint(cpu->iowait_boost * 100));
1831 }
1832
1833 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1834                                      unsigned int flags)
1835 {
1836         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1837         u64 delta_ns;
1838
1839         if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) {
1840                 if (flags & SCHED_CPUFREQ_IOWAIT) {
1841                         cpu->iowait_boost = int_tofp(1);
1842                 } else if (cpu->iowait_boost) {
1843                         /* Clear iowait_boost if the CPU may have been idle. */
1844                         delta_ns = time - cpu->last_update;
1845                         if (delta_ns > TICK_NSEC)
1846                                 cpu->iowait_boost = 0;
1847                 }
1848                 cpu->last_update = time;
1849         }
1850
1851         delta_ns = time - cpu->sample.time;
1852         if ((s64)delta_ns >= pid_params.sample_rate_ns) {
1853                 bool sample_taken = intel_pstate_sample(cpu, time);
1854
1855                 if (sample_taken) {
1856                         intel_pstate_calc_avg_perf(cpu);
1857                         if (!hwp_active)
1858                                 intel_pstate_adjust_busy_pstate(cpu);
1859                 }
1860         }
1861 }
1862
1863 #define ICPU(model, policy) \
1864         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1865                         (unsigned long)&policy }
1866
1867 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1868         ICPU(INTEL_FAM6_SANDYBRIDGE,            core_params),
1869         ICPU(INTEL_FAM6_SANDYBRIDGE_X,          core_params),
1870         ICPU(INTEL_FAM6_ATOM_SILVERMONT1,       silvermont_params),
1871         ICPU(INTEL_FAM6_IVYBRIDGE,              core_params),
1872         ICPU(INTEL_FAM6_HASWELL_CORE,           core_params),
1873         ICPU(INTEL_FAM6_BROADWELL_CORE,         core_params),
1874         ICPU(INTEL_FAM6_IVYBRIDGE_X,            core_params),
1875         ICPU(INTEL_FAM6_HASWELL_X,              core_params),
1876         ICPU(INTEL_FAM6_HASWELL_ULT,            core_params),
1877         ICPU(INTEL_FAM6_HASWELL_GT3E,           core_params),
1878         ICPU(INTEL_FAM6_BROADWELL_GT3E,         core_params),
1879         ICPU(INTEL_FAM6_ATOM_AIRMONT,           airmont_params),
1880         ICPU(INTEL_FAM6_SKYLAKE_MOBILE,         core_params),
1881         ICPU(INTEL_FAM6_BROADWELL_X,            core_params),
1882         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP,        core_params),
1883         ICPU(INTEL_FAM6_BROADWELL_XEON_D,       core_params),
1884         ICPU(INTEL_FAM6_XEON_PHI_KNL,           knl_params),
1885         ICPU(INTEL_FAM6_XEON_PHI_KNM,           knl_params),
1886         ICPU(INTEL_FAM6_ATOM_GOLDMONT,          bxt_params),
1887         {}
1888 };
1889 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1890
1891 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1892         ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1893         ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1894         ICPU(INTEL_FAM6_SKYLAKE_X, core_params),
1895         {}
1896 };
1897
1898 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1899         ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_params),
1900         {}
1901 };
1902
1903 static int intel_pstate_init_cpu(unsigned int cpunum)
1904 {
1905         struct cpudata *cpu;
1906
1907         cpu = all_cpu_data[cpunum];
1908
1909         if (!cpu) {
1910                 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1911                 if (!cpu)
1912                         return -ENOMEM;
1913
1914                 all_cpu_data[cpunum] = cpu;
1915
1916                 cpu->epp_default = -EINVAL;
1917                 cpu->epp_powersave = -EINVAL;
1918                 cpu->epp_saved = -EINVAL;
1919         }
1920
1921         cpu = all_cpu_data[cpunum];
1922
1923         cpu->cpu = cpunum;
1924
1925         if (hwp_active) {
1926                 const struct x86_cpu_id *id;
1927
1928                 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1929                 if (id)
1930                         intel_pstate_disable_ee(cpunum);
1931
1932                 intel_pstate_hwp_enable(cpu);
1933                 pid_params.sample_rate_ms = 50;
1934                 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
1935         }
1936
1937         intel_pstate_get_cpu_pstates(cpu);
1938
1939         intel_pstate_busy_pid_reset(cpu);
1940
1941         pr_debug("controlling: cpu %d\n", cpunum);
1942
1943         return 0;
1944 }
1945
1946 static unsigned int intel_pstate_get(unsigned int cpu_num)
1947 {
1948         struct cpudata *cpu = all_cpu_data[cpu_num];
1949
1950         return cpu ? get_avg_frequency(cpu) : 0;
1951 }
1952
1953 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1954 {
1955         struct cpudata *cpu = all_cpu_data[cpu_num];
1956
1957         if (cpu->update_util_set)
1958                 return;
1959
1960         /* Prevent intel_pstate_update_util() from using stale data. */
1961         cpu->sample.time = 0;
1962         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1963                                      intel_pstate_update_util);
1964         cpu->update_util_set = true;
1965 }
1966
1967 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1968 {
1969         struct cpudata *cpu_data = all_cpu_data[cpu];
1970
1971         if (!cpu_data->update_util_set)
1972                 return;
1973
1974         cpufreq_remove_update_util_hook(cpu);
1975         cpu_data->update_util_set = false;
1976         synchronize_sched();
1977 }
1978
1979 static int intel_pstate_get_max_freq(struct cpudata *cpu)
1980 {
1981         return global.turbo_disabled || global.no_turbo ?
1982                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1983 }
1984
1985 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1986                                             struct cpudata *cpu)
1987 {
1988         int max_freq = intel_pstate_get_max_freq(cpu);
1989         int32_t max_policy_perf, min_policy_perf;
1990
1991         max_policy_perf = div_ext_fp(policy->max, max_freq);
1992         max_policy_perf = clamp_t(int32_t, max_policy_perf, 0, int_ext_tofp(1));
1993         if (policy->max == policy->min) {
1994                 min_policy_perf = max_policy_perf;
1995         } else {
1996                 min_policy_perf = div_ext_fp(policy->min, max_freq);
1997                 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1998                                           0, max_policy_perf);
1999         }
2000
2001         /* Normalize user input to [min_perf, max_perf] */
2002         if (per_cpu_limits) {
2003                 cpu->min_perf = min_policy_perf;
2004                 cpu->max_perf = max_policy_perf;
2005         } else {
2006                 int32_t global_min, global_max;
2007
2008                 /* Global limits are in percent of the maximum turbo P-state. */
2009                 global_max = percent_ext_fp(global.max_perf_pct);
2010                 global_min = percent_ext_fp(global.min_perf_pct);
2011                 if (max_freq != cpu->pstate.turbo_freq) {
2012                         int32_t turbo_factor;
2013
2014                         turbo_factor = div_ext_fp(cpu->pstate.turbo_pstate,
2015                                                   cpu->pstate.max_pstate);
2016                         global_min = mul_ext_fp(global_min, turbo_factor);
2017                         global_max = mul_ext_fp(global_max, turbo_factor);
2018                 }
2019                 global_min = clamp_t(int32_t, global_min, 0, global_max);
2020
2021                 cpu->min_perf = max(min_policy_perf, global_min);
2022                 cpu->min_perf = min(cpu->min_perf, max_policy_perf);
2023                 cpu->max_perf = min(max_policy_perf, global_max);
2024                 cpu->max_perf = max(min_policy_perf, cpu->max_perf);
2025
2026                 /* Make sure min_perf <= max_perf */
2027                 cpu->min_perf = min(cpu->min_perf, cpu->max_perf);
2028         }
2029
2030         cpu->max_perf = round_up(cpu->max_perf, EXT_FRAC_BITS);
2031         cpu->min_perf = round_up(cpu->min_perf, EXT_FRAC_BITS);
2032
2033         pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
2034                  fp_ext_toint(cpu->max_perf * 100),
2035                  fp_ext_toint(cpu->min_perf * 100));
2036 }
2037
2038 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2039 {
2040         struct cpudata *cpu;
2041
2042         if (!policy->cpuinfo.max_freq)
2043                 return -ENODEV;
2044
2045         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2046                  policy->cpuinfo.max_freq, policy->max);
2047
2048         cpu = all_cpu_data[policy->cpu];
2049         cpu->policy = policy->policy;
2050
2051         mutex_lock(&intel_pstate_limits_lock);
2052
2053         intel_pstate_update_perf_limits(policy, cpu);
2054
2055         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2056                 /*
2057                  * NOHZ_FULL CPUs need this as the governor callback may not
2058                  * be invoked on them.
2059                  */
2060                 intel_pstate_clear_update_util_hook(policy->cpu);
2061                 intel_pstate_max_within_limits(cpu);
2062         }
2063
2064         intel_pstate_set_update_util_hook(policy->cpu);
2065
2066         if (hwp_active)
2067                 intel_pstate_hwp_set(policy);
2068
2069         mutex_unlock(&intel_pstate_limits_lock);
2070
2071         return 0;
2072 }
2073
2074 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
2075                                          struct cpudata *cpu)
2076 {
2077         if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2078             policy->max < policy->cpuinfo.max_freq &&
2079             policy->max > cpu->pstate.max_freq) {
2080                 pr_debug("policy->max > max non turbo frequency\n");
2081                 policy->max = policy->cpuinfo.max_freq;
2082         }
2083 }
2084
2085 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2086 {
2087         struct cpudata *cpu = all_cpu_data[policy->cpu];
2088
2089         update_turbo_state();
2090         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2091                                      intel_pstate_get_max_freq(cpu));
2092
2093         if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2094             policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2095                 return -EINVAL;
2096
2097         intel_pstate_adjust_policy_max(policy, cpu);
2098
2099         return 0;
2100 }
2101
2102 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2103 {
2104         intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2105 }
2106
2107 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2108 {
2109         pr_debug("CPU %d exiting\n", policy->cpu);
2110
2111         intel_pstate_clear_update_util_hook(policy->cpu);
2112         if (hwp_active)
2113                 intel_pstate_hwp_save_state(policy);
2114         else
2115                 intel_cpufreq_stop_cpu(policy);
2116 }
2117
2118 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2119 {
2120         intel_pstate_exit_perf_limits(policy);
2121
2122         policy->fast_switch_possible = false;
2123
2124         return 0;
2125 }
2126
2127 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2128 {
2129         struct cpudata *cpu;
2130         int rc;
2131
2132         rc = intel_pstate_init_cpu(policy->cpu);
2133         if (rc)
2134                 return rc;
2135
2136         cpu = all_cpu_data[policy->cpu];
2137
2138         cpu->max_perf = int_ext_tofp(1);
2139         cpu->min_perf = 0;
2140
2141         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2142         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2143
2144         /* cpuinfo and default policy values */
2145         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2146         update_turbo_state();
2147         policy->cpuinfo.max_freq = global.turbo_disabled ?
2148                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2149         policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2150
2151         intel_pstate_init_acpi_perf_limits(policy);
2152         cpumask_set_cpu(policy->cpu, policy->cpus);
2153
2154         policy->fast_switch_possible = true;
2155
2156         return 0;
2157 }
2158
2159 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2160 {
2161         int ret = __intel_pstate_cpu_init(policy);
2162
2163         if (ret)
2164                 return ret;
2165
2166         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2167         if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
2168                 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2169         else
2170                 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2171
2172         return 0;
2173 }
2174
2175 static struct cpufreq_driver intel_pstate = {
2176         .flags          = CPUFREQ_CONST_LOOPS,
2177         .verify         = intel_pstate_verify_policy,
2178         .setpolicy      = intel_pstate_set_policy,
2179         .suspend        = intel_pstate_hwp_save_state,
2180         .resume         = intel_pstate_resume,
2181         .get            = intel_pstate_get,
2182         .init           = intel_pstate_cpu_init,
2183         .exit           = intel_pstate_cpu_exit,
2184         .stop_cpu       = intel_pstate_stop_cpu,
2185         .name           = "intel_pstate",
2186 };
2187
2188 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2189 {
2190         struct cpudata *cpu = all_cpu_data[policy->cpu];
2191
2192         update_turbo_state();
2193         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2194                                      intel_pstate_get_max_freq(cpu));
2195
2196         intel_pstate_adjust_policy_max(policy, cpu);
2197
2198         intel_pstate_update_perf_limits(policy, cpu);
2199
2200         return 0;
2201 }
2202
2203 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2204                                 unsigned int target_freq,
2205                                 unsigned int relation)
2206 {
2207         struct cpudata *cpu = all_cpu_data[policy->cpu];
2208         struct cpufreq_freqs freqs;
2209         int target_pstate;
2210
2211         update_turbo_state();
2212
2213         freqs.old = policy->cur;
2214         freqs.new = target_freq;
2215
2216         cpufreq_freq_transition_begin(policy, &freqs);
2217         switch (relation) {
2218         case CPUFREQ_RELATION_L:
2219                 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2220                 break;
2221         case CPUFREQ_RELATION_H:
2222                 target_pstate = freqs.new / cpu->pstate.scaling;
2223                 break;
2224         default:
2225                 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2226                 break;
2227         }
2228         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2229         if (target_pstate != cpu->pstate.current_pstate) {
2230                 cpu->pstate.current_pstate = target_pstate;
2231                 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2232                               pstate_funcs.get_val(cpu, target_pstate));
2233         }
2234         freqs.new = target_pstate * cpu->pstate.scaling;
2235         cpufreq_freq_transition_end(policy, &freqs, false);
2236
2237         return 0;
2238 }
2239
2240 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2241                                               unsigned int target_freq)
2242 {
2243         struct cpudata *cpu = all_cpu_data[policy->cpu];
2244         int target_pstate;
2245
2246         update_turbo_state();
2247
2248         target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2249         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2250         intel_pstate_update_pstate(cpu, target_pstate);
2251         return target_pstate * cpu->pstate.scaling;
2252 }
2253
2254 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2255 {
2256         int ret = __intel_pstate_cpu_init(policy);
2257
2258         if (ret)
2259                 return ret;
2260
2261         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2262         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2263         policy->cur = policy->cpuinfo.min_freq;
2264
2265         return 0;
2266 }
2267
2268 static struct cpufreq_driver intel_cpufreq = {
2269         .flags          = CPUFREQ_CONST_LOOPS,
2270         .verify         = intel_cpufreq_verify_policy,
2271         .target         = intel_cpufreq_target,
2272         .fast_switch    = intel_cpufreq_fast_switch,
2273         .init           = intel_cpufreq_cpu_init,
2274         .exit           = intel_pstate_cpu_exit,
2275         .stop_cpu       = intel_cpufreq_stop_cpu,
2276         .name           = "intel_cpufreq",
2277 };
2278
2279 static struct cpufreq_driver *intel_pstate_driver = &intel_pstate;
2280
2281 static void intel_pstate_driver_cleanup(void)
2282 {
2283         unsigned int cpu;
2284
2285         get_online_cpus();
2286         for_each_online_cpu(cpu) {
2287                 if (all_cpu_data[cpu]) {
2288                         if (intel_pstate_driver == &intel_pstate)
2289                                 intel_pstate_clear_update_util_hook(cpu);
2290
2291                         kfree(all_cpu_data[cpu]);
2292                         all_cpu_data[cpu] = NULL;
2293                 }
2294         }
2295         put_online_cpus();
2296 }
2297
2298 static int intel_pstate_register_driver(void)
2299 {
2300         int ret;
2301
2302         memset(&global, 0, sizeof(global));
2303         global.max_perf_pct = 100;
2304
2305         ret = cpufreq_register_driver(intel_pstate_driver);
2306         if (ret) {
2307                 intel_pstate_driver_cleanup();
2308                 return ret;
2309         }
2310
2311         global.min_perf_pct = min_perf_pct_min();
2312
2313         mutex_lock(&intel_pstate_limits_lock);
2314         driver_registered = true;
2315         mutex_unlock(&intel_pstate_limits_lock);
2316
2317         if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2318             pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2319                 intel_pstate_debug_expose_params();
2320
2321         return 0;
2322 }
2323
2324 static int intel_pstate_unregister_driver(void)
2325 {
2326         if (hwp_active)
2327                 return -EBUSY;
2328
2329         if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2330             pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2331                 intel_pstate_debug_hide_params();
2332
2333         mutex_lock(&intel_pstate_limits_lock);
2334         driver_registered = false;
2335         mutex_unlock(&intel_pstate_limits_lock);
2336
2337         cpufreq_unregister_driver(intel_pstate_driver);
2338         intel_pstate_driver_cleanup();
2339
2340         return 0;
2341 }
2342
2343 static ssize_t intel_pstate_show_status(char *buf)
2344 {
2345         if (!driver_registered)
2346                 return sprintf(buf, "off\n");
2347
2348         return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2349                                         "active" : "passive");
2350 }
2351
2352 static int intel_pstate_update_status(const char *buf, size_t size)
2353 {
2354         int ret;
2355
2356         if (size == 3 && !strncmp(buf, "off", size))
2357                 return driver_registered ?
2358                         intel_pstate_unregister_driver() : -EINVAL;
2359
2360         if (size == 6 && !strncmp(buf, "active", size)) {
2361                 if (driver_registered) {
2362                         if (intel_pstate_driver == &intel_pstate)
2363                                 return 0;
2364
2365                         ret = intel_pstate_unregister_driver();
2366                         if (ret)
2367                                 return ret;
2368                 }
2369
2370                 intel_pstate_driver = &intel_pstate;
2371                 return intel_pstate_register_driver();
2372         }
2373
2374         if (size == 7 && !strncmp(buf, "passive", size)) {
2375                 if (driver_registered) {
2376                         if (intel_pstate_driver != &intel_pstate)
2377                                 return 0;
2378
2379                         ret = intel_pstate_unregister_driver();
2380                         if (ret)
2381                                 return ret;
2382                 }
2383
2384                 intel_pstate_driver = &intel_cpufreq;
2385                 return intel_pstate_register_driver();
2386         }
2387
2388         return -EINVAL;
2389 }
2390
2391 static int no_load __initdata;
2392 static int no_hwp __initdata;
2393 static int hwp_only __initdata;
2394 static unsigned int force_load __initdata;
2395
2396 static int __init intel_pstate_msrs_not_valid(void)
2397 {
2398         if (!pstate_funcs.get_max() ||
2399             !pstate_funcs.get_min() ||
2400             !pstate_funcs.get_turbo())
2401                 return -ENODEV;
2402
2403         return 0;
2404 }
2405
2406 #ifdef CONFIG_ACPI
2407 static void intel_pstate_use_acpi_profile(void)
2408 {
2409         switch (acpi_gbl_FADT.preferred_profile) {
2410         case PM_MOBILE:
2411         case PM_TABLET:
2412         case PM_APPLIANCE_PC:
2413         case PM_DESKTOP:
2414         case PM_WORKSTATION:
2415                 pstate_funcs.get_target_pstate =
2416                                 get_target_pstate_use_cpu_load;
2417         }
2418 }
2419 #else
2420 static void intel_pstate_use_acpi_profile(void)
2421 {
2422 }
2423 #endif
2424
2425 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2426 {
2427         pstate_funcs.get_max   = funcs->get_max;
2428         pstate_funcs.get_max_physical = funcs->get_max_physical;
2429         pstate_funcs.get_min   = funcs->get_min;
2430         pstate_funcs.get_turbo = funcs->get_turbo;
2431         pstate_funcs.get_scaling = funcs->get_scaling;
2432         pstate_funcs.get_val   = funcs->get_val;
2433         pstate_funcs.get_vid   = funcs->get_vid;
2434         pstate_funcs.get_target_pstate = funcs->get_target_pstate;
2435
2436         intel_pstate_use_acpi_profile();
2437 }
2438
2439 #ifdef CONFIG_ACPI
2440
2441 static bool __init intel_pstate_no_acpi_pss(void)
2442 {
2443         int i;
2444
2445         for_each_possible_cpu(i) {
2446                 acpi_status status;
2447                 union acpi_object *pss;
2448                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2449                 struct acpi_processor *pr = per_cpu(processors, i);
2450
2451                 if (!pr)
2452                         continue;
2453
2454                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2455                 if (ACPI_FAILURE(status))
2456                         continue;
2457
2458                 pss = buffer.pointer;
2459                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2460                         kfree(pss);
2461                         return false;
2462                 }
2463
2464                 kfree(pss);
2465         }
2466
2467         return true;
2468 }
2469
2470 static bool __init intel_pstate_has_acpi_ppc(void)
2471 {
2472         int i;
2473
2474         for_each_possible_cpu(i) {
2475                 struct acpi_processor *pr = per_cpu(processors, i);
2476
2477                 if (!pr)
2478                         continue;
2479                 if (acpi_has_method(pr->handle, "_PPC"))
2480                         return true;
2481         }
2482         return false;
2483 }
2484
2485 enum {
2486         PSS,
2487         PPC,
2488 };
2489
2490 struct hw_vendor_info {
2491         u16  valid;
2492         char oem_id[ACPI_OEM_ID_SIZE];
2493         char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
2494         int  oem_pwr_table;
2495 };
2496
2497 /* Hardware vendor-specific info that has its own power management modes */
2498 static struct hw_vendor_info vendor_info[] __initdata = {
2499         {1, "HP    ", "ProLiant", PSS},
2500         {1, "ORACLE", "X4-2    ", PPC},
2501         {1, "ORACLE", "X4-2L   ", PPC},
2502         {1, "ORACLE", "X4-2B   ", PPC},
2503         {1, "ORACLE", "X3-2    ", PPC},
2504         {1, "ORACLE", "X3-2L   ", PPC},
2505         {1, "ORACLE", "X3-2B   ", PPC},
2506         {1, "ORACLE", "X4470M2 ", PPC},
2507         {1, "ORACLE", "X4270M3 ", PPC},
2508         {1, "ORACLE", "X4270M2 ", PPC},
2509         {1, "ORACLE", "X4170M2 ", PPC},
2510         {1, "ORACLE", "X4170 M3", PPC},
2511         {1, "ORACLE", "X4275 M3", PPC},
2512         {1, "ORACLE", "X6-2    ", PPC},
2513         {1, "ORACLE", "Sudbury ", PPC},
2514         {0, "", ""},
2515 };
2516
2517 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2518 {
2519         struct acpi_table_header hdr;
2520         struct hw_vendor_info *v_info;
2521         const struct x86_cpu_id *id;
2522         u64 misc_pwr;
2523
2524         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2525         if (id) {
2526                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2527                 if ( misc_pwr & (1 << 8))
2528                         return true;
2529         }
2530
2531         if (acpi_disabled ||
2532             ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
2533                 return false;
2534
2535         for (v_info = vendor_info; v_info->valid; v_info++) {
2536                 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
2537                         !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2538                                                 ACPI_OEM_TABLE_ID_SIZE))
2539                         switch (v_info->oem_pwr_table) {
2540                         case PSS:
2541                                 return intel_pstate_no_acpi_pss();
2542                         case PPC:
2543                                 return intel_pstate_has_acpi_ppc() &&
2544                                         (!force_load);
2545                         }
2546         }
2547
2548         return false;
2549 }
2550
2551 static void intel_pstate_request_control_from_smm(void)
2552 {
2553         /*
2554          * It may be unsafe to request P-states control from SMM if _PPC support
2555          * has not been enabled.
2556          */
2557         if (acpi_ppc)
2558                 acpi_processor_pstate_control();
2559 }
2560 #else /* CONFIG_ACPI not enabled */
2561 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2562 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2563 static inline void intel_pstate_request_control_from_smm(void) {}
2564 #endif /* CONFIG_ACPI */
2565
2566 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2567         { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2568         {}
2569 };
2570
2571 static int __init intel_pstate_init(void)
2572 {
2573         int rc;
2574
2575         if (no_load)
2576                 return -ENODEV;
2577
2578         if (x86_match_cpu(hwp_support_ids)) {
2579                 copy_cpu_funcs(&core_params.funcs);
2580                 if (no_hwp) {
2581                         pstate_funcs.get_target_pstate = get_target_pstate_use_cpu_load;
2582                 } else {
2583                         hwp_active++;
2584                         intel_pstate.attr = hwp_cpufreq_attrs;
2585                         goto hwp_cpu_matched;
2586                 }
2587         } else {
2588                 const struct x86_cpu_id *id;
2589                 struct cpu_defaults *cpu_def;
2590
2591                 id = x86_match_cpu(intel_pstate_cpu_ids);
2592                 if (!id)
2593                         return -ENODEV;
2594
2595                 cpu_def = (struct cpu_defaults *)id->driver_data;
2596                 copy_cpu_funcs(&cpu_def->funcs);
2597         }
2598
2599         if (intel_pstate_msrs_not_valid())
2600                 return -ENODEV;
2601
2602 hwp_cpu_matched:
2603         /*
2604          * The Intel pstate driver will be ignored if the platform
2605          * firmware has its own power management modes.
2606          */
2607         if (intel_pstate_platform_pwr_mgmt_exists())
2608                 return -ENODEV;
2609
2610         if (!hwp_active && hwp_only)
2611                 return -ENOTSUPP;
2612
2613         pr_info("Intel P-state driver initializing\n");
2614
2615         all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2616         if (!all_cpu_data)
2617                 return -ENOMEM;
2618
2619         intel_pstate_request_control_from_smm();
2620
2621         intel_pstate_sysfs_expose_params();
2622
2623         mutex_lock(&intel_pstate_driver_lock);
2624         rc = intel_pstate_register_driver();
2625         mutex_unlock(&intel_pstate_driver_lock);
2626         if (rc)
2627                 return rc;
2628
2629         if (hwp_active)
2630                 pr_info("HWP enabled\n");
2631
2632         return 0;
2633 }
2634 device_initcall(intel_pstate_init);
2635
2636 static int __init intel_pstate_setup(char *str)
2637 {
2638         if (!str)
2639                 return -EINVAL;
2640
2641         if (!strcmp(str, "disable")) {
2642                 no_load = 1;
2643         } else if (!strcmp(str, "passive")) {
2644                 pr_info("Passive mode enabled\n");
2645                 intel_pstate_driver = &intel_cpufreq;
2646                 no_hwp = 1;
2647         }
2648         if (!strcmp(str, "no_hwp")) {
2649                 pr_info("HWP disabled\n");
2650                 no_hwp = 1;
2651         }
2652         if (!strcmp(str, "force"))
2653                 force_load = 1;
2654         if (!strcmp(str, "hwp_only"))
2655                 hwp_only = 1;
2656         if (!strcmp(str, "per_cpu_perf_limits"))
2657                 per_cpu_limits = true;
2658
2659 #ifdef CONFIG_ACPI
2660         if (!strcmp(str, "support_acpi_ppc"))
2661                 acpi_ppc = true;
2662 #endif
2663
2664         return 0;
2665 }
2666 early_param("intel_pstate", intel_pstate_setup);
2667
2668 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2669 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2670 MODULE_LICENSE("GPL");