2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched/cpufreq.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
34 #include <asm/div64.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
40 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
43 #include <acpi/processor.h>
44 #include <acpi/cppc_acpi.h>
48 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
49 #define fp_toint(X) ((X) >> FRAC_BITS)
52 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
53 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
54 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
56 static inline int32_t mul_fp(int32_t x, int32_t y)
58 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
61 static inline int32_t div_fp(s64 x, s64 y)
63 return div64_s64((int64_t)x << FRAC_BITS, y);
66 static inline int ceiling_fp(int32_t x)
71 mask = (1 << FRAC_BITS) - 1;
77 static inline u64 mul_ext_fp(u64 x, u64 y)
79 return (x * y) >> EXT_FRAC_BITS;
82 static inline u64 div_ext_fp(u64 x, u64 y)
84 return div64_u64(x << EXT_FRAC_BITS, y);
87 static inline int32_t percent_ext_fp(int percent)
89 return div_ext_fp(percent, 100);
93 * struct sample - Store performance sample
94 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
95 * performance during last sample period
96 * @busy_scaled: Scaled busy value which is used to calculate next
97 * P state. This can be different than core_avg_perf
98 * to account for cpu idle period
99 * @aperf: Difference of actual performance frequency clock count
100 * read from APERF MSR between last and current sample
101 * @mperf: Difference of maximum performance frequency clock count
102 * read from MPERF MSR between last and current sample
103 * @tsc: Difference of time stamp counter between last and
105 * @time: Current time from scheduler
107 * This structure is used in the cpudata structure to store performance sample
108 * data for choosing next P State.
111 int32_t core_avg_perf;
120 * struct pstate_data - Store P state data
121 * @current_pstate: Current requested P state
122 * @min_pstate: Min P state possible for this platform
123 * @max_pstate: Max P state possible for this platform
124 * @max_pstate_physical:This is physical Max P state for a processor
125 * This can be higher than the max_pstate which can
126 * be limited by platform thermal design power limits
127 * @scaling: Scaling factor to convert frequency to cpufreq
129 * @turbo_pstate: Max Turbo P state possible for this platform
130 * @max_freq: @max_pstate frequency in cpufreq units
131 * @turbo_freq: @turbo_pstate frequency in cpufreq units
133 * Stores the per cpu model P state limits and current P state.
139 int max_pstate_physical;
142 unsigned int max_freq;
143 unsigned int turbo_freq;
147 * struct vid_data - Stores voltage information data
148 * @min: VID data for this platform corresponding to
150 * @max: VID data corresponding to the highest P State.
151 * @turbo: VID data for turbo P state
152 * @ratio: Ratio of (vid max - vid min) /
153 * (max P state - Min P State)
155 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
156 * This data is used in Atom platforms, where in addition to target P state,
157 * the voltage data needs to be specified to select next P State.
167 * struct _pid - Stores PID data
168 * @setpoint: Target set point for busyness or performance
169 * @integral: Storage for accumulated error values
170 * @p_gain: PID proportional gain
171 * @i_gain: PID integral gain
172 * @d_gain: PID derivative gain
173 * @deadband: PID deadband
174 * @last_err: Last error storage for integral part of PID calculation
176 * Stores PID coefficients and last error for PID controller.
189 * struct perf_limits - Store user and policy limits
190 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct
191 * This value is used to limit max pstate
192 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct
193 * This value is used to limit min pstate
195 * Storage for policy defined limits.
203 * struct global_params - Global parameters, mostly tunable via sysfs.
204 * @no_turbo: Whether or not to use turbo P-states.
205 * @turbo_disabled: Whethet or not turbo P-states are available at all,
206 * based on the MSR_IA32_MISC_ENABLE value and whether or
207 * not the maximum reported turbo P-state is different from
208 * the maximum reported non-turbo one.
209 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
211 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
214 struct global_params {
222 * struct cpudata - Per CPU instance data storage
223 * @cpu: CPU number for this instance data
224 * @policy: CPUFreq policy value
225 * @update_util: CPUFreq utility callback information
226 * @update_util_set: CPUFreq utility callback is set
227 * @iowait_boost: iowait-related boost fraction
228 * @last_update: Time of the last update.
229 * @pstate: Stores P state limits for this CPU
230 * @vid: Stores VID limits for this CPU
231 * @pid: Stores PID parameters for this CPU
232 * @last_sample_time: Last Sample time
233 * @prev_aperf: Last APERF value read from APERF MSR
234 * @prev_mperf: Last MPERF value read from MPERF MSR
235 * @prev_tsc: Last timestamp counter (TSC) value
236 * @prev_cummulative_iowait: IO Wait time difference from last and
238 * @sample: Storage for storing last Sample data
239 * @perf_limits: Capacity limits unique to this CPU
240 * @acpi_perf_data: Stores ACPI perf information read from _PSS
241 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
242 * @epp_powersave: Last saved HWP energy performance preference
243 * (EPP) or energy performance bias (EPB),
244 * when policy switched to performance
245 * @epp_policy: Last saved policy used to set EPP/EPB
246 * @epp_default: Power on default HWP energy performance
248 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
251 * This structure stores per CPU instance data for all CPUs.
257 struct update_util_data update_util;
258 bool update_util_set;
260 struct pstate_data pstate;
265 u64 last_sample_time;
269 u64 prev_cummulative_iowait;
270 struct sample sample;
271 struct perf_limits perf_limits;
273 struct acpi_processor_performance acpi_perf_data;
274 bool valid_pss_table;
276 unsigned int iowait_boost;
283 static struct cpudata **all_cpu_data;
286 * struct pstate_adjust_policy - Stores static PID configuration data
287 * @sample_rate_ms: PID calculation sample rate in ms
288 * @sample_rate_ns: Sample rate calculation in ns
289 * @deadband: PID deadband
290 * @setpoint: PID Setpoint
291 * @p_gain_pct: PID proportional gain
292 * @i_gain_pct: PID integral gain
293 * @d_gain_pct: PID derivative gain
295 * Stores per CPU model static PID configuration data.
297 struct pstate_adjust_policy {
308 * struct pstate_funcs - Per CPU model specific callbacks
309 * @get_max: Callback to get maximum non turbo effective P state
310 * @get_max_physical: Callback to get maximum non turbo physical P state
311 * @get_min: Callback to get minimum P state
312 * @get_turbo: Callback to get turbo P state
313 * @get_scaling: Callback to get frequency scaling factor
314 * @get_val: Callback to convert P state to actual MSR write value
315 * @get_vid: Callback to get VID data for Atom platforms
316 * @get_target_pstate: Callback to a function to calculate next P state to use
318 * Core and Atom CPU models have different way to get P State limits. This
319 * structure is used to store those callbacks.
321 struct pstate_funcs {
322 int (*get_max)(void);
323 int (*get_max_physical)(void);
324 int (*get_min)(void);
325 int (*get_turbo)(void);
326 int (*get_scaling)(void);
327 u64 (*get_val)(struct cpudata*, int pstate);
328 void (*get_vid)(struct cpudata *);
329 int32_t (*get_target_pstate)(struct cpudata *);
333 * struct cpu_defaults- Per CPU model default config data
334 * @pid_policy: PID config data
335 * @funcs: Callback function data
337 struct cpu_defaults {
338 struct pstate_adjust_policy pid_policy;
339 struct pstate_funcs funcs;
342 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
343 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
345 static struct pstate_adjust_policy pid_params __read_mostly;
346 static struct pstate_funcs pstate_funcs __read_mostly;
347 static int hwp_active __read_mostly;
348 static bool per_cpu_limits __read_mostly;
350 static bool driver_registered __read_mostly;
353 static bool acpi_ppc;
356 static struct global_params global;
358 static DEFINE_MUTEX(intel_pstate_driver_lock);
359 static DEFINE_MUTEX(intel_pstate_limits_lock);
363 static bool intel_pstate_get_ppc_enable_status(void)
365 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
366 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
372 #ifdef CONFIG_ACPI_CPPC_LIB
374 /* The work item is needed to avoid CPU hotplug locking issues */
375 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
377 sched_set_itmt_support();
380 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
382 static void intel_pstate_set_itmt_prio(int cpu)
384 struct cppc_perf_caps cppc_perf;
385 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
388 ret = cppc_get_perf_caps(cpu, &cppc_perf);
393 * The priorities can be set regardless of whether or not
394 * sched_set_itmt_support(true) has been called and it is valid to
395 * update them at any time after it has been called.
397 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
399 if (max_highest_perf <= min_highest_perf) {
400 if (cppc_perf.highest_perf > max_highest_perf)
401 max_highest_perf = cppc_perf.highest_perf;
403 if (cppc_perf.highest_perf < min_highest_perf)
404 min_highest_perf = cppc_perf.highest_perf;
406 if (max_highest_perf > min_highest_perf) {
408 * This code can be run during CPU online under the
409 * CPU hotplug locks, so sched_set_itmt_support()
410 * cannot be called from here. Queue up a work item
413 schedule_work(&sched_itmt_work);
418 static void intel_pstate_set_itmt_prio(int cpu)
423 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
430 intel_pstate_set_itmt_prio(policy->cpu);
434 if (!intel_pstate_get_ppc_enable_status())
437 cpu = all_cpu_data[policy->cpu];
439 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
445 * Check if the control value in _PSS is for PERF_CTL MSR, which should
446 * guarantee that the states returned by it map to the states in our
449 if (cpu->acpi_perf_data.control_register.space_id !=
450 ACPI_ADR_SPACE_FIXED_HARDWARE)
454 * If there is only one entry _PSS, simply ignore _PSS and continue as
455 * usual without taking _PSS into account
457 if (cpu->acpi_perf_data.state_count < 2)
460 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
461 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
462 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
463 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
464 (u32) cpu->acpi_perf_data.states[i].core_frequency,
465 (u32) cpu->acpi_perf_data.states[i].power,
466 (u32) cpu->acpi_perf_data.states[i].control);
470 * The _PSS table doesn't contain whole turbo frequency range.
471 * This just contains +1 MHZ above the max non turbo frequency,
472 * with control value corresponding to max turbo ratio. But
473 * when cpufreq set policy is called, it will call with this
474 * max frequency, which will cause a reduced performance as
475 * this driver uses real max turbo frequency as the max
476 * frequency. So correct this frequency in _PSS table to
477 * correct max turbo frequency based on the turbo state.
478 * Also need to convert to MHz as _PSS freq is in MHz.
480 if (!global.turbo_disabled)
481 cpu->acpi_perf_data.states[0].core_frequency =
482 policy->cpuinfo.max_freq / 1000;
483 cpu->valid_pss_table = true;
484 pr_debug("_PPC limits will be enforced\n");
489 cpu->valid_pss_table = false;
490 acpi_processor_unregister_performance(policy->cpu);
493 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
497 cpu = all_cpu_data[policy->cpu];
498 if (!cpu->valid_pss_table)
501 acpi_processor_unregister_performance(policy->cpu);
504 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
508 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
513 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
514 int deadband, int integral) {
515 pid->setpoint = int_tofp(setpoint);
516 pid->deadband = int_tofp(deadband);
517 pid->integral = int_tofp(integral);
518 pid->last_err = int_tofp(setpoint) - int_tofp(busy);
521 static inline void pid_p_gain_set(struct _pid *pid, int percent)
523 pid->p_gain = div_fp(percent, 100);
526 static inline void pid_i_gain_set(struct _pid *pid, int percent)
528 pid->i_gain = div_fp(percent, 100);
531 static inline void pid_d_gain_set(struct _pid *pid, int percent)
533 pid->d_gain = div_fp(percent, 100);
536 static signed int pid_calc(struct _pid *pid, int32_t busy)
539 int32_t pterm, dterm, fp_error;
540 int32_t integral_limit;
542 fp_error = pid->setpoint - busy;
544 if (abs(fp_error) <= pid->deadband)
547 pterm = mul_fp(pid->p_gain, fp_error);
549 pid->integral += fp_error;
552 * We limit the integral here so that it will never
553 * get higher than 30. This prevents it from becoming
554 * too large an input over long periods of time and allows
555 * it to get factored out sooner.
557 * The value of 30 was chosen through experimentation.
559 integral_limit = int_tofp(30);
560 if (pid->integral > integral_limit)
561 pid->integral = integral_limit;
562 if (pid->integral < -integral_limit)
563 pid->integral = -integral_limit;
565 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
566 pid->last_err = fp_error;
568 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
569 result = result + (1 << (FRAC_BITS-1));
570 return (signed int)fp_toint(result);
573 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
575 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
576 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
577 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
579 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
582 static inline void intel_pstate_reset_all_pid(void)
586 for_each_online_cpu(cpu) {
587 if (all_cpu_data[cpu])
588 intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
592 static inline void update_turbo_state(void)
597 cpu = all_cpu_data[0];
598 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
599 global.turbo_disabled =
600 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
601 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
604 static int min_perf_pct_min(void)
606 struct cpudata *cpu = all_cpu_data[0];
608 return DIV_ROUND_UP(cpu->pstate.min_pstate * 100,
609 cpu->pstate.turbo_pstate);
612 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
617 if (!static_cpu_has(X86_FEATURE_EPB))
620 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
624 return (s16)(epb & 0x0f);
627 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
631 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
633 * When hwp_req_data is 0, means that caller didn't read
634 * MSR_HWP_REQUEST, so need to read and get EPP.
637 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
642 epp = (hwp_req_data >> 24) & 0xff;
644 /* When there is no EPP present, HWP uses EPB settings */
645 epp = intel_pstate_get_epb(cpu_data);
651 static int intel_pstate_set_epb(int cpu, s16 pref)
656 if (!static_cpu_has(X86_FEATURE_EPB))
659 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
663 epb = (epb & ~0x0f) | pref;
664 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
670 * EPP/EPB display strings corresponding to EPP index in the
671 * energy_perf_strings[]
673 *-------------------------------------
676 * 2 balance_performance
680 static const char * const energy_perf_strings[] = {
683 "balance_performance",
689 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
694 epp = intel_pstate_get_epp(cpu_data, 0);
698 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
701 * 0x00-0x3F : Performance
702 * 0x40-0x7F : Balance performance
703 * 0x80-0xBF : Balance power
705 * The EPP is a 8 bit value, but our ranges restrict the
706 * value which can be set. Here only using top two bits
709 index = (epp >> 6) + 1;
710 } else if (static_cpu_has(X86_FEATURE_EPB)) {
713 * 0x00-0x03 : Performance
714 * 0x04-0x07 : Balance performance
715 * 0x08-0x0B : Balance power
717 * The EPB is a 4 bit value, but our ranges restrict the
718 * value which can be set. Here only using top two bits
721 index = (epp >> 2) + 1;
727 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
734 epp = cpu_data->epp_default;
736 mutex_lock(&intel_pstate_limits_lock);
738 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
741 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
745 value &= ~GENMASK_ULL(31, 24);
748 * If epp is not default, convert from index into
749 * energy_perf_strings to epp value, by shifting 6
750 * bits left to use only top two bits in epp.
751 * The resultant epp need to shifted by 24 bits to
752 * epp position in MSR_HWP_REQUEST.
755 epp = (pref_index - 1) << 6;
757 value |= (u64)epp << 24;
758 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
761 epp = (pref_index - 1) << 2;
762 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
765 mutex_unlock(&intel_pstate_limits_lock);
770 static ssize_t show_energy_performance_available_preferences(
771 struct cpufreq_policy *policy, char *buf)
776 while (energy_perf_strings[i] != NULL)
777 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
779 ret += sprintf(&buf[ret], "\n");
784 cpufreq_freq_attr_ro(energy_performance_available_preferences);
786 static ssize_t store_energy_performance_preference(
787 struct cpufreq_policy *policy, const char *buf, size_t count)
789 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
790 char str_preference[21];
793 ret = sscanf(buf, "%20s", str_preference);
797 while (energy_perf_strings[i] != NULL) {
798 if (!strcmp(str_preference, energy_perf_strings[i])) {
799 intel_pstate_set_energy_pref_index(cpu_data, i);
808 static ssize_t show_energy_performance_preference(
809 struct cpufreq_policy *policy, char *buf)
811 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
814 preference = intel_pstate_get_energy_pref_index(cpu_data);
818 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
821 cpufreq_freq_attr_rw(energy_performance_preference);
823 static struct freq_attr *hwp_cpufreq_attrs[] = {
824 &energy_performance_preference,
825 &energy_performance_available_preferences,
829 static void intel_pstate_hwp_set(struct cpufreq_policy *policy)
831 int min, hw_min, max, hw_max, cpu;
834 for_each_cpu(cpu, policy->cpus) {
835 struct cpudata *cpu_data = all_cpu_data[cpu];
836 struct perf_limits *perf_limits = &cpu_data->perf_limits;
839 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
840 hw_min = HWP_LOWEST_PERF(cap);
842 hw_max = HWP_GUARANTEED_PERF(cap);
844 hw_max = HWP_HIGHEST_PERF(cap);
846 max = fp_ext_toint(hw_max * perf_limits->max_perf);
847 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
850 min = fp_ext_toint(hw_max * perf_limits->min_perf);
852 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
854 value &= ~HWP_MIN_PERF(~0L);
855 value |= HWP_MIN_PERF(min);
857 value &= ~HWP_MAX_PERF(~0L);
858 value |= HWP_MAX_PERF(max);
860 if (cpu_data->epp_policy == cpu_data->policy)
863 cpu_data->epp_policy = cpu_data->policy;
865 if (cpu_data->epp_saved >= 0) {
866 epp = cpu_data->epp_saved;
867 cpu_data->epp_saved = -EINVAL;
871 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
872 epp = intel_pstate_get_epp(cpu_data, value);
873 cpu_data->epp_powersave = epp;
874 /* If EPP read was failed, then don't try to write */
881 /* skip setting EPP, when saved value is invalid */
882 if (cpu_data->epp_powersave < 0)
886 * No need to restore EPP when it is not zero. This
888 * - Policy is not changed
889 * - user has manually changed
890 * - Error reading EPB
892 epp = intel_pstate_get_epp(cpu_data, value);
896 epp = cpu_data->epp_powersave;
899 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
900 value &= ~GENMASK_ULL(31, 24);
901 value |= (u64)epp << 24;
903 intel_pstate_set_epb(cpu, epp);
906 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
910 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
912 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
917 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
922 static int intel_pstate_resume(struct cpufreq_policy *policy)
927 mutex_lock(&intel_pstate_limits_lock);
929 all_cpu_data[policy->cpu]->epp_policy = 0;
930 intel_pstate_hwp_set(policy);
932 mutex_unlock(&intel_pstate_limits_lock);
937 static void intel_pstate_update_policies(void)
941 for_each_possible_cpu(cpu)
942 cpufreq_update_policy(cpu);
945 /************************** debugfs begin ************************/
946 static int pid_param_set(void *data, u64 val)
949 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
950 intel_pstate_reset_all_pid();
954 static int pid_param_get(void *data, u64 *val)
959 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
961 static struct dentry *debugfs_parent;
966 struct dentry *dentry;
969 static struct pid_param pid_files[] = {
970 {"sample_rate_ms", &pid_params.sample_rate_ms, },
971 {"d_gain_pct", &pid_params.d_gain_pct, },
972 {"i_gain_pct", &pid_params.i_gain_pct, },
973 {"deadband", &pid_params.deadband, },
974 {"setpoint", &pid_params.setpoint, },
975 {"p_gain_pct", &pid_params.p_gain_pct, },
979 static void intel_pstate_debug_expose_params(void)
983 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
984 if (IS_ERR_OR_NULL(debugfs_parent))
987 for (i = 0; pid_files[i].name; i++) {
988 struct dentry *dentry;
990 dentry = debugfs_create_file(pid_files[i].name, 0660,
991 debugfs_parent, pid_files[i].value,
994 pid_files[i].dentry = dentry;
998 static void intel_pstate_debug_hide_params(void)
1002 if (IS_ERR_OR_NULL(debugfs_parent))
1005 for (i = 0; pid_files[i].name; i++) {
1006 debugfs_remove(pid_files[i].dentry);
1007 pid_files[i].dentry = NULL;
1010 debugfs_remove(debugfs_parent);
1011 debugfs_parent = NULL;
1014 /************************** debugfs end ************************/
1016 /************************** sysfs begin ************************/
1017 #define show_one(file_name, object) \
1018 static ssize_t show_##file_name \
1019 (struct kobject *kobj, struct attribute *attr, char *buf) \
1021 return sprintf(buf, "%u\n", global.object); \
1024 static ssize_t intel_pstate_show_status(char *buf);
1025 static int intel_pstate_update_status(const char *buf, size_t size);
1027 static ssize_t show_status(struct kobject *kobj,
1028 struct attribute *attr, char *buf)
1032 mutex_lock(&intel_pstate_driver_lock);
1033 ret = intel_pstate_show_status(buf);
1034 mutex_unlock(&intel_pstate_driver_lock);
1039 static ssize_t store_status(struct kobject *a, struct attribute *b,
1040 const char *buf, size_t count)
1042 char *p = memchr(buf, '\n', count);
1045 mutex_lock(&intel_pstate_driver_lock);
1046 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1047 mutex_unlock(&intel_pstate_driver_lock);
1049 return ret < 0 ? ret : count;
1052 static ssize_t show_turbo_pct(struct kobject *kobj,
1053 struct attribute *attr, char *buf)
1055 struct cpudata *cpu;
1056 int total, no_turbo, turbo_pct;
1059 mutex_lock(&intel_pstate_driver_lock);
1061 if (!driver_registered) {
1062 mutex_unlock(&intel_pstate_driver_lock);
1066 cpu = all_cpu_data[0];
1068 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1069 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1070 turbo_fp = div_fp(no_turbo, total);
1071 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1073 mutex_unlock(&intel_pstate_driver_lock);
1075 return sprintf(buf, "%u\n", turbo_pct);
1078 static ssize_t show_num_pstates(struct kobject *kobj,
1079 struct attribute *attr, char *buf)
1081 struct cpudata *cpu;
1084 mutex_lock(&intel_pstate_driver_lock);
1086 if (!driver_registered) {
1087 mutex_unlock(&intel_pstate_driver_lock);
1091 cpu = all_cpu_data[0];
1092 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1094 mutex_unlock(&intel_pstate_driver_lock);
1096 return sprintf(buf, "%u\n", total);
1099 static ssize_t show_no_turbo(struct kobject *kobj,
1100 struct attribute *attr, char *buf)
1104 mutex_lock(&intel_pstate_driver_lock);
1106 if (!driver_registered) {
1107 mutex_unlock(&intel_pstate_driver_lock);
1111 update_turbo_state();
1112 if (global.turbo_disabled)
1113 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1115 ret = sprintf(buf, "%u\n", global.no_turbo);
1117 mutex_unlock(&intel_pstate_driver_lock);
1122 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
1123 const char *buf, size_t count)
1128 ret = sscanf(buf, "%u", &input);
1132 mutex_lock(&intel_pstate_driver_lock);
1134 if (!driver_registered) {
1135 mutex_unlock(&intel_pstate_driver_lock);
1139 mutex_lock(&intel_pstate_limits_lock);
1141 update_turbo_state();
1142 if (global.turbo_disabled) {
1143 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1144 mutex_unlock(&intel_pstate_limits_lock);
1145 mutex_unlock(&intel_pstate_driver_lock);
1149 global.no_turbo = clamp_t(int, input, 0, 1);
1151 if (global.no_turbo) {
1152 struct cpudata *cpu = all_cpu_data[0];
1153 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1155 /* Squash the global minimum into the permitted range. */
1156 if (global.min_perf_pct > pct)
1157 global.min_perf_pct = pct;
1160 mutex_unlock(&intel_pstate_limits_lock);
1162 intel_pstate_update_policies();
1164 mutex_unlock(&intel_pstate_driver_lock);
1169 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
1170 const char *buf, size_t count)
1175 ret = sscanf(buf, "%u", &input);
1179 mutex_lock(&intel_pstate_driver_lock);
1181 if (!driver_registered) {
1182 mutex_unlock(&intel_pstate_driver_lock);
1186 mutex_lock(&intel_pstate_limits_lock);
1188 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1190 mutex_unlock(&intel_pstate_limits_lock);
1192 intel_pstate_update_policies();
1194 mutex_unlock(&intel_pstate_driver_lock);
1199 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1200 const char *buf, size_t count)
1205 ret = sscanf(buf, "%u", &input);
1209 mutex_lock(&intel_pstate_driver_lock);
1211 if (!driver_registered) {
1212 mutex_unlock(&intel_pstate_driver_lock);
1216 mutex_lock(&intel_pstate_limits_lock);
1218 global.min_perf_pct = clamp_t(int, input,
1219 min_perf_pct_min(), global.max_perf_pct);
1221 mutex_unlock(&intel_pstate_limits_lock);
1223 intel_pstate_update_policies();
1225 mutex_unlock(&intel_pstate_driver_lock);
1230 show_one(max_perf_pct, max_perf_pct);
1231 show_one(min_perf_pct, min_perf_pct);
1233 define_one_global_rw(status);
1234 define_one_global_rw(no_turbo);
1235 define_one_global_rw(max_perf_pct);
1236 define_one_global_rw(min_perf_pct);
1237 define_one_global_ro(turbo_pct);
1238 define_one_global_ro(num_pstates);
1240 static struct attribute *intel_pstate_attributes[] = {
1248 static struct attribute_group intel_pstate_attr_group = {
1249 .attrs = intel_pstate_attributes,
1252 static void __init intel_pstate_sysfs_expose_params(void)
1254 struct kobject *intel_pstate_kobject;
1257 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1258 &cpu_subsys.dev_root->kobj);
1259 if (WARN_ON(!intel_pstate_kobject))
1262 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1267 * If per cpu limits are enforced there are no global limits, so
1268 * return without creating max/min_perf_pct attributes
1273 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1276 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1280 /************************** sysfs end ************************/
1282 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1284 /* First disable HWP notification interrupt as we don't process them */
1285 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1286 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1288 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1289 cpudata->epp_policy = 0;
1290 if (cpudata->epp_default == -EINVAL)
1291 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1294 #define MSR_IA32_POWER_CTL_BIT_EE 19
1296 /* Disable energy efficiency optimization */
1297 static void intel_pstate_disable_ee(int cpu)
1302 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1306 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1307 pr_info("Disabling energy efficiency optimization\n");
1308 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1309 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1313 static int atom_get_min_pstate(void)
1317 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1318 return (value >> 8) & 0x7F;
1321 static int atom_get_max_pstate(void)
1325 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1326 return (value >> 16) & 0x7F;
1329 static int atom_get_turbo_pstate(void)
1333 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1334 return value & 0x7F;
1337 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1343 val = (u64)pstate << 8;
1344 if (global.no_turbo && !global.turbo_disabled)
1345 val |= (u64)1 << 32;
1347 vid_fp = cpudata->vid.min + mul_fp(
1348 int_tofp(pstate - cpudata->pstate.min_pstate),
1349 cpudata->vid.ratio);
1351 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1352 vid = ceiling_fp(vid_fp);
1354 if (pstate > cpudata->pstate.max_pstate)
1355 vid = cpudata->vid.turbo;
1360 static int silvermont_get_scaling(void)
1364 /* Defined in Table 35-6 from SDM (Sept 2015) */
1365 static int silvermont_freq_table[] = {
1366 83300, 100000, 133300, 116700, 80000};
1368 rdmsrl(MSR_FSB_FREQ, value);
1372 return silvermont_freq_table[i];
1375 static int airmont_get_scaling(void)
1379 /* Defined in Table 35-10 from SDM (Sept 2015) */
1380 static int airmont_freq_table[] = {
1381 83300, 100000, 133300, 116700, 80000,
1382 93300, 90000, 88900, 87500};
1384 rdmsrl(MSR_FSB_FREQ, value);
1388 return airmont_freq_table[i];
1391 static void atom_get_vid(struct cpudata *cpudata)
1395 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1396 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1397 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1398 cpudata->vid.ratio = div_fp(
1399 cpudata->vid.max - cpudata->vid.min,
1400 int_tofp(cpudata->pstate.max_pstate -
1401 cpudata->pstate.min_pstate));
1403 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1404 cpudata->vid.turbo = value & 0x7f;
1407 static int core_get_min_pstate(void)
1411 rdmsrl(MSR_PLATFORM_INFO, value);
1412 return (value >> 40) & 0xFF;
1415 static int core_get_max_pstate_physical(void)
1419 rdmsrl(MSR_PLATFORM_INFO, value);
1420 return (value >> 8) & 0xFF;
1423 static int core_get_tdp_ratio(u64 plat_info)
1425 /* Check how many TDP levels present */
1426 if (plat_info & 0x600000000) {
1432 /* Get the TDP level (0, 1, 2) to get ratios */
1433 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1437 /* TDP MSR are continuous starting at 0x648 */
1438 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1439 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1443 /* For level 1 and 2, bits[23:16] contain the ratio */
1444 if (tdp_ctrl & 0x03)
1447 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1448 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1450 return (int)tdp_ratio;
1456 static int core_get_max_pstate(void)
1464 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1465 max_pstate = (plat_info >> 8) & 0xFF;
1467 tdp_ratio = core_get_tdp_ratio(plat_info);
1472 /* Turbo activation ratio is not used on HWP platforms */
1476 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1480 /* Do some sanity checking for safety */
1481 tar_levels = tar & 0xff;
1482 if (tdp_ratio - 1 == tar_levels) {
1483 max_pstate = tar_levels;
1484 pr_debug("max_pstate=TAC %x\n", max_pstate);
1491 static int core_get_turbo_pstate(void)
1496 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1497 nont = core_get_max_pstate();
1498 ret = (value) & 255;
1504 static inline int core_get_scaling(void)
1509 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1513 val = (u64)pstate << 8;
1514 if (global.no_turbo && !global.turbo_disabled)
1515 val |= (u64)1 << 32;
1520 static int knl_get_turbo_pstate(void)
1525 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1526 nont = core_get_max_pstate();
1527 ret = (((value) >> 8) & 0xFF);
1533 static struct cpu_defaults core_params = {
1535 .sample_rate_ms = 10,
1543 .get_max = core_get_max_pstate,
1544 .get_max_physical = core_get_max_pstate_physical,
1545 .get_min = core_get_min_pstate,
1546 .get_turbo = core_get_turbo_pstate,
1547 .get_scaling = core_get_scaling,
1548 .get_val = core_get_val,
1549 .get_target_pstate = get_target_pstate_use_performance,
1553 static const struct cpu_defaults silvermont_params = {
1555 .sample_rate_ms = 10,
1563 .get_max = atom_get_max_pstate,
1564 .get_max_physical = atom_get_max_pstate,
1565 .get_min = atom_get_min_pstate,
1566 .get_turbo = atom_get_turbo_pstate,
1567 .get_val = atom_get_val,
1568 .get_scaling = silvermont_get_scaling,
1569 .get_vid = atom_get_vid,
1570 .get_target_pstate = get_target_pstate_use_cpu_load,
1574 static const struct cpu_defaults airmont_params = {
1576 .sample_rate_ms = 10,
1584 .get_max = atom_get_max_pstate,
1585 .get_max_physical = atom_get_max_pstate,
1586 .get_min = atom_get_min_pstate,
1587 .get_turbo = atom_get_turbo_pstate,
1588 .get_val = atom_get_val,
1589 .get_scaling = airmont_get_scaling,
1590 .get_vid = atom_get_vid,
1591 .get_target_pstate = get_target_pstate_use_cpu_load,
1595 static const struct cpu_defaults knl_params = {
1597 .sample_rate_ms = 10,
1605 .get_max = core_get_max_pstate,
1606 .get_max_physical = core_get_max_pstate_physical,
1607 .get_min = core_get_min_pstate,
1608 .get_turbo = knl_get_turbo_pstate,
1609 .get_scaling = core_get_scaling,
1610 .get_val = core_get_val,
1611 .get_target_pstate = get_target_pstate_use_performance,
1615 static const struct cpu_defaults bxt_params = {
1617 .sample_rate_ms = 10,
1625 .get_max = core_get_max_pstate,
1626 .get_max_physical = core_get_max_pstate_physical,
1627 .get_min = core_get_min_pstate,
1628 .get_turbo = core_get_turbo_pstate,
1629 .get_scaling = core_get_scaling,
1630 .get_val = core_get_val,
1631 .get_target_pstate = get_target_pstate_use_cpu_load,
1635 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
1637 int max_perf = cpu->pstate.turbo_pstate;
1640 struct perf_limits *perf_limits = &cpu->perf_limits;
1642 if (global.no_turbo || global.turbo_disabled)
1643 max_perf = cpu->pstate.max_pstate;
1646 * performance can be limited by user through sysfs, by cpufreq
1647 * policy, or by cpu specific default values determined through
1650 max_perf_adj = fp_ext_toint(max_perf * perf_limits->max_perf);
1651 *max = clamp_t(int, max_perf_adj,
1652 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
1654 min_perf = fp_ext_toint(max_perf * perf_limits->min_perf);
1655 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
1658 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1660 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1661 cpu->pstate.current_pstate = pstate;
1663 * Generally, there is no guarantee that this code will always run on
1664 * the CPU being updated, so force the register update to run on the
1667 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1668 pstate_funcs.get_val(cpu, pstate));
1671 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1673 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1676 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1678 int min_pstate, max_pstate;
1680 update_turbo_state();
1681 intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate);
1682 intel_pstate_set_pstate(cpu, max_pstate);
1685 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1687 cpu->pstate.min_pstate = pstate_funcs.get_min();
1688 cpu->pstate.max_pstate = pstate_funcs.get_max();
1689 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1690 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1691 cpu->pstate.scaling = pstate_funcs.get_scaling();
1692 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1693 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1695 if (pstate_funcs.get_vid)
1696 pstate_funcs.get_vid(cpu);
1698 intel_pstate_set_min_pstate(cpu);
1701 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1703 struct sample *sample = &cpu->sample;
1705 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1708 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1711 unsigned long flags;
1714 local_irq_save(flags);
1715 rdmsrl(MSR_IA32_APERF, aperf);
1716 rdmsrl(MSR_IA32_MPERF, mperf);
1718 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1719 local_irq_restore(flags);
1722 local_irq_restore(flags);
1724 cpu->last_sample_time = cpu->sample.time;
1725 cpu->sample.time = time;
1726 cpu->sample.aperf = aperf;
1727 cpu->sample.mperf = mperf;
1728 cpu->sample.tsc = tsc;
1729 cpu->sample.aperf -= cpu->prev_aperf;
1730 cpu->sample.mperf -= cpu->prev_mperf;
1731 cpu->sample.tsc -= cpu->prev_tsc;
1733 cpu->prev_aperf = aperf;
1734 cpu->prev_mperf = mperf;
1735 cpu->prev_tsc = tsc;
1737 * First time this function is invoked in a given cycle, all of the
1738 * previous sample data fields are equal to zero or stale and they must
1739 * be populated with meaningful numbers for things to work, so assume
1740 * that sample.time will always be reset before setting the utilization
1741 * update hook and make the caller skip the sample then.
1743 return !!cpu->last_sample_time;
1746 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1748 return mul_ext_fp(cpu->sample.core_avg_perf,
1749 cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1752 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1754 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1755 cpu->sample.core_avg_perf);
1758 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1760 struct sample *sample = &cpu->sample;
1761 int32_t busy_frac, boost;
1762 int target, avg_pstate;
1764 busy_frac = div_fp(sample->mperf, sample->tsc);
1766 boost = cpu->iowait_boost;
1767 cpu->iowait_boost >>= 1;
1769 if (busy_frac < boost)
1772 sample->busy_scaled = busy_frac * 100;
1774 target = global.no_turbo || global.turbo_disabled ?
1775 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1776 target += target >> 2;
1777 target = mul_fp(target, busy_frac);
1778 if (target < cpu->pstate.min_pstate)
1779 target = cpu->pstate.min_pstate;
1782 * If the average P-state during the previous cycle was higher than the
1783 * current target, add 50% of the difference to the target to reduce
1784 * possible performance oscillations and offset possible performance
1785 * loss related to moving the workload from one CPU to another within
1788 avg_pstate = get_avg_pstate(cpu);
1789 if (avg_pstate > target)
1790 target += (avg_pstate - target) >> 1;
1795 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1797 int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1801 * perf_scaled is the ratio of the average P-state during the last
1802 * sampling period to the P-state requested last time (in percent).
1804 * That measures the system's response to the previous P-state
1807 max_pstate = cpu->pstate.max_pstate_physical;
1808 current_pstate = cpu->pstate.current_pstate;
1809 perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1810 div_fp(100 * max_pstate, current_pstate));
1813 * Since our utilization update callback will not run unless we are
1814 * in C0, check if the actual elapsed time is significantly greater (3x)
1815 * than our sample interval. If it is, then we were idle for a long
1816 * enough period of time to adjust our performance metric.
1818 duration_ns = cpu->sample.time - cpu->last_sample_time;
1819 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1820 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1821 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1823 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1824 if (sample_ratio < int_tofp(1))
1828 cpu->sample.busy_scaled = perf_scaled;
1829 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1832 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1834 int max_perf, min_perf;
1836 intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1837 pstate = clamp_t(int, pstate, min_perf, max_perf);
1841 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1843 if (pstate == cpu->pstate.current_pstate)
1846 cpu->pstate.current_pstate = pstate;
1847 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1850 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1852 int from, target_pstate;
1853 struct sample *sample;
1855 from = cpu->pstate.current_pstate;
1857 target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ?
1858 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu);
1860 update_turbo_state();
1862 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1863 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1864 intel_pstate_update_pstate(cpu, target_pstate);
1866 sample = &cpu->sample;
1867 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1868 fp_toint(sample->busy_scaled),
1870 cpu->pstate.current_pstate,
1874 get_avg_frequency(cpu),
1875 fp_toint(cpu->iowait_boost * 100));
1878 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1881 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1884 if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) {
1885 if (flags & SCHED_CPUFREQ_IOWAIT) {
1886 cpu->iowait_boost = int_tofp(1);
1887 } else if (cpu->iowait_boost) {
1888 /* Clear iowait_boost if the CPU may have been idle. */
1889 delta_ns = time - cpu->last_update;
1890 if (delta_ns > TICK_NSEC)
1891 cpu->iowait_boost = 0;
1893 cpu->last_update = time;
1896 delta_ns = time - cpu->sample.time;
1897 if ((s64)delta_ns >= pid_params.sample_rate_ns) {
1898 bool sample_taken = intel_pstate_sample(cpu, time);
1901 intel_pstate_calc_avg_perf(cpu);
1903 intel_pstate_adjust_busy_pstate(cpu);
1908 #define ICPU(model, policy) \
1909 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1910 (unsigned long)&policy }
1912 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1913 ICPU(INTEL_FAM6_SANDYBRIDGE, core_params),
1914 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params),
1915 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params),
1916 ICPU(INTEL_FAM6_IVYBRIDGE, core_params),
1917 ICPU(INTEL_FAM6_HASWELL_CORE, core_params),
1918 ICPU(INTEL_FAM6_BROADWELL_CORE, core_params),
1919 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params),
1920 ICPU(INTEL_FAM6_HASWELL_X, core_params),
1921 ICPU(INTEL_FAM6_HASWELL_ULT, core_params),
1922 ICPU(INTEL_FAM6_HASWELL_GT3E, core_params),
1923 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params),
1924 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params),
1925 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params),
1926 ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1927 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params),
1928 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1929 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params),
1930 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_params),
1931 ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_params),
1934 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1936 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1937 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1938 ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1939 ICPU(INTEL_FAM6_SKYLAKE_X, core_params),
1943 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1944 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_params),
1948 static int intel_pstate_init_cpu(unsigned int cpunum)
1950 struct cpudata *cpu;
1952 cpu = all_cpu_data[cpunum];
1955 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1959 all_cpu_data[cpunum] = cpu;
1961 cpu->epp_default = -EINVAL;
1962 cpu->epp_powersave = -EINVAL;
1963 cpu->epp_saved = -EINVAL;
1966 cpu = all_cpu_data[cpunum];
1971 const struct x86_cpu_id *id;
1973 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1975 intel_pstate_disable_ee(cpunum);
1977 intel_pstate_hwp_enable(cpu);
1978 pid_params.sample_rate_ms = 50;
1979 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
1982 intel_pstate_get_cpu_pstates(cpu);
1984 intel_pstate_busy_pid_reset(cpu);
1986 pr_debug("controlling: cpu %d\n", cpunum);
1991 static unsigned int intel_pstate_get(unsigned int cpu_num)
1993 struct cpudata *cpu = all_cpu_data[cpu_num];
1995 return cpu ? get_avg_frequency(cpu) : 0;
1998 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2000 struct cpudata *cpu = all_cpu_data[cpu_num];
2002 if (cpu->update_util_set)
2005 /* Prevent intel_pstate_update_util() from using stale data. */
2006 cpu->sample.time = 0;
2007 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2008 intel_pstate_update_util);
2009 cpu->update_util_set = true;
2012 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2014 struct cpudata *cpu_data = all_cpu_data[cpu];
2016 if (!cpu_data->update_util_set)
2019 cpufreq_remove_update_util_hook(cpu);
2020 cpu_data->update_util_set = false;
2021 synchronize_sched();
2024 static int intel_pstate_get_max_freq(struct cpudata *cpu)
2026 return global.turbo_disabled || global.no_turbo ?
2027 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2030 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
2031 struct cpudata *cpu)
2033 struct perf_limits *limits = &cpu->perf_limits;
2034 int max_freq = intel_pstate_get_max_freq(cpu);
2035 int32_t max_policy_perf, min_policy_perf;
2037 max_policy_perf = div_ext_fp(policy->max, max_freq);
2038 max_policy_perf = clamp_t(int32_t, max_policy_perf, 0, int_ext_tofp(1));
2039 if (policy->max == policy->min) {
2040 min_policy_perf = max_policy_perf;
2042 min_policy_perf = div_ext_fp(policy->min, max_freq);
2043 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2044 0, max_policy_perf);
2047 /* Normalize user input to [min_perf, max_perf] */
2048 if (per_cpu_limits) {
2049 limits->min_perf = min_policy_perf;
2050 limits->max_perf = max_policy_perf;
2052 int32_t global_min, global_max;
2054 /* Global limits are in percent of the maximum turbo P-state. */
2055 global_max = percent_ext_fp(global.max_perf_pct);
2056 global_min = percent_ext_fp(global.min_perf_pct);
2057 if (max_freq != cpu->pstate.turbo_freq) {
2058 int32_t turbo_factor;
2060 turbo_factor = div_ext_fp(cpu->pstate.turbo_pstate,
2061 cpu->pstate.max_pstate);
2062 global_min = mul_ext_fp(global_min, turbo_factor);
2063 global_max = mul_ext_fp(global_max, turbo_factor);
2065 global_min = clamp_t(int32_t, global_min, 0, global_max);
2067 limits->min_perf = max(min_policy_perf, global_min);
2068 limits->min_perf = min(limits->min_perf, max_policy_perf);
2069 limits->max_perf = min(max_policy_perf, global_max);
2070 limits->max_perf = max(min_policy_perf, limits->max_perf);
2072 /* Make sure min_perf <= max_perf */
2073 limits->min_perf = min(limits->min_perf, limits->max_perf);
2076 limits->max_perf = round_up(limits->max_perf, EXT_FRAC_BITS);
2077 limits->min_perf = round_up(limits->min_perf, EXT_FRAC_BITS);
2079 pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
2080 fp_ext_toint(limits->max_perf * 100),
2081 fp_ext_toint(limits->min_perf * 100));
2084 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2086 struct cpudata *cpu;
2088 if (!policy->cpuinfo.max_freq)
2091 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2092 policy->cpuinfo.max_freq, policy->max);
2094 cpu = all_cpu_data[policy->cpu];
2095 cpu->policy = policy->policy;
2097 mutex_lock(&intel_pstate_limits_lock);
2099 intel_pstate_update_perf_limits(policy, cpu);
2101 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2103 * NOHZ_FULL CPUs need this as the governor callback may not
2104 * be invoked on them.
2106 intel_pstate_clear_update_util_hook(policy->cpu);
2107 intel_pstate_max_within_limits(cpu);
2110 intel_pstate_set_update_util_hook(policy->cpu);
2113 intel_pstate_hwp_set(policy);
2115 mutex_unlock(&intel_pstate_limits_lock);
2120 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
2121 struct cpudata *cpu)
2123 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2124 policy->max < policy->cpuinfo.max_freq &&
2125 policy->max > cpu->pstate.max_freq) {
2126 pr_debug("policy->max > max non turbo frequency\n");
2127 policy->max = policy->cpuinfo.max_freq;
2131 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2133 struct cpudata *cpu = all_cpu_data[policy->cpu];
2135 update_turbo_state();
2136 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2137 intel_pstate_get_max_freq(cpu));
2139 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2140 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2143 intel_pstate_adjust_policy_max(policy, cpu);
2148 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2150 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2153 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2155 pr_debug("CPU %d exiting\n", policy->cpu);
2157 intel_pstate_clear_update_util_hook(policy->cpu);
2159 intel_pstate_hwp_save_state(policy);
2161 intel_cpufreq_stop_cpu(policy);
2164 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2166 intel_pstate_exit_perf_limits(policy);
2168 policy->fast_switch_possible = false;
2173 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2175 struct cpudata *cpu;
2178 rc = intel_pstate_init_cpu(policy->cpu);
2182 cpu = all_cpu_data[policy->cpu];
2184 cpu->perf_limits.max_perf = int_ext_tofp(1);
2185 cpu->perf_limits.min_perf = 0;
2187 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2188 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2190 /* cpuinfo and default policy values */
2191 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2192 update_turbo_state();
2193 policy->cpuinfo.max_freq = global.turbo_disabled ?
2194 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2195 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2197 intel_pstate_init_acpi_perf_limits(policy);
2198 cpumask_set_cpu(policy->cpu, policy->cpus);
2200 policy->fast_switch_possible = true;
2205 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2207 int ret = __intel_pstate_cpu_init(policy);
2212 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2213 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
2214 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2216 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2221 static struct cpufreq_driver intel_pstate = {
2222 .flags = CPUFREQ_CONST_LOOPS,
2223 .verify = intel_pstate_verify_policy,
2224 .setpolicy = intel_pstate_set_policy,
2225 .suspend = intel_pstate_hwp_save_state,
2226 .resume = intel_pstate_resume,
2227 .get = intel_pstate_get,
2228 .init = intel_pstate_cpu_init,
2229 .exit = intel_pstate_cpu_exit,
2230 .stop_cpu = intel_pstate_stop_cpu,
2231 .name = "intel_pstate",
2234 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2236 struct cpudata *cpu = all_cpu_data[policy->cpu];
2238 update_turbo_state();
2239 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2240 intel_pstate_get_max_freq(cpu));
2242 intel_pstate_adjust_policy_max(policy, cpu);
2244 intel_pstate_update_perf_limits(policy, cpu);
2249 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2250 unsigned int target_freq,
2251 unsigned int relation)
2253 struct cpudata *cpu = all_cpu_data[policy->cpu];
2254 struct cpufreq_freqs freqs;
2257 update_turbo_state();
2259 freqs.old = policy->cur;
2260 freqs.new = target_freq;
2262 cpufreq_freq_transition_begin(policy, &freqs);
2264 case CPUFREQ_RELATION_L:
2265 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2267 case CPUFREQ_RELATION_H:
2268 target_pstate = freqs.new / cpu->pstate.scaling;
2271 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2274 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2275 if (target_pstate != cpu->pstate.current_pstate) {
2276 cpu->pstate.current_pstate = target_pstate;
2277 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2278 pstate_funcs.get_val(cpu, target_pstate));
2280 freqs.new = target_pstate * cpu->pstate.scaling;
2281 cpufreq_freq_transition_end(policy, &freqs, false);
2286 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2287 unsigned int target_freq)
2289 struct cpudata *cpu = all_cpu_data[policy->cpu];
2292 update_turbo_state();
2294 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2295 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2296 intel_pstate_update_pstate(cpu, target_pstate);
2297 return target_pstate * cpu->pstate.scaling;
2300 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2302 int ret = __intel_pstate_cpu_init(policy);
2307 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2308 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2309 policy->cur = policy->cpuinfo.min_freq;
2314 static struct cpufreq_driver intel_cpufreq = {
2315 .flags = CPUFREQ_CONST_LOOPS,
2316 .verify = intel_cpufreq_verify_policy,
2317 .target = intel_cpufreq_target,
2318 .fast_switch = intel_cpufreq_fast_switch,
2319 .init = intel_cpufreq_cpu_init,
2320 .exit = intel_pstate_cpu_exit,
2321 .stop_cpu = intel_cpufreq_stop_cpu,
2322 .name = "intel_cpufreq",
2325 static struct cpufreq_driver *intel_pstate_driver = &intel_pstate;
2327 static void intel_pstate_driver_cleanup(void)
2332 for_each_online_cpu(cpu) {
2333 if (all_cpu_data[cpu]) {
2334 if (intel_pstate_driver == &intel_pstate)
2335 intel_pstate_clear_update_util_hook(cpu);
2337 kfree(all_cpu_data[cpu]);
2338 all_cpu_data[cpu] = NULL;
2344 static int intel_pstate_register_driver(void)
2348 memset(&global, 0, sizeof(global));
2349 global.max_perf_pct = 100;
2351 ret = cpufreq_register_driver(intel_pstate_driver);
2353 intel_pstate_driver_cleanup();
2357 global.min_perf_pct = min_perf_pct_min();
2359 mutex_lock(&intel_pstate_limits_lock);
2360 driver_registered = true;
2361 mutex_unlock(&intel_pstate_limits_lock);
2363 if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2364 pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2365 intel_pstate_debug_expose_params();
2370 static int intel_pstate_unregister_driver(void)
2375 if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2376 pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2377 intel_pstate_debug_hide_params();
2379 mutex_lock(&intel_pstate_limits_lock);
2380 driver_registered = false;
2381 mutex_unlock(&intel_pstate_limits_lock);
2383 cpufreq_unregister_driver(intel_pstate_driver);
2384 intel_pstate_driver_cleanup();
2389 static ssize_t intel_pstate_show_status(char *buf)
2391 if (!driver_registered)
2392 return sprintf(buf, "off\n");
2394 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2395 "active" : "passive");
2398 static int intel_pstate_update_status(const char *buf, size_t size)
2402 if (size == 3 && !strncmp(buf, "off", size))
2403 return driver_registered ?
2404 intel_pstate_unregister_driver() : -EINVAL;
2406 if (size == 6 && !strncmp(buf, "active", size)) {
2407 if (driver_registered) {
2408 if (intel_pstate_driver == &intel_pstate)
2411 ret = intel_pstate_unregister_driver();
2416 intel_pstate_driver = &intel_pstate;
2417 return intel_pstate_register_driver();
2420 if (size == 7 && !strncmp(buf, "passive", size)) {
2421 if (driver_registered) {
2422 if (intel_pstate_driver != &intel_pstate)
2425 ret = intel_pstate_unregister_driver();
2430 intel_pstate_driver = &intel_cpufreq;
2431 return intel_pstate_register_driver();
2437 static int no_load __initdata;
2438 static int no_hwp __initdata;
2439 static int hwp_only __initdata;
2440 static unsigned int force_load __initdata;
2442 static int __init intel_pstate_msrs_not_valid(void)
2444 if (!pstate_funcs.get_max() ||
2445 !pstate_funcs.get_min() ||
2446 !pstate_funcs.get_turbo())
2452 static void __init copy_pid_params(struct pstate_adjust_policy *policy)
2454 pid_params.sample_rate_ms = policy->sample_rate_ms;
2455 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
2456 pid_params.p_gain_pct = policy->p_gain_pct;
2457 pid_params.i_gain_pct = policy->i_gain_pct;
2458 pid_params.d_gain_pct = policy->d_gain_pct;
2459 pid_params.deadband = policy->deadband;
2460 pid_params.setpoint = policy->setpoint;
2464 static void intel_pstate_use_acpi_profile(void)
2466 switch (acpi_gbl_FADT.preferred_profile) {
2469 case PM_APPLIANCE_PC:
2471 case PM_WORKSTATION:
2472 pstate_funcs.get_target_pstate =
2473 get_target_pstate_use_cpu_load;
2477 static void intel_pstate_use_acpi_profile(void)
2482 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2484 pstate_funcs.get_max = funcs->get_max;
2485 pstate_funcs.get_max_physical = funcs->get_max_physical;
2486 pstate_funcs.get_min = funcs->get_min;
2487 pstate_funcs.get_turbo = funcs->get_turbo;
2488 pstate_funcs.get_scaling = funcs->get_scaling;
2489 pstate_funcs.get_val = funcs->get_val;
2490 pstate_funcs.get_vid = funcs->get_vid;
2491 pstate_funcs.get_target_pstate = funcs->get_target_pstate;
2493 intel_pstate_use_acpi_profile();
2498 static bool __init intel_pstate_no_acpi_pss(void)
2502 for_each_possible_cpu(i) {
2504 union acpi_object *pss;
2505 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2506 struct acpi_processor *pr = per_cpu(processors, i);
2511 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2512 if (ACPI_FAILURE(status))
2515 pss = buffer.pointer;
2516 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2527 static bool __init intel_pstate_has_acpi_ppc(void)
2531 for_each_possible_cpu(i) {
2532 struct acpi_processor *pr = per_cpu(processors, i);
2536 if (acpi_has_method(pr->handle, "_PPC"))
2547 struct hw_vendor_info {
2549 char oem_id[ACPI_OEM_ID_SIZE];
2550 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
2554 /* Hardware vendor-specific info that has its own power management modes */
2555 static struct hw_vendor_info vendor_info[] __initdata = {
2556 {1, "HP ", "ProLiant", PSS},
2557 {1, "ORACLE", "X4-2 ", PPC},
2558 {1, "ORACLE", "X4-2L ", PPC},
2559 {1, "ORACLE", "X4-2B ", PPC},
2560 {1, "ORACLE", "X3-2 ", PPC},
2561 {1, "ORACLE", "X3-2L ", PPC},
2562 {1, "ORACLE", "X3-2B ", PPC},
2563 {1, "ORACLE", "X4470M2 ", PPC},
2564 {1, "ORACLE", "X4270M3 ", PPC},
2565 {1, "ORACLE", "X4270M2 ", PPC},
2566 {1, "ORACLE", "X4170M2 ", PPC},
2567 {1, "ORACLE", "X4170 M3", PPC},
2568 {1, "ORACLE", "X4275 M3", PPC},
2569 {1, "ORACLE", "X6-2 ", PPC},
2570 {1, "ORACLE", "Sudbury ", PPC},
2574 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2576 struct acpi_table_header hdr;
2577 struct hw_vendor_info *v_info;
2578 const struct x86_cpu_id *id;
2581 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2583 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2584 if ( misc_pwr & (1 << 8))
2588 if (acpi_disabled ||
2589 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
2592 for (v_info = vendor_info; v_info->valid; v_info++) {
2593 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
2594 !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2595 ACPI_OEM_TABLE_ID_SIZE))
2596 switch (v_info->oem_pwr_table) {
2598 return intel_pstate_no_acpi_pss();
2600 return intel_pstate_has_acpi_ppc() &&
2608 static void intel_pstate_request_control_from_smm(void)
2611 * It may be unsafe to request P-states control from SMM if _PPC support
2612 * has not been enabled.
2615 acpi_processor_pstate_control();
2617 #else /* CONFIG_ACPI not enabled */
2618 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2619 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2620 static inline void intel_pstate_request_control_from_smm(void) {}
2621 #endif /* CONFIG_ACPI */
2623 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2624 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2628 static int __init intel_pstate_init(void)
2635 if (x86_match_cpu(hwp_support_ids)) {
2636 copy_cpu_funcs(&core_params.funcs);
2638 pstate_funcs.get_target_pstate = get_target_pstate_use_cpu_load;
2641 intel_pstate.attr = hwp_cpufreq_attrs;
2642 goto hwp_cpu_matched;
2645 const struct x86_cpu_id *id;
2646 struct cpu_defaults *cpu_def;
2648 id = x86_match_cpu(intel_pstate_cpu_ids);
2652 cpu_def = (struct cpu_defaults *)id->driver_data;
2654 copy_pid_params(&cpu_def->pid_policy);
2655 copy_cpu_funcs(&cpu_def->funcs);
2658 if (intel_pstate_msrs_not_valid())
2663 * The Intel pstate driver will be ignored if the platform
2664 * firmware has its own power management modes.
2666 if (intel_pstate_platform_pwr_mgmt_exists())
2669 if (!hwp_active && hwp_only)
2672 pr_info("Intel P-state driver initializing\n");
2674 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2678 intel_pstate_request_control_from_smm();
2680 intel_pstate_sysfs_expose_params();
2682 mutex_lock(&intel_pstate_driver_lock);
2683 rc = intel_pstate_register_driver();
2684 mutex_unlock(&intel_pstate_driver_lock);
2689 pr_info("HWP enabled\n");
2693 device_initcall(intel_pstate_init);
2695 static int __init intel_pstate_setup(char *str)
2700 if (!strcmp(str, "disable")) {
2702 } else if (!strcmp(str, "passive")) {
2703 pr_info("Passive mode enabled\n");
2704 intel_pstate_driver = &intel_cpufreq;
2707 if (!strcmp(str, "no_hwp")) {
2708 pr_info("HWP disabled\n");
2711 if (!strcmp(str, "force"))
2713 if (!strcmp(str, "hwp_only"))
2715 if (!strcmp(str, "per_cpu_perf_limits"))
2716 per_cpu_limits = true;
2719 if (!strcmp(str, "support_acpi_ppc"))
2725 early_param("intel_pstate", intel_pstate_setup);
2727 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2728 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2729 MODULE_LICENSE("GPL");